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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:37:50.5214 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8945d385-c3ad-4b0c-a44b-08db3c45cdc4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4202 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407508978100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" rangeset_{xxx}_range() functions are invoked with 'start' and 'size' as arguments which are either 'uint64_t' or 'paddr_t'. However, the function accepts 'unsigned long' for 'start' and 'size'. 'unsigned long' is 32 bits = for Arm32. Thus, there is an implicit downcasting from 'uint64_t'/'paddr_t' to 'unsigned long' when invoking rangeset_{xxx}_range(). So, it may seem there is a possibility of lose of data due to truncation. In reality, 'start' and 'size' are always page aligned. And Arm32 currently supports 40 bits as the width of physical address. So if the addresses are page aligned, the last 12 bits contain zeroes. Thus, we could instead pass page frame number which will contain 28 bits (4= 0-12 on Arm32) and this can be represented using 'unsigned long'. On Arm64, this change will not induce any adverse side effect as the width = of physical address is 48 bits. Thus, the width of 'gfn' (ie 48 - 12 =3D 36) c= an be represented using 'unsigned long' (which is 64 bits wide). Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall Reviewed-by: Michal Orzel --- Changes from - v3 - 1. Extracted the patch from https://lists.xenproject.org/archives/html= /xen-devel/2023-02/msg00657.html and added it to this series. 2. Modified add_ext_regions(). This accepts a frame number instead of physi= cal address. v4 - 1. Reworded the commit message to use Arm32/Arm64 (32-bit/64-bit Arm architecture). 2. Replaced pfn with gfn to denote guest frame number in add_ext_regions(). 3. Use pfn_to_paddr() to return a physical address from the guest frame num= ber. xen/arch/arm/domain_build.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 4f9d4f9d88..c8f08d8ee2 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1500,10 +1500,13 @@ static int __init make_resv_memory_node(const struc= t domain *d, return res; } =20 -static int __init add_ext_regions(unsigned long s, unsigned long e, void *= data) +static int __init add_ext_regions(unsigned long s_gfn, unsigned long e_gfn, + void *data) { struct meminfo *ext_regions =3D data; paddr_t start, size; + paddr_t s =3D pfn_to_paddr(s_gfn); + paddr_t e =3D pfn_to_paddr(e_gfn); =20 if ( ext_regions->nr_banks >=3D ARRAY_SIZE(ext_regions->bank) ) return 0; @@ -1566,7 +1569,8 @@ static int __init find_unallocated_memory(const struc= t kernel_info *kinfo, { start =3D bootinfo.mem.bank[i].start; end =3D bootinfo.mem.bank[i].start + bootinfo.mem.bank[i].size; - res =3D rangeset_add_range(unalloc_mem, start, end - 1); + res =3D rangeset_add_range(unalloc_mem, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to add: %#"PRIpaddr"->%#"PRIpaddr"\n= ", @@ -1580,7 +1584,8 @@ static int __init find_unallocated_memory(const struc= t kernel_info *kinfo, { start =3D assign_mem->bank[i].start; end =3D assign_mem->bank[i].start + assign_mem->bank[i].size; - res =3D rangeset_remove_range(unalloc_mem, start, end - 1); + res =3D rangeset_remove_range(unalloc_mem, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr= "\n", @@ -1595,7 +1600,8 @@ static int __init find_unallocated_memory(const struc= t kernel_info *kinfo, start =3D bootinfo.reserved_mem.bank[i].start; end =3D bootinfo.reserved_mem.bank[i].start + bootinfo.reserved_mem.bank[i].size; - res =3D rangeset_remove_range(unalloc_mem, start, end - 1); + res =3D rangeset_remove_range(unalloc_mem, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr= "\n", @@ -1607,7 +1613,7 @@ static int __init find_unallocated_memory(const struc= t kernel_info *kinfo, /* Remove grant table region */ start =3D kinfo->gnttab_start; end =3D kinfo->gnttab_start + kinfo->gnttab_size; - res =3D rangeset_remove_range(unalloc_mem, start, end - 1); + res =3D rangeset_remove_range(unalloc_mem, PFN_DOWN(start), PFN_DOWN(e= nd - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1617,7 +1623,7 @@ static int __init find_unallocated_memory(const struc= t kernel_info *kinfo, =20 start =3D 0; end =3D (1ULL << p2m_ipa_bits) - 1; - res =3D rangeset_report_ranges(unalloc_mem, start, end, + res =3D rangeset_report_ranges(unalloc_mem, PFN_DOWN(start), PFN_DOWN(= end), add_ext_regions, ext_regions); if ( res ) ext_regions->nr_banks =3D 0; @@ -1639,7 +1645,7 @@ static int __init handle_pci_range(const struct dt_de= vice_node *dev, =20 start =3D addr & PAGE_MASK; end =3D PAGE_ALIGN(addr + len); - res =3D rangeset_remove_range(mem_holes, start, end - 1); + res =3D rangeset_remove_range(mem_holes, PFN_DOWN(start), PFN_DOWN(end= - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1677,7 +1683,7 @@ static int __init find_memory_holes(const struct kern= el_info *kinfo, /* Start with maximum possible addressable physical memory range */ start =3D 0; end =3D (1ULL << p2m_ipa_bits) - 1; - res =3D rangeset_add_range(mem_holes, start, end); + res =3D rangeset_add_range(mem_holes, PFN_DOWN(start), PFN_DOWN(end)); if ( res ) { printk(XENLOG_ERR "Failed to add: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1708,7 +1714,8 @@ static int __init find_memory_holes(const struct kern= el_info *kinfo, =20 start =3D addr & PAGE_MASK; end =3D PAGE_ALIGN(addr + size); - res =3D rangeset_remove_range(mem_holes, start, end - 1); + res =3D rangeset_remove_range(mem_holes, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIp= addr"\n", @@ -1735,7 +1742,7 @@ static int __init find_memory_holes(const struct kern= el_info *kinfo, =20 start =3D 0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:37:55.3350 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56f16cf2-22ed-4bf8-c163-08db3c45d0a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4343 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407508560100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DT functions (dt_read_number(), device_tree_get_reg(), fdt_get_mem_rsv(= )) currently accept or return 64-bit values. In future when we support 32-bit physical address, these DT functions are expected to accept/return 32-bit or 64-bit values (depending on the width of physical address). Also, we wish to detect if any truncation has occurred (i.e. while parsing 32-bit physical addresses from 64-bit values read from = DT). device_tree_get_reg() should now be able to return paddr_t. This is invoked= by various callers to get DT address and size. For fdt_get_mem_rsv(), we have introduced a wrapper named fdt_get_mem_rsv_paddr() which will invoke fdt_get_mem_rsv() and translate uint64_t to paddr_t. The reason being we cannot modify fdt_get_mem_rsv() as= it has been imported from external source. For dt_read_number(), we have also introduced a wrapper named dt_read_paddr= () dt_read_paddr() to read physical addresses. We chose not to modify the orig= inal function as it is used in places where it needs to specifically read 64-bit values from dt (For e.g. dt_property_read_u64()). Xen prints warning when it detects truncation in cases where it is not able= to return error. Also, replaced u32/u64 with uint32_t/uint64_t in the functions touched by the code changes. Also, initialized variables to fix the warning "-Werror=3Dmaybe-uninitializ= ed". Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. Dropped "[XEN v1 2/9] xen/arm: Define translate_dt_address_size() f= or the translation between u64 and paddr_t" and "[XEN v1 4/9] xen/arm: Use translate_dt_address_size() to translate between= device tree addr/size and paddr_t", instead this approach achieves the same purpose. 2. No need to check for truncation while converting values from u64 to padd= r_t. v2 - 1. Use "( (dt_start >> (PADDR_SHIFT - 1)) > 1 )" to detect truncation. 2. Introduced libfdt_xen.h to implement fdt_get_mem_rsv_paddr 3. Logged error messages in case truncation is detected. v3 - 1. Renamed libfdt_xen.h to libfdt-xen.h. 2. Replaced u32/u64 with uint32_t/uint64_t 3. Use "(paddr_t)val !=3D val" to check for truncation. 4. Removed the alias "#define PADDR_SHIFT PADDR_BITS".=20 v4 - 1. Added a WARN() when truncation is detected. 2. Always check the return value of fdt_get_mem_rsv(). xen/arch/arm/bootfdt.c | 48 +++++++++++++++++++------ xen/arch/arm/domain_build.c | 2 +- xen/arch/arm/include/asm/setup.h | 4 +-- xen/arch/arm/setup.c | 18 +++++----- xen/arch/arm/smpboot.c | 2 +- xen/include/xen/device_tree.h | 23 ++++++++++++ xen/include/xen/libfdt/libfdt-xen.h | 55 +++++++++++++++++++++++++++++ 7 files changed, 129 insertions(+), 23 deletions(-) create mode 100644 xen/include/xen/libfdt/libfdt-xen.h diff --git a/xen/arch/arm/bootfdt.c b/xen/arch/arm/bootfdt.c index 0085c28d74..ac8148da55 100644 --- a/xen/arch/arm/bootfdt.c +++ b/xen/arch/arm/bootfdt.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -52,11 +52,37 @@ static bool __init device_tree_node_compatible(const vo= id *fdt, int node, return false; } =20 -void __init device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size) +void __init device_tree_get_reg(const __be32 **cell, uint32_t address_cell= s, + uint32_t size_cells, paddr_t *start, + paddr_t *size) { - *start =3D dt_next_cell(address_cells, cell); - *size =3D dt_next_cell(size_cells, cell); + uint64_t dt_start, dt_size; + + /* + * dt_next_cell will return uint64_t whereas paddr_t may not be 64-bit. + * Thus, there is an implicit cast from uint64_t to paddr_t. + */ + dt_start =3D dt_next_cell(address_cells, cell); + dt_size =3D dt_next_cell(size_cells, cell); + + if ( dt_start !=3D (paddr_t)dt_start ) + { + printk("Error: Physical address greater than max width supported\n= "); + WARN(); + } + + if ( dt_size !=3D (paddr_t)dt_size ) + { + printk("Error: Physical size greater than max width supported\n"); + WARN(); + } + + /* + * Xen will truncate the address/size if it is greater than the maximum + * supported width and it will give an appropriate warning. + */ + *start =3D dt_start; + *size =3D dt_size; } =20 static int __init device_tree_get_meminfo(const void *fdt, int node, @@ -326,7 +352,7 @@ static int __init process_chosen_node(const void *fdt, = int node, printk("linux,initrd-start property has invalid length %d\n", len); return -EINVAL; } - start =3D dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + start =3D dt_read_paddr((void *)&prop->data, dt_size_to_cells(len)); =20 prop =3D fdt_get_property(fdt, node, "linux,initrd-end", &len); if ( !prop ) @@ -339,7 +365,7 @@ static int __init process_chosen_node(const void *fdt, = int node, printk("linux,initrd-end property has invalid length %d\n", len); return -EINVAL; } - end =3D dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + end =3D dt_read_paddr((void *)&prop->data, dt_size_to_cells(len)); =20 if ( start >=3D end ) { @@ -593,10 +619,12 @@ static void __init early_print_info(void) nr_rsvd =3D fdt_num_mem_rsv(device_tree_flattened); for ( i =3D 0; i < nr_rsvd; i++ ) { - paddr_t s, e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &s, &e) < 0 ) + paddr_t s =3D 0, e =3D 0; + + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &s, &e) < 0 ) continue; - /* fdt_get_mem_rsv returns length */ + + /* fdt_get_mem_rsv_paddr returns length */ e +=3D s; printk(" RESVD[%u]: %"PRIpaddr" - %"PRIpaddr"\n", i, s, e); } diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index c8f08d8ee2..15c8bdd9e4 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -949,7 +949,7 @@ static int __init process_shm(struct domain *d, struct = kernel_info *kinfo, BUG_ON(!prop); cells =3D (const __be32 *)prop->value; device_tree_get_reg(&cells, addr_cells, addr_cells, &pbase, &gbase= ); - psize =3D dt_read_number(cells, size_cells); + psize =3D dt_read_paddr(cells, size_cells); if ( !IS_ALIGNED(pbase, PAGE_SIZE) || !IS_ALIGNED(gbase, PAGE_SIZE= ) ) { printk("%pd: physical address 0x%"PRIpaddr", or guest address = 0x%"PRIpaddr" is not suitably aligned.\n", diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/asm/se= tup.h index a926f30a2b..7b697d879e 100644 --- a/xen/arch/arm/include/asm/setup.h +++ b/xen/arch/arm/include/asm/setup.h @@ -157,8 +157,8 @@ const char *boot_module_kind_as_string(bootmodule_kind = kind); extern uint32_t hyp_traps_vector[]; void init_traps(void); =20 -void device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size); +void device_tree_get_reg(const __be32 **cell, uint32_t address_cells, + uint32_t size_cells, paddr_t *start, paddr_t *siz= e); =20 u32 device_tree_get_u32(const void *fdt, int node, const char *prop_name, u32 dflt); diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 1f26f67b90..d2a3d8c340 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -220,13 +220,13 @@ static void __init dt_unreserved_regions(paddr_t s, p= addr_t e, =20 for ( i =3D first; i < nr ; i++ ) { - paddr_t r_s, r_e; + paddr_t r_s =3D 0, r_e =3D 0; =20 - if ( fdt_get_mem_rsv(device_tree_flattened, i, &r_s, &r_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &r_s, &r_e ) = < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; =20 - r_e +=3D r_s; /* fdt_get_mem_rsv returns length */ + r_e +=3D r_s; /* fdt_get_mem_rsv_paddr returns length */ =20 if ( s < r_e && r_s < e ) { @@ -500,15 +500,15 @@ static paddr_t __init consider_modules(paddr_t s, pad= dr_t e, =20 for ( ; i < mi->nr_mods + nr; i++ ) { - paddr_t mod_s, mod_e; + paddr_t mod_s =3D 0, mod_e =3D 0; =20 - if ( fdt_get_mem_rsv(device_tree_flattened, - i - mi->nr_mods, - &mod_s, &mod_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, + i - mi->nr_mods, + &mod_s, &mod_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; =20 - /* fdt_get_mem_rsv returns length */ + /* fdt_get_mem_rsv_paddr returns length */ mod_e +=3D mod_s; =20 if ( s < mod_e && mod_s < e ) diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 412ae22869..c15c177487 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -159,7 +159,7 @@ static void __init dt_smp_init_cpus(void) continue; } =20 - addr =3D dt_read_number(prop, dt_n_addr_cells(cpu)); + addr =3D dt_read_paddr(prop, dt_n_addr_cells(cpu)); =20 hwid =3D addr; if ( hwid !=3D addr ) diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 19a74909ce..11bda2fd3d 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -241,6 +241,29 @@ static inline u64 dt_read_number(const __be32 *cell, i= nt size) return r; } =20 +/* Wrapper for dt_read_number() to return paddr_t (instead of uint64_t) */ +static inline paddr_t dt_read_paddr(const __be32 *cell, int size) +{ + uint64_t dt_r =3D 0; + paddr_t r; + + dt_r =3D dt_read_number(cell, size); + + if ( dt_r !=3D (paddr_t)dt_r ) + { + printk("Error: Physical address greater than max width supported\n= "); + WARN(); + } + + /* + * Xen will truncate the address/size if it is greater than the maximum + * supported width and it will give an appropriate warning. + */ + r =3D dt_r; + + return r; +} + /* Helper to convert a number of cells to bytes */ static inline int dt_cells_to_size(int size) { diff --git a/xen/include/xen/libfdt/libfdt-xen.h b/xen/include/xen/libfdt/l= ibfdt-xen.h new file mode 100644 index 0000000000..3296a368a6 --- /dev/null +++ b/xen/include/xen/libfdt/libfdt-xen.h @@ -0,0 +1,55 @@ +/* + * SPDX-License-Identifier: GPL-2.0-only + * + * xen/include/xen/libfdt/libfdt-xen.h + * + * Wrapper functions for device tree. This helps to convert dt values + * between uint64_t and paddr_t. + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All Rights Reserved. + */ + +#ifndef LIBFDT_XEN_H +#define LIBFDT_XEN_H + +#include + +static inline int fdt_get_mem_rsv_paddr(const void *fdt, int n, + paddr_t *address, + paddr_t *size) +{ + uint64_t dt_addr; + uint64_t dt_size; + int ret =3D 0; + + ret =3D fdt_get_mem_rsv(fdt, n, &dt_addr, &dt_size); + if ( ret ) + return ret; + + if ( dt_addr !=3D (paddr_t)dt_addr ) + { + printk("Error: Physical address greater than max width supported\n= "); + return -FDT_ERR_MAX; + } + + if ( dt_size !=3D (paddr_t)dt_size ) + { + printk("Error: Physical size greater than max width supported\n"); + return -FDT_ERR_MAX; + } + + *address =3D dt_addr; + *size =3D dt_size; + + return ret; +} + +#endif /* LIBFDT_XEN_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.17.1 From nobody Wed May 15 03:32:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 03/10] xen/arm: Introduce a wrapper for dt_device_get_address() to handle paddr_t Date: Thu, 13 Apr 2023 18:37:28 +0100 Message-ID: <20230413173735.48387-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT038:EE_|IA1PR12MB6162:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e35c369-2398-4e22-8367-08db3c45d750 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NjT3a55Y92ln30oEP7rU+udXS1MzAdqohmmEoWQ9wdPdsgWd8KzMxVcX/9j2s3up40EuE+cCyXC8J8ZQV7As2IeNTc/tC+T6hrRMLG8NgUbp5v1Gkx//fhEUM2+n/Poo70/+JJ8LIDZzcvrRNNZuVEbT5QtxoU/JUHbO6qAphZGuTOxTBy7KlqWdYSVkzP5GvJZlT2eYKwG1Wc3UMSaEYZ7uNtfHpsmTGZnAH2Ngr6kJiRuPsCn2psjo3DEgf2HXxfsjoqy02NKfEhQWLymJ3/Zq9KBcuVvuJ1tX8yHfpnmubEw1CrgYJgeOBa7D22n4ZeVl+asw/zERj32nupB9/Lja206auWuazefQWE4ClKKLS2LF+GxdM8vluBWXnxfgcd50SzeW49BhALIXgTFscAmchOAMz7c7bqE2W8Lb6YxjPby6PzAKotnVGGc04TPbGd/cEdlW/JnBSguO+xp69OzX23hidzHdVe4bOczKhZTbbqAGB33Um4ksgZ1xRNVd3iIgIp3ksVZJYwP/qtPJdDZevGU0rUOXrino8mg0S34TCGlGrflA7Tdm0crLCUzlvpjshpUI/ESv7YAvUMMfrPUwK63P+bPwvxcsNlzRbu+HDoZmq+TMIVO+x3/Aly85I8AxJft2c+nYjl8pnOMlrnOwrPm+Lvo+0rnvcCLdDJNy3j+mr+lRkk7ssACzYJFt2IchgBhgkqdC1lmNfPu/6klbwplSuiXMF2RmXnw4MPE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199021)(46966006)(36840700001)(40470700004)(7416002)(47076005)(36860700001)(82740400003)(2616005)(5660300002)(83380400001)(30864003)(2906002)(336012)(426003)(40460700003)(26005)(1076003)(186003)(8936002)(8676002)(6666004)(54906003)(36756003)(6916009)(4326008)(86362001)(70586007)(70206006)(316002)(81166007)(356005)(40480700001)(41300700001)(966005)(103116003)(82310400005)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:06.5376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e35c369-2398-4e22-8367-08db3c45d750 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6162 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407517681100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" dt_device_get_address() can accept uint64_t only for address and size. However, the address/size denotes physical addresses. Thus, they should be represented by 'paddr_t'. Consequently, we introduce a wrapper for dt_device_get_address() ie dt_device_get_paddr() which accepts address/size as paddr_t and inturn invokes dt_device_get_address() after converting address/size to uint64_t. The reason for introducing this is that in future 'paddr_t' may not always be 64-bit. Thus, we need an explicit wrapper to do the type conversion and return an error in case of truncation. With this, callers can now invoke dt_device_get_paddr(). Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. New patch. v2 - 1. Extracted part of "[XEN v2 05/11] xen/arm: Use paddr_t instead of u= 64 for address/size" into this patch. 2. dt_device_get_address() callers now invoke dt_device_get_paddr() instead. 3. Logged error in case of truncation. v3 - 1. Modified the truncation checks as "dt_addr !=3D (paddr_t)dt_addr". 2. Some sanity fixes. v4 - 1. Some sanity fixes. 2. Preserved the declaration of dt_device_get_address() in xen/include/xen/device_tree.h. The reason being it is currently used by ns16550.c. This driver requires some more changes as pointed by Jan in https://lore.kernel.org/xen-devel/6196e90f-752e-e61a-45ce-37e46c22b812@suse= .com/ which is to be addressed as a separate series. xen/arch/arm/domain_build.c | 10 +++---- xen/arch/arm/gic-v2.c | 10 +++---- xen/arch/arm/gic-v3-its.c | 4 +-- xen/arch/arm/gic-v3.c | 10 +++---- xen/arch/arm/pci/pci-host-common.c | 6 ++-- xen/arch/arm/platforms/brcm-raspberry-pi.c | 2 +- xen/arch/arm/platforms/brcm.c | 6 ++-- xen/arch/arm/platforms/exynos5.c | 32 ++++++++++---------- xen/arch/arm/platforms/sunxi.c | 2 +- xen/arch/arm/platforms/xgene-storm.c | 2 +- xen/common/device_tree.c | 35 ++++++++++++++++++++++ xen/drivers/char/cadence-uart.c | 4 +-- xen/drivers/char/exynos4210-uart.c | 4 +-- xen/drivers/char/imx-lpuart.c | 4 +-- xen/drivers/char/meson-uart.c | 4 +-- xen/drivers/char/mvebu-uart.c | 4 +-- xen/drivers/char/omap-uart.c | 4 +-- xen/drivers/char/pl011.c | 6 ++-- xen/drivers/char/scif-uart.c | 4 +-- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 8 ++--- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 8 ++--- xen/include/xen/device_tree.h | 13 ++++++++ 23 files changed, 116 insertions(+), 68 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 15c8bdd9e4..7d28b75517 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1698,13 +1698,13 @@ static int __init find_memory_holes(const struct ke= rnel_info *kinfo, dt_for_each_device_node( dt_host, np ) { unsigned int naddr; - u64 addr, size; + paddr_t addr, size; =20 naddr =3D dt_number_of_address(np); =20 for ( i =3D 0; i < naddr; i++ ) { - res =3D dt_device_get_address(np, i, &addr, &size); + res =3D dt_device_get_paddr(np, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2478,7 +2478,7 @@ static int __init handle_device(struct domain *d, str= uct dt_device_node *dev, unsigned int naddr; unsigned int i; int res; - u64 addr, size; + paddr_t addr, size; bool own_device =3D !dt_device_for_passthrough(dev); /* * We want to avoid mapping the MMIO in dom0 for the following cases: @@ -2533,7 +2533,7 @@ static int __init handle_device(struct domain *d, str= uct dt_device_node *dev, /* Give permission and map MMIOs */ for ( i =3D 0; i < naddr; i++ ) { - res =3D dt_device_get_address(dev, i, &addr, &size); + res =3D dt_device_get_paddr(dev, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2964,7 +2964,7 @@ static int __init handle_passthrough_prop(struct kern= el_info *kinfo, if ( res ) { printk(XENLOG_ERR "Unable to permit to dom%d access to" - " 0x%"PRIx64" - 0x%"PRIx64"\n", + " 0x%"PRIpaddr" - 0x%"PRIpaddr"\n", kinfo->d->domain_id, mstart & PAGE_MASK, PAGE_ALIGN(mstart + size) - 1); return res; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5d4d298b86..6476ff4230 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -993,7 +993,7 @@ static void gicv2_extension_dt_init(const struct dt_dev= ice_node *node) continue; =20 /* Get register frame resource from DT. */ - if ( dt_device_get_address(v2m, 0, &addr, &size) ) + if ( dt_device_get_paddr(v2m, 0, &addr, &size) ) panic("GICv2: Cannot find a valid v2m frame address\n"); =20 /* @@ -1018,19 +1018,19 @@ static void __init gicv2_dt_init(void) paddr_t vsize; const struct dt_device_node *node =3D gicv2_info.node; =20 - res =3D dt_device_get_address(node, 0, &dbase, NULL); + res =3D dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the distributor\n"); =20 - res =3D dt_device_get_address(node, 1, &cbase, &csize); + res =3D dt_device_get_paddr(node, 1, &cbase, &csize); if ( res ) panic("GICv2: Cannot find a valid address for the CPU\n"); =20 - res =3D dt_device_get_address(node, 2, &hbase, NULL); + res =3D dt_device_get_paddr(node, 2, &hbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the hypervisor\n"); =20 - res =3D dt_device_get_address(node, 3, &vbase, &vsize); + res =3D dt_device_get_paddr(node, 3, &vbase, &vsize); if ( res ) panic("GICv2: Cannot find a valid address for the virtual CPU\n"); =20 diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 1ec9934191..3aa4edda10 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -1004,12 +1004,12 @@ static void gicv3_its_dt_init(const struct dt_devic= e_node *node) */ dt_for_each_child_node(node, its) { - uint64_t addr, size; + paddr_t addr, size; =20 if ( !dt_device_is_compatible(its, "arm,gic-v3-its") ) continue; =20 - if ( dt_device_get_address(its, 0, &addr, &size) ) + if ( dt_device_get_paddr(its, 0, &addr, &size) ) panic("GICv3: Cannot find a valid ITS frame address\n"); =20 add_to_host_its_list(addr, size, its); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bb59ea94cd..4e6c98bada 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1377,7 +1377,7 @@ static void __init gicv3_dt_init(void) int res, i; const struct dt_device_node *node =3D gicv3_info.node; =20 - res =3D dt_device_get_address(node, 0, &dbase, NULL); + res =3D dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv3: Cannot find a valid distributor address\n"); =20 @@ -1393,9 +1393,9 @@ static void __init gicv3_dt_init(void) =20 for ( i =3D 0; i < gicv3.rdist_count; i++ ) { - uint64_t rdist_base, rdist_size; + paddr_t rdist_base, rdist_size; =20 - res =3D dt_device_get_address(node, 1 + i, &rdist_base, &rdist_siz= e); + res =3D dt_device_get_paddr(node, 1 + i, &rdist_base, &rdist_size); if ( res ) panic("GICv3: No rdist base found for region %d\n", i); =20 @@ -1417,10 +1417,10 @@ static void __init gicv3_dt_init(void) * For GICv3 supporting GICv2, GICC and GICV base address will be * provided. */ - res =3D dt_device_get_address(node, 1 + gicv3.rdist_count, + res =3D dt_device_get_paddr(node, 1 + gicv3.rdist_count, &cbase, &csize); if ( !res ) - dt_device_get_address(node, 1 + gicv3.rdist_count + 2, + dt_device_get_paddr(node, 1 + gicv3.rdist_count + 2, &vbase, &vsize); } =20 diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host= -common.c index a8ece94303..5550f9478d 100644 --- a/xen/arch/arm/pci/pci-host-common.c +++ b/xen/arch/arm/pci/pci-host-common.c @@ -93,7 +93,7 @@ gen_pci_init(struct dt_device_node *dev, const struct pci= _ecam_ops *ops) cfg_reg_idx =3D 0; =20 /* Parse our PCI ecam register address */ - err =3D dt_device_get_address(dev, cfg_reg_idx, &addr, &size); + err =3D dt_device_get_paddr(dev, cfg_reg_idx, &addr, &size); if ( err ) goto err_exit; =20 @@ -349,10 +349,10 @@ int __init pci_host_bridge_mappings(struct domain *d) =20 for ( i =3D 0; i < dt_number_of_address(dev); i++ ) { - uint64_t addr, size; + paddr_t addr, size; int err; =20 - err =3D dt_device_get_address(dev, i, &addr, &size); + err =3D dt_device_get_paddr(dev, i, &addr, &size); if ( err ) { printk(XENLOG_ERR diff --git a/xen/arch/arm/platforms/brcm-raspberry-pi.c b/xen/arch/arm/plat= forms/brcm-raspberry-pi.c index 811b40b1a6..407ec07f63 100644 --- a/xen/arch/arm/platforms/brcm-raspberry-pi.c +++ b/xen/arch/arm/platforms/brcm-raspberry-pi.c @@ -64,7 +64,7 @@ static void __iomem *rpi4_map_watchdog(void) if ( !node ) return NULL; =20 - ret =3D dt_device_get_address(node, 0, &start, &len); + ret =3D dt_device_get_paddr(node, 0, &start, &len); if ( ret ) { printk("Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/platforms/brcm.c b/xen/arch/arm/platforms/brcm.c index d481b2c60f..951e4d6cc3 100644 --- a/xen/arch/arm/platforms/brcm.c +++ b/xen/arch/arm/platforms/brcm.c @@ -40,7 +40,7 @@ static __init int brcm_get_dt_node(char *compat_str, u32 *reg_base) { const struct dt_device_node *node; - u64 reg_base_64; + paddr_t reg_base_paddr; int rc; =20 node =3D dt_find_compatible_node(NULL, NULL, compat_str); @@ -50,7 +50,7 @@ static __init int brcm_get_dt_node(char *compat_str, return -ENOENT; } =20 - rc =3D dt_device_get_address(node, 0, ®_base_64, NULL); + rc =3D dt_device_get_paddr(node, 0, ®_base_paddr, NULL); if ( rc ) { dprintk(XENLOG_ERR, "%s: missing \"reg\" prop\n", __func__); @@ -61,7 +61,7 @@ static __init int brcm_get_dt_node(char *compat_str, *dn =3D node; =20 if ( reg_base ) - *reg_base =3D reg_base_64; + *reg_base =3D reg_base_paddr; =20 return 0; } diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exyn= os5.c index 6560507092..c48093cd4f 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -42,8 +42,8 @@ static int exynos5_init_time(void) void __iomem *mct; int rc; struct dt_device_node *node; - u64 mct_base_addr; - u64 size; + paddr_t mct_base_addr; + paddr_t size; =20 node =3D dt_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct"); if ( !node ) @@ -52,14 +52,14 @@ static int exynos5_init_time(void) return -ENXIO; } =20 - rc =3D dt_device_get_address(node, 0, &mct_base_addr, &size); + rc =3D dt_device_get_paddr(node, 0, &mct_base_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos4210-mct\"\n"); return -ENXIO; } =20 - dprintk(XENLOG_INFO, "mct_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_INFO, "mct_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"= \n", mct_base_addr, size); =20 mct =3D ioremap_nocache(mct_base_addr, size); @@ -97,9 +97,9 @@ static int __init exynos5_smp_init(void) struct dt_device_node *node; void __iomem *sysram; char *compatible; - u64 sysram_addr; - u64 size; - u64 sysram_offset; + paddr_t sysram_addr; + paddr_t size; + paddr_t sysram_offset; int rc; =20 node =3D dt_find_compatible_node(NULL, NULL, "samsung,secure-firmware"= ); @@ -125,13 +125,13 @@ static int __init exynos5_smp_init(void) return -ENXIO; } =20 - rc =3D dt_device_get_address(node, 0, &sysram_addr, &size); + rc =3D dt_device_get_paddr(node, 0, &sysram_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in %s\n", compatible); return -ENXIO; } - dprintk(XENLOG_INFO, "sysram_addr: %016llx size: %016llx offset: %016l= lx\n", + dprintk(XENLOG_INFO,"sysram_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"off= set: 0x%"PRIpaddr"\n", sysram_addr, size, sysram_offset); =20 sysram =3D ioremap_nocache(sysram_addr, size); @@ -189,7 +189,7 @@ static int exynos5_cpu_power_up(void __iomem *power, in= t cpu) return 0; } =20 -static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) +static int exynos5_get_pmu_baseandsize(paddr_t *power_base_addr, paddr_t *= size) { struct dt_device_node *node; int rc; @@ -208,14 +208,14 @@ static int exynos5_get_pmu_baseandsize(u64 *power_bas= e_addr, u64 *size) return -ENXIO; } =20 - rc =3D dt_device_get_address(node, 0, power_base_addr, size); + rc =3D dt_device_get_paddr(node, 0, power_base_addr, size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos5XXX-pmu\"\n"); return -ENXIO; } =20 - dprintk(XENLOG_DEBUG, "power_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_DEBUG, "power_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpad= dr"\n", *power_base_addr, *size); =20 return 0; @@ -223,8 +223,8 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_= addr, u64 *size) =20 static int exynos5_cpu_up(int cpu) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *power; int rc; =20 @@ -256,8 +256,8 @@ static int exynos5_cpu_up(int cpu) =20 static void exynos5_reset(void) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *pmu; int rc; =20 diff --git a/xen/arch/arm/platforms/sunxi.c b/xen/arch/arm/platforms/sunxi.c index e8e4d88bef..2b2c215f20 100644 --- a/xen/arch/arm/platforms/sunxi.c +++ b/xen/arch/arm/platforms/sunxi.c @@ -50,7 +50,7 @@ static void __iomem *sunxi_map_watchdog(bool *new_wdt) return NULL; } =20 - ret =3D dt_device_get_address(node, 0, &wdt_start, &wdt_len); + ret =3D dt_device_get_paddr(node, 0, &wdt_start, &wdt_len); if ( ret ) { dprintk(XENLOG_ERR, "Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/= xgene-storm.c index befd0c3c2d..6fc2f9679e 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -50,7 +50,7 @@ static void __init xgene_check_pirq_eoi(void) if ( !node ) panic("%s: Can not find interrupt controller node\n", __func__); =20 - res =3D dt_device_get_address(node, 0, &dbase, NULL); + res =3D dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("%s: Cannot find a valid address for the distributor\n", __f= unc__); =20 diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c index 6c9712ab7b..fdef74e7ff 100644 --- a/xen/common/device_tree.c +++ b/xen/common/device_tree.c @@ -955,6 +955,41 @@ int dt_device_get_address(const struct dt_device_node = *dev, unsigned int index, return 0; } =20 +int dt_device_get_paddr(const struct dt_device_node *dev, unsigned int ind= ex, + paddr_t *addr, paddr_t *size) +{ + uint64_t dt_addr =3D 0, dt_size =3D 0; + int ret; + + ret =3D dt_device_get_address(dev, index, &dt_addr, &dt_size); + if ( ret ) + return ret; + + if ( addr ) + { + if ( dt_addr !=3D (paddr_t)dt_addr ) + { + printk("Error: Physical address 0x%"PRIx64" for node=3D%s is g= reater than max width (%zu bytes) supported\n", + dt_addr, dev->name, sizeof(paddr_t)); + return -ERANGE; + } + + *addr =3D dt_addr; + } + + if ( size ) + { + if ( dt_size !=3D (paddr_t)dt_size ) + { + printk("Error: Physical size 0x%"PRIx64" for node=3D%s is grea= ter than max width (%zu bytes) supported\n", + dt_size, dev->name, sizeof(paddr_t)); + return -ERANGE; + } + *size =3D dt_size; + } + + return ret; +} =20 int dt_for_each_range(const struct dt_device_node *dev, int (*cb)(const struct dt_device_node *, diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uar= t.c index 22905ba66c..c38d7ed143 100644 --- a/xen/drivers/char/cadence-uart.c +++ b/xen/drivers/char/cadence-uart.c @@ -158,14 +158,14 @@ static int __init cuart_init(struct dt_device_node *d= ev, const void *data) const char *config =3D data; struct cuart *uart; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); =20 uart =3D &cuart_com; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("cadence: Unable to retrieve the base" diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos42= 10-uart.c index 43aaf02e18..2503392ccd 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -303,7 +303,7 @@ static int __init exynos4210_uart_init(struct dt_device= _node *dev, const char *config =3D data; struct exynos4210_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -316,7 +316,7 @@ static int __init exynos4210_uart_init(struct dt_device= _node *dev, uart->parity =3D PARITY_NONE; uart->stop_bits =3D 1; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("exynos4210: Unable to retrieve the base" diff --git a/xen/drivers/char/imx-lpuart.c b/xen/drivers/char/imx-lpuart.c index 9c1f3b71a3..77f70c2719 100644 --- a/xen/drivers/char/imx-lpuart.c +++ b/xen/drivers/char/imx-lpuart.c @@ -204,7 +204,7 @@ static int __init imx_lpuart_init(struct dt_device_node= *dev, const char *config =3D data; struct imx_lpuart *uart; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -216,7 +216,7 @@ static int __init imx_lpuart_init(struct dt_device_node= *dev, uart->parity =3D 0; uart->stop_bits =3D 1; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("imx8-lpuart: Unable to retrieve the base" diff --git a/xen/drivers/char/meson-uart.c b/xen/drivers/char/meson-uart.c index b1e25e0468..c627328122 100644 --- a/xen/drivers/char/meson-uart.c +++ b/xen/drivers/char/meson-uart.c @@ -209,14 +209,14 @@ static int __init meson_uart_init(struct dt_device_no= de *dev, const void *data) const char *config =3D data; struct meson_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); =20 uart =3D &meson_com; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("meson: Unable to retrieve the base address of the UART\n"); diff --git a/xen/drivers/char/mvebu-uart.c b/xen/drivers/char/mvebu-uart.c index a00618b96f..cc55173513 100644 --- a/xen/drivers/char/mvebu-uart.c +++ b/xen/drivers/char/mvebu-uart.c @@ -231,14 +231,14 @@ static int __init mvebu_uart_init(struct dt_device_no= de *dev, const void *data) const char *config =3D data; struct mvebu3700_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); =20 uart =3D &mvebu3700_com; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("mvebu3700: Unable to retrieve the base address of the UART= \n"); diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c index d6a5d59aa2..8e643cb039 100644 --- a/xen/drivers/char/omap-uart.c +++ b/xen/drivers/char/omap-uart.c @@ -324,7 +324,7 @@ static int __init omap_uart_init(struct dt_device_node = *dev, struct omap_uart *uart; u32 clkspec; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -344,7 +344,7 @@ static int __init omap_uart_init(struct dt_device_node = *dev, uart->parity =3D UART_PARITY_NONE; uart->stop_bits =3D 1; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("omap-uart: Unable to retrieve the base" diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index be67242bc0..052a651251 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -222,7 +222,7 @@ static struct uart_driver __read_mostly pl011_driver = =3D { .vuart_info =3D pl011_vuart, }; =20 -static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa) +static int __init pl011_uart_init(int irq, paddr_t addr, paddr_t size, boo= l sbsa) { struct pl011 *uart; =20 @@ -258,14 +258,14 @@ static int __init pl011_dt_uart_init(struct dt_device= _node *dev, { const char *config =3D data; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) { printk("WARNING: UART configuration is not supported\n"); } =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("pl011: Unable to retrieve the base" diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 2fccafe340..1b28ba90e9 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -311,14 +311,14 @@ static int __init scif_uart_init(struct dt_device_nod= e *dev, const char *config =3D data; struct scif_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; =20 if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); =20 uart =3D &scif_com; =20 - res =3D dt_device_get_address(dev, 0, &addr, &size); + res =3D dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("scif-uart: Unable to retrieve the base" diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr= ough/arm/ipmmu-vmsa.c index 091f09b217..611d9eeba5 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -794,7 +794,7 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device= *mmu) static __init bool ipmmu_stage2_supported(void) { struct dt_device_node *np; - uint64_t addr, size; + paddr_t addr, size; void __iomem *base; uint32_t product, cut; bool stage2_supported =3D false; @@ -806,7 +806,7 @@ static __init bool ipmmu_stage2_supported(void) return false; } =20 - if ( dt_device_get_address(np, 0, &addr, &size) ) + if ( dt_device_get_paddr(np, 0, &addr, &size) ) { printk(XENLOG_ERR "ipmmu: Failed to get PRR MMIO\n"); return false; @@ -884,7 +884,7 @@ static int ipmmu_probe(struct dt_device_node *node) { const struct dt_device_match *match; struct ipmmu_vmsa_device *mmu; - uint64_t addr, size; + paddr_t addr, size; uint32_t reg; int irq, ret; =20 @@ -905,7 +905,7 @@ static int ipmmu_probe(struct dt_device_node *node) bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); =20 /* Map I/O memory and request IRQ. */ - ret =3D dt_device_get_address(node, 0, &addr, &size); + ret =3D dt_device_get_paddr(node, 0, &addr, &size); if ( ret ) { dev_err(&node->dev, "Failed to get MMIO\n"); diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index bfdb62b395..b7fa2e90f7 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -2428,7 +2428,7 @@ static int arm_smmu_device_probe(struct platform_devi= ce *pdev) } =20 /* Base address */ - ret =3D dt_device_get_address(np, 0, &ioaddr, &iosize); + ret =3D dt_device_get_paddr(np, 0, &ioaddr, &iosize); if (ret) goto out_free_smmu; =20 diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index 0a514821b3..79281075ba 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -73,8 +73,8 @@ /* Xen: Helpers to get device MMIO and IRQs */ struct resource { - u64 addr; - u64 size; + paddr_t addr; + paddr_t size; unsigned int type; }; =20 @@ -101,7 +101,7 @@ static struct resource *platform_get_resource(struct pl= atform_device *pdev, =20 switch (type) { case IORESOURCE_MEM: - ret =3D dt_device_get_address(pdev, num, &res.addr, &res.size); + ret =3D dt_device_get_paddr(pdev, num, &res.addr, &res.size); =20 return ((ret) ? NULL : &res); =20 @@ -169,7 +169,7 @@ static void __iomem *devm_ioremap_resource(struct devic= e *dev, ptr =3D ioremap_nocache(res->addr, res->size); if (!ptr) { dev_err(dev, - "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n", + "ioremap failed (addr 0x%"PRIpaddr" size 0x%"PRIpaddr")\n", res->addr, res->size); return ERR_PTR(-ENOMEM); } diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 11bda2fd3d..c1dc5400e1 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -581,6 +581,19 @@ int dt_find_node_by_gpath(XEN_GUEST_HANDLE(char) u_pat= h, uint32_t u_plen, */ const struct dt_device_node *dt_get_parent(const struct dt_device_node *no= de); =20 +/** + * dt_device_get_paddr - Resolve an address for a device + * @device: the device whose address is to be resolved + * @index: index of the address to resolve + * @addr: address filled by this function + * @size: size filled by this function + * + * This function resolves an address, walking the tree, for a give + * device-tree node. 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 04/10] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0 Date: Thu, 13 Apr 2023 18:37:29 +0100 Message-ID: <20230413173735.48387-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT056:EE_|IA0PR12MB7723:EE_ X-MS-Office365-Filtering-Correlation-Id: d4fd22d6-3c30-4f17-a19e-08db3c45d902 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:09.3826 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4fd22d6-3c30-4f17-a19e-08db3c45d902 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7723 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407516093100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9, SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use writeq_relaxed_non_atomic() to write to it instead of invoking writel_relaxed() twice for lower half and upper half of the register. This also helps us as p2maddr is 'paddr_t' (which may be u32 in future). Thus, one can assign p2maddr to a 64 bit register and do the bit manipulations on it, to generate the value for SMMU_CBn_TTBR0. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations r= equired to support 32bit paddr". Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic fashion. v2 - 1. Added R-b. v3 - 1. No changes. v4 - 1. Reordered the R-b. No further changes. (This patch can be committed independent of the series). xen/drivers/passthrough/arm/smmu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index 79281075ba..c8ef2a925f 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -499,8 +499,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 -#define ARM_SMMU_CB_TTBR0_LO 0x20 -#define ARM_SMMU_CB_TTBR0_HI 0x24 +#define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 @@ -1083,6 +1082,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_de= vice *smmu, void *addr, static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) { u32 reg; + u64 reg64; bool stage1; struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; struct arm_smmu_device *smmu =3D smmu_domain->smmu; @@ -1177,12 +1177,13 @@ static void arm_smmu_init_context_bank(struct arm_s= mmu_domain *smmu_domain) dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", smmu_domain->cfg.domain->domain_id, p2maddr); =20 - reg =3D (p2maddr & ((1ULL << 32) - 1)); - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); - reg =3D (p2maddr >> 32); + reg64 =3D p2maddr; + if (stage1) - reg |=3D ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); + reg64 |=3D (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT)) + << 32); + + writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0); =20 /* * TTBCR --=20 2.17.1 From nobody Wed May 15 03:32:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; 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bh=rTjpNh+BHfToII30u7IVf5AGDUbfYB8YKJohyCLK1pQ=; b=tEhm6AW4eQRfV6ho0FbQogVzJddsBYsVAdmf7jk04n65gm1+Dv9KoEUfmRPVHLBc5w2GCibGKHR1RPLtukblXNq6vQ2vSNg13Qq0EAu1j/fOGYuLINUdVaWbFLUZvZhHJNgkQYIdauvVEWWyue2c+4ecCqu4k6QFoTEqlT8QPDU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 05/10] xen/arm: Introduce choice to enable 64/32 bit physical addressing Date: Thu, 13 Apr 2023 18:37:30 +0100 Message-ID: <20230413173735.48387-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT022:EE_|MN0PR12MB5931:EE_ X-MS-Office365-Filtering-Correlation-Id: cbdf1f5b-395a-4866-7162-08db3c45dafd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:12.7041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbdf1f5b-395a-4866-7162-08db3c45dafd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5931 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407515832100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Arm based hardware platforms which does not support LPAE (eg Cortex-R52), uses 32 bit physical addresses. Also, users may choose to use 32 bits to represent physical addresses for optimization. To support the above use cases, we have introduced arch independent configs to choose if the physical address can be represented using 32 bits (PHYS_ADDR_T_32) or 64 bits (!PHYS_ADDR_T_32). For now only ARM_32 provides support to enable 32 bit physical addressing. When PHYS_ADDR_T_32 is defined, PADDR_BITS is set to 32. When PHYS_ADDR_T_32 is not defined for ARM_32, PADDR_BITS is set to 40. When PHYS_ADDR_T_32 is not defined for ARM_64, PADDR_BITS is set to 48. The last two are same as the current configuration used today on Xen. PADDR_BITS is also set to 48 when ARM_64 is defined. The reason being the choice to select ARM_PA_BITS_32/ARM_PA_BITS_40/ARM_PA_BITS_48 is currently allowed when ARM_32 is defined. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to= support 32bit paddr". v2 - 1. Introduced Kconfig choice. ARM_64 can select PHYS_ADDR_64 only wher= eas ARM_32 can select PHYS_ADDR_32 or PHYS_ADDR_64. 2. For CONFIG_ARM_PA_32, paddr_t is defined as 'unsigned long'.=20 v3 - 1. Allow user to define PADDR_BITS by selecting different config optio= ns ARM_PA_BITS_32, ARM_PA_BITS_40 and ARM_PA_BITS_48. 2. Add the choice under "Architecture Features". v4 - 1. Removed PHYS_ADDR_T_64 as !PHYS_ADDR_T_32 means PHYS_ADDR_T_32. xen/arch/Kconfig | 3 +++ xen/arch/arm/Kconfig | 37 ++++++++++++++++++++++++++-- xen/arch/arm/include/asm/page-bits.h | 6 +---- xen/arch/arm/include/asm/types.h | 6 +++++ xen/arch/arm/mm.c | 5 ++++ 5 files changed, 50 insertions(+), 7 deletions(-) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 7028f7b74f..67ba38f32f 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -1,6 +1,9 @@ config 64BIT bool =20 +config PHYS_ADDR_T_32 + bool + config NR_CPUS int "Maximum number of CPUs" range 1 4095 diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 239d3aed3c..3f6e13e475 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -19,13 +19,46 @@ config ARM select HAS_PMAP select IOMMU_FORCE_PT_SHARE =20 +menu "Architecture Features" + +choice + prompt "Physical address space size" if ARM_32 + default ARM_PA_BITS_48 if ARM_64 + default ARM_PA_BITS_40 if ARM_32 + help + User can choose to represent the width of physical address. This can + sometimes help in optimizing the size of image when user chooses a + smaller size to represent physical address. + +config ARM_PA_BITS_32 + bool "32-bit" + help + On platforms where any physical address can be represented within 32 bi= ts, + user should choose this option. This will help is reduced size of the + binary. + select PHYS_ADDR_T_32 + depends on ARM_32 + +config ARM_PA_BITS_40 + bool "40-bit" + depends on ARM_32 + +config ARM_PA_BITS_48 + bool "40-bit" + depends on ARM_48 +endchoice + +config PADDR_BITS + int + default 32 if ARM_PA_BITS_32 + default 40 if ARM_PA_BITS_40 + default 48 if ARM_PA_BITS_48 || ARM_64 + config ARCH_DEFCONFIG string default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 =20 -menu "Architecture Features" - source "arch/Kconfig" =20 config ACPI diff --git a/xen/arch/arm/include/asm/page-bits.h b/xen/arch/arm/include/as= m/page-bits.h index 5d6477e599..deb381ceeb 100644 --- a/xen/arch/arm/include/asm/page-bits.h +++ b/xen/arch/arm/include/asm/page-bits.h @@ -3,10 +3,6 @@ =20 #define PAGE_SHIFT 12 =20 -#ifdef CONFIG_ARM_64 -#define PADDR_BITS 48 -#else -#define PADDR_BITS 40 -#endif +#define PADDR_BITS CONFIG_PADDR_BITS =20 #endif /* __ARM_PAGE_SHIFT_H__ */ diff --git a/xen/arch/arm/include/asm/types.h b/xen/arch/arm/include/asm/ty= pes.h index e218ed77bd..e3cfbbb060 100644 --- a/xen/arch/arm/include/asm/types.h +++ b/xen/arch/arm/include/asm/types.h @@ -34,9 +34,15 @@ typedef signed long long s64; typedef unsigned long long u64; typedef u32 vaddr_t; #define PRIvaddr PRIx32 +#if defined(CONFIG_PHYS_ADDR_T_32) +typedef unsigned long paddr_t; +#define INVALID_PADDR (~0UL) +#define PRIpaddr "08lx" +#else typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" +#endif typedef u32 register_t; #define PRIregister "08x" #elif defined (CONFIG_ARM_64) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index b99806af99..6dc37be97e 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -690,6 +690,11 @@ void __init setup_frametable_mappings(paddr_t ps, padd= r_t pe) const unsigned long mapping_size =3D frametable_size < MB(32) ? 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bh=eTQJ7lPK89ZtnWjeWUiqYAA5GuUNieXG2h1mgdQDvYw=; b=vqHOMzgyq886Y1jjUWpFN3KHM7/VP2C/5TVEbTt7HIDsj1blMl6FsHRWmcY7uwKJgyQxybq33DTw6wQHhf0jWbKMg4F7RNFcCW4VA3DAjBpweHUm3LU0EXwWQQB8rVt6c4wamMgwyePtSc3AcUfHNfxCPU4Mk5EFoaHlXmHnkpA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 06/10] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32" Date: Thu, 13 Apr 2023 18:37:31 +0100 Message-ID: <20230413173735.48387-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT010:EE_|SJ1PR12MB6099:EE_ X-MS-Office365-Filtering-Correlation-Id: edeceec4-7f4a-4f4c-54cd-08db3c45e046 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:21.5704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edeceec4-7f4a-4f4c-54cd-08db3c45e046 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6099 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407530925100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the previous patch introduces CONFIG_PHYS_ADDR_T_32 to support 32 bit physical addresses, the code specific to "Large Physical Address Extension" (ie LPAE) should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32". Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t" unsigned int extbase1:4; /* Extended base address, PA[35:32] */ unsigned int extbase2:4; /* Extended base address, PA[39:36] */ Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses are supported. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to= support 32bit paddr". v2 - 1. Reordered this patch so that it appears after CONFIG_ARM_PA_32 is introduced (in 6/9). v3 - 1. Updated the commit message. 2. Added Ack. v4 - 1. No changes. xen/arch/arm/guest_walk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..c80a0ce55b 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v, mask =3D (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; *ipa =3D gva & mask; *ipa |=3D (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_= SHIFT; +#ifndef CONFIG_PHYS_ADDR_T_32 *ipa |=3D (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECT= ION_EXT_BASE1_SHIFT; *ipa |=3D (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECT= ION_EXT_BASE2_SHIFT; +#endif /* CONFIG_PHYS_ADDR_T_32 */ } =20 /* Set permissions so that the caller can check the flags by herse= lf. */ --=20 2.17.1 From nobody Wed May 15 03:32:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 07/10] xen/arm: Restrict zeroeth_table_offset for ARM_64 Date: Thu, 13 Apr 2023 18:37:32 +0100 Message-ID: <20230413173735.48387-8-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT103:EE_|CO6PR12MB5459:EE_ X-MS-Office365-Filtering-Correlation-Id: a09b65e1-a62c-4f92-61d3-08db3c45e1f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aMbQQyI0lhjB3Ol7ogO4+excqyipn5GqqqDSeN/UqMAq9vzOnoFksbyhlkHEk2P0n86ZZeMpenwIQ+cogYthlkd5q7xYOFsRpzmCGDsVfAj6+nqRFgpqKpW+F2pxUAbutXyBqdUstnApCphwDvhcpdaHLAjfpKQPzTR4iSy1guPC1woiN2bploUbzHWSgOQ9Gd3O56hACfjUALgjuwbsDayZ7hKzdTpjNbae3mvHPZyFTf57PMzV6RqOZHMBB7gocl5TB18SxkpPuHW9Sw7uKG2/gbCtSPOlkCCMccMsnBnVwAl6x6XpFpN9JgPJ7b/Ci3bfADvA3dvChmnZQO7ed069ao89BHm0caX3h3KGx0TcZ/74nzbwKKe4rS3hIzWt/GgDclhqZ8evNXXDfp/NZOVF0fLqOw//3RhgQCOcaxZWjtgrLa+v7MqktRdpYeYHrE9cjBtvoYPt30mfByFuFMhbXWuDRdzuIocaSqKmtuVLf+AoBsf8mKxZwnUyyL4rrjxbZ6bMP/skcA0F5vKddUgVyJShphqw96MKTwjApHojV5WLSNEyMMbsXuWvkRzbdpkkMrTs+gg6yN3srKAUaleITMpoc5W3Qt9kq/mE3hvbuZc1myOJuVtKX8mKbbpgY5CSg8eqi8uoPHKf4CoGJqc6syA6qjMOZlmeeg9Wx7H29e0H7hoYKNd46RHO7umEfrFGBSl5TeKA172PFskc/WJ6oulYJPEqkmbvg433Fvg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199021)(40470700004)(36840700001)(46966006)(40460700003)(316002)(41300700001)(81166007)(1076003)(26005)(186003)(86362001)(6666004)(47076005)(356005)(36860700001)(2616005)(82310400005)(426003)(336012)(83380400001)(82740400003)(6916009)(4326008)(54906003)(36756003)(40480700001)(70206006)(70586007)(8676002)(8936002)(5660300002)(2906002)(7416002)(103116003)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:24.3756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a09b65e1-a62c-4f92-61d3-08db3c45e1f2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5459 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407530136100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When 32 bit physical addresses are used (ie PHYS_ADDR_T_32=3Dy), "va >> ZEROETH_SHIFT" causes an overflow. Also, there is no zeroeth level page table on Arm32. Also took the opportunity to clean up dump_pt_walk(). One could use DECLARE_OFFSETS() macro instead of declaring the declaring an array of page table offsets. Signed-off-by: Ayan Kumar Halder Acked-by: Julien Grall Reviewed-by: Michal Orzel --- Changes from - v1 - Removed the duplicate declaration for DECLARE_OFFSETS. v2 - 1. Reworded the commit message.=20 2. Use CONFIG_ARM_PA_32 to restrict zeroeth_table_offset. v3 - 1. Added R-b and Ack. v4 - 1. Removed R-b and Ack as we use CONFIG_PHYS_ADDR_T_32 instead of CONFIG_ARM_PA_BITS_32. This is to be in parity with our earlier patches where we use CONFIG_PHYS_ADDR_T_32 to denote 32-bit physical addr support. xen/arch/arm/include/asm/lpae.h | 4 ++++ xen/arch/arm/mm.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpa= e.h index 3fdd5d0de2..7d2f6fd1bd 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -259,7 +259,11 @@ lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned int attr); #define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) #define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) #define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) +#ifdef CONFIG_PHYS_ADDR_T_32 +#define zeroeth_table_offset(va) 0 +#else #define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) +#endif =20 /* * Macros to define page-tables: diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6dc37be97e..247510ac57 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -221,12 +221,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, { static const char *level_strs[4] =3D { "0TH", "1ST", "2ND", "3RD" }; const mfn_t root_mfn =3D maddr_to_mfn(ttbr); - const unsigned int offsets[4] =3D { - zeroeth_table_offset(addr), - first_table_offset(addr), - second_table_offset(addr), - third_table_offset(addr) - }; + DECLARE_OFFSETS(offsets, addr); lpae_t pte, *mapping; unsigned int level, root_table; =20 --=20 2.17.1 From nobody Wed May 15 03:32:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1681407530; cv=pass; d=zohomail.com; s=zohoarc; b=IQo/84SAnI+2HAQjdF+U1WElv3uVKa/U0s/LHhRyDh96Hp10cdO2FBT0sOIs6aUvkR8esG9niOEeZ4xKUL3gPOc9HS1sp8NHw/o1XQ/rcNyb2qifgz6H+LjyATf8OF6UbEVgxwqGYI0NtOekuGVPtgop3dnThWjYWK99kCLqqj0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:27.0413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94e40bd9-7988-4fb9-219f-08db3c45e389 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5106 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407532784100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" handle_pci_range() and map_range_to_domain() take addr and len as uint64_t parameters. Then frame numbers are obtained from addr and len by right shif= ting with PAGE_SHIFT. The page frame numbers are saved using unsigned long. Now if 64-bit >> PAGE_SHIFT, the result will have 52-bits as valid. On a 32= -bit system, 'unsigned long' is 32-bits. Thus, there is a potential loss of value when the result is stored as 'unsigned long'. To mitigate this issue, we check if the starting and end address can be contained within the range of physical address supported on the system. If = not, then an appropriate error is returned. Also, the end address is computed once and used when required. And replaced= u64 with uint64_t. Signed-off-by: Ayan Kumar Halder --- Changes from :- v1...v4 - NA. New patch introduced in v5. xen/arch/arm/domain_build.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 7d28b75517..b98ee506a8 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1637,15 +1637,23 @@ out: } =20 static int __init handle_pci_range(const struct dt_device_node *dev, - u64 addr, u64 len, void *data) + uint64_t addr, uint64_t len, void *data) { struct rangeset *mem_holes =3D data; paddr_t start, end; int res; + uint64_t end_addr =3D addr + len - 1; + + if ( addr !=3D (paddr_t)addr || end_addr !=3D (paddr_t)end_addr ) + { + printk(XENLOG_ERR "addr (0x%"PRIx64") or end_addr (0x%"PRIx64") ex= ceeds the maximum allowed width (%d bits) for physical address\n", + addr, end_addr, CONFIG_PADDR_BITS); + return -ERANGE; + } =20 start =3D addr & PAGE_MASK; - end =3D PAGE_ALIGN(addr + len); - res =3D rangeset_remove_range(mem_holes, PFN_DOWN(start), PFN_DOWN(end= - 1)); + end =3D PAGE_ALIGN(end_addr); + res =3D rangeset_remove_range(mem_holes, PFN_DOWN(start), PFN_DOWN(end= )); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -2330,11 +2338,19 @@ static int __init map_dt_irq_to_domain(const struct= dt_device_node *dev, } =20 int __init map_range_to_domain(const struct dt_device_node *dev, - u64 addr, u64 len, void *data) + uint64_t addr, uint64_t len, void *data) { struct map_range_data *mr_data =3D data; struct domain *d =3D mr_data->d; int res; + uint64_t end_addr =3D addr + len - 1; + + if ( addr !=3D (paddr_t)addr || end_addr !=3D (paddr_t)end_addr ) + { + printk(XENLOG_ERR "addr (0x%"PRIx64") or end_addr (0x%"PRIx64") ex= ceeds the maximum allowed width (%d bits) for physical address\n", + addr, end_addr, CONFIG_PADDR_BITS); + return -ERANGE; + } =20 /* * reserved-memory regions are RAM carved out for a special purpose. @@ -2345,13 +2361,13 @@ int __init map_range_to_domain(const struct dt_devi= ce_node *dev, strlen("/reserved-memory/")) !=3D 0 ) { res =3D iomem_permit_access(d, paddr_to_pfn(addr), - paddr_to_pfn(PAGE_ALIGN(addr + len - 1))); + paddr_to_pfn(PAGE_ALIGN(end_addr))); if ( res ) { printk(XENLOG_ERR "Unable to permit to dom%d access to" " 0x%"PRIx64" - 0x%"PRIx64"\n", d->domain_id, - addr & PAGE_MASK, PAGE_ALIGN(addr + len) - 1); + addr & PAGE_MASK, PAGE_ALIGN(end_addr) - 1); return res; } } @@ -2368,7 +2384,7 @@ int __init map_range_to_domain(const struct dt_device= _node *dev, { printk(XENLOG_ERR "Unable to map 0x%"PRIx64 " - 0x%"PRIx64" in domain %d\n", - addr & PAGE_MASK, PAGE_ALIGN(addr + len) - 1, + addr & PAGE_MASK, PAGE_ALIGN(end_addr) - 1, d->domain_id); return res; } --=20 2.17.1 From nobody Wed May 15 03:32:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1681407567; cv=pass; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:40.8052 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21a193d6-7f89-415a-42af-08db3c45ebbd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7618 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407568978100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restructure the code so that one can use pa_range_info[] table for both ARM_32 as well as ARM_64. Also, removed the hardcoding for P2M_ROOT_ORDER and P2M_ROOT_LEVEL as p2m_root_order can be obtained from the pa_range_info[].root_order and p2m_root_level can be obtained from pa_range_info[].sl0. Refer ARM DDI 0406C.d ID040418, B3-1345, "Use of concatenated first-level translation tables ...However, a 40-bit input address range with a translation granularity of = 4KB requires a total of 28 bits of address resolution. Therefore, a stage 2 translation that supports a 40-bit input address range requires two concate= nated first-level translation tables,..." Thus, root-order is 1 for 40-bit IPA on ARM_32. Refer ARM DDI 0406C.d ID040418, B3-1348, "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the i= nput address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 =3D 1 (maximum value) and VTCR.T0SZ =3D -8 when the size of i= nput address region is 2^40 bytes. Thus, pa_range_info[].t0sz =3D 1 (VTCR.S) | 8 (VTCR.T0SZ) ie 11000b which i= s 24. Signed-off-by: Ayan Kumar Halder --- Changes from - v3 - 1. New patch introduced in v4. 2. Restructure the code such that pa_range_info[] is used both by ARM_32 as well as ARM_64. v4 - 1. Removed the hardcoded definitions of P2M_ROOT_ORDER and P2M_ROOT_LE= VEL. The reason being root_order will not be always 1 (See the next patch). 2. Updated the commit message to explain t0sz, sl0 and root_order values for 32-bit IPA on Arm32. 3. Some sanity fixes. xen/arch/arm/include/asm/p2m.h | 8 +------- xen/arch/arm/p2m.c | 34 ++++++++++++++++++---------------- 2 files changed, 19 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 91df922e1c..28c68428d3 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -14,16 +14,10 @@ /* Holds the bit size of IPAs in p2m tables. */ extern unsigned int p2m_ipa_bits; =20 -#ifdef CONFIG_ARM_64 extern unsigned int p2m_root_order; extern unsigned int p2m_root_level; -#define P2M_ROOT_ORDER p2m_root_order +#define P2M_ROOT_ORDER p2m_root_order #define P2M_ROOT_LEVEL p2m_root_level -#else -/* First level P2M is always 2 consecutive pages */ -#define P2M_ROOT_ORDER 1 -#define P2M_ROOT_LEVEL 1 -#endif =20 struct domain; =20 diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 948f199d84..4583658f92 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -19,9 +19,9 @@ =20 #define INVALID_VMID 0 /* VMID 0 is reserved */ =20 -#ifdef CONFIG_ARM_64 unsigned int __read_mostly p2m_root_order; unsigned int __read_mostly p2m_root_level; +#ifdef CONFIG_ARM_64 static unsigned int __read_mostly max_vmid =3D MAX_VMID_8_BIT; /* VMID is by default 8 bit width on AArch64 */ #define MAX_VMID max_vmid @@ -2265,16 +2265,6 @@ void __init setup_virt_paging(void) /* Setup Stage 2 address translation */ register_t val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WB= WA; =20 -#ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) - panic("P2M: Not able to support %u-bit IPA at the moment\n", - p2m_ipa_bits); - - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits =3D 40; - val |=3D VTCR_T0SZ(0x18); /* 40 bit IPA */ - val |=3D VTCR_SL0(0x1); /* P2M starts at first level */ -#else /* CONFIG_ARM_64 */ static const struct { unsigned int pabits; /* Physical Address Size */ unsigned int t0sz; /* Desired T0SZ, minimum in comment */ @@ -2283,19 +2273,24 @@ void __init setup_virt_paging(void) } pa_range_info[] __initconst =3D { /* T0SZ minimum and SL0 maximum from ARM DDI 0487H.a Table D5-6 */ /* PA size, t0sz(min), root-order, sl0(max) */ - [0] =3D { 32, 32/*32*/, 0, 1 }, - [1] =3D { 36, 28/*28*/, 0, 1 }, - [2] =3D { 40, 24/*24*/, 1, 1 }, + [0] =3D { 40, 24/*24*/, 1, 1 }, +#ifdef CONFIG_ARM_64 + [1] =3D { 32, 32/*32*/, 0, 1 }, + [2] =3D { 36, 28/*28*/, 0, 1 }, [3] =3D { 42, 22/*22*/, 3, 1 }, [4] =3D { 44, 20/*20*/, 0, 2 }, [5] =3D { 48, 16/*16*/, 0, 2 }, [6] =3D { 52, 12/*12*/, 4, 2 }, [7] =3D { 0 } /* Invalid */ +#else + [1] =3D { 0 } /* Invalid */ +#endif }; =20 unsigned int i; unsigned int pa_range =3D 0x10; /* Larger than any possible value */ =20 +#ifdef CONFIG_ARM_64 /* * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured * with IPA bits =3D=3D PA bits, compare against "pabits". @@ -2309,6 +2304,9 @@ void __init setup_virt_paging(void) */ if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT ) max_vmid =3D MAX_VMID_16_BIT; +#else + p2m_ipa_bits =3D PADDR_BITS; +#endif =20 /* Choose suitable "pa_range" according to the resulted "p2m_ipa_bits"= . */ for ( i =3D 0; i < ARRAY_SIZE(pa_range_info); i++ ) @@ -2324,24 +2322,28 @@ void __init setup_virt_paging(void) if ( pa_range >=3D ARRAY_SIZE(pa_range_info) || !pa_range_info[pa_rang= e].pabits ) panic("Unknown encoding of ID_AA64MMFR0_EL1.PARange %x\n", pa_rang= e); =20 +#ifdef CONFIG_ARM_64 val |=3D VTCR_PS(pa_range); val |=3D VTCR_TG0_4K; =20 /* Set the VS bit only if 16 bit VMID is supported. */ if ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) val |=3D VTCR_VS; + + p2m_ipa_bits =3D 64 - pa_range_info[pa_range].t0sz; +#endif + val |=3D VTCR_SL0(pa_range_info[pa_range].sl0); val |=3D VTCR_T0SZ(pa_range_info[pa_range].t0sz); =20 p2m_root_order =3D pa_range_info[pa_range].root_order; p2m_root_level =3D 2 - pa_range_info[pa_range].sl0; - p2m_ipa_bits =3D 64 - pa_range_info[pa_range].t0sz; =20 printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", p2m_ipa_bits, pa_range_info[pa_range].pabits, ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); -#endif + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); =20 --=20 2.17.1 From nobody Wed May 15 03:32:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1681407567; cv=pass; d=zohomail.com; s=zohoarc; b=PjZ/RPSI6LIMJPGj36kl3Pj5eWCUeN/lKAq2rgUFmOc1WIfNCvrrE8B7rgtOKR3RiSkl01qwAqe4nxtFynZh7UJuvgJ1uJUcTO8zQhkTdDltwlO5D45jeQsU2LziAQJAyVvR8OFoFj4lA7yTzJ9a9qctN2erRX7AqKymBOudPg8= ARC-Message-Signature: i=2; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v5 10/10] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Thu, 13 Apr 2023 18:37:35 +0100 Message-ID: <20230413173735.48387-11-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230413173735.48387-1-ayan.kumar.halder@amd.com> References: <20230413173735.48387-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT089:EE_|SA1PR12MB5613:EE_ X-MS-Office365-Filtering-Correlation-Id: 963d6794-6a95-4b08-355b-08db3c45edca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 17:38:44.2105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 963d6794-6a95-4b08-355b-08db3c45edca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5613 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1681407568949100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 =3D 1 (maximum value) and VTCR.T0SZ =3D 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack.=20 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. xen/arch/arm/p2m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 4583658f92..746b6553e5 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2283,7 +2283,8 @@ void __init setup_virt_paging(void) [6] =3D { 52, 12/*12*/, 4, 2 }, [7] =3D { 0 } /* Invalid */ #else - [1] =3D { 0 } /* Invalid */ + [1] =3D { 32, 0/*0*/, 0, 1 }, + [2] =3D { 0 } /* Invalid */ #endif }; =20 --=20 2.17.1