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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- include/sysemu/hax.h | 2 ++ include/sysemu/kvm.h | 2 ++ include/sysemu/nvmm.h | 2 ++ include/sysemu/tcg.h | 2 ++ include/sysemu/whpx.h | 2 ++ include/sysemu/xen.h | 2 ++ 6 files changed, 12 insertions(+) diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h index bf8f99a824..80fc716f80 100644 --- a/include/sysemu/hax.h +++ b/include/sysemu/hax.h @@ -19,6 +19,8 @@ * */ =20 +/* header to be included in non-HAX-specific code */ + #ifndef QEMU_HAX_H #define QEMU_HAX_H =20 diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index c8281c07a7..cc6c678ed8 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -11,6 +11,8 @@ * */ =20 +/* header to be included in non-KVM-specific code */ + #ifndef QEMU_KVM_H #define QEMU_KVM_H =20 diff --git a/include/sysemu/nvmm.h b/include/sysemu/nvmm.h index 833670fccb..be7bc9a62d 100644 --- a/include/sysemu/nvmm.h +++ b/include/sysemu/nvmm.h @@ -7,6 +7,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-NVMM-specific code */ + #ifndef QEMU_NVMM_H #define QEMU_NVMM_H =20 diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 53352450ff..5e2ca9aab3 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-TCG-specific code */ + #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H =20 diff --git a/include/sysemu/whpx.h b/include/sysemu/whpx.h index 2889fa2278..781ca5b2b6 100644 --- a/include/sysemu/whpx.h +++ b/include/sysemu/whpx.h @@ -10,6 +10,8 @@ * */ =20 +/* header to be included in non-WHPX-specific code */ + #ifndef QEMU_WHPX_H #define QEMU_WHPX_H =20 diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h index 0ca25697e4..bc13ad5692 100644 --- a/include/sysemu/xen.h +++ b/include/sysemu/xen.h @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ =20 +/* header to be included in non-Xen-specific code */ + #ifndef SYSEMU_XEN_H #define SYSEMU_XEN_H =20 --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-accel-ops-mttcg.c | 4 ---- accel/tcg/tcg-accel-ops-rr.c | 3 --- target/i386/whpx/whpx-accel-ops.c | 3 --- 3 files changed, 10 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index d50239e0e2..19cfb26c02 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -152,8 +152,4 @@ void mttcg_start_vcpu_thread(CPUState *cpu) =20 qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); - -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 290833a37f..dafff71530 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -291,9 +291,6 @@ void rr_start_vcpu_thread(CPUState *cpu) =20 single_tcg_halt_cond =3D cpu->halt_cond; single_tcg_cpu_thread =3D cpu->thread; -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } else { /* we share the thread */ cpu->thread =3D single_tcg_cpu_thread; diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-acce= l-ops.c index e8dc4b3a47..67cad86720 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -71,9 +71,6 @@ static void whpx_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, whpx_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif } =20 static void whpx_kick_vcpu_thread(CPUState *cpu) --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680689941; cv=none; d=zohomail.com; s=zohoarc; b=jdSokRCW4d6GPoXolzmPJg7luVA8tsul/qDA5Raqm825kj5Uz7V1bkwYWoZXwhQJiVOQw26GQ1qHpP7pezbztLVO/+a7T/ziHbfyqppSCVJMS8itnQhSKnPisFrC5OMqe/B2ur1r+vM7xdeU3Oc+vm2m9TyTmnqacitGQc+V8TI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680689941; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E6NW9VhhS5fLeVwZeTyWWyTbAHfvPOC/r0zI8X/AYhw=; b=fiWKm/Te8hGWCyakLZaFXnzR5ZiacJAy5JnIHyCUaOP6GtArC7rqa3SsrygAaYLDz9eNgJw8medn0VKTPCfODrBqgvBOpxJaWiPzk1hz3vX4B+Cy+2B/QRQj7X3EU+cmbRzd8LhKfDk5yK/vtC3aflGLlXaw8ENo3n60RLQ9E2U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1680689941185602.5100457136772; Wed, 5 Apr 2023 03:19:01 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.518393.804898 (Exim 4.92) (envelope-from ) id 1pk0Ds-00036C-Et; Wed, 05 Apr 2023 10:18:36 +0000 Received: by outflank-mailman (output) from mailman id 518393.804898; Wed, 05 Apr 2023 10:18:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pk0Ds-000365-AP; Wed, 05 Apr 2023 10:18:36 +0000 Received: by outflank-mailman (input) for mailman id 518393; Wed, 05 Apr 2023 10:18:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pk0Dr-0002Na-Sm for xen-devel@lists.xenproject.org; Wed, 05 Apr 2023 10:18:35 +0000 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [2a00:1450:4864:20::42b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3893df93-d39b-11ed-b464-930f4c7d94ae; Wed, 05 Apr 2023 12:18:34 +0200 (CEST) Received: by mail-wr1-x42b.google.com with SMTP id y14so35677419wrq.4 for ; Wed, 05 Apr 2023 03:18:34 -0700 (PDT) Received: from localhost.localdomain (4ab54-h01-176-184-52-81.dsl.sta.abo.bbox.fr. [176.184.52.81]) by smtp.gmail.com with ESMTPSA id d9-20020adff849000000b002c56af32e8csm14637033wrq.35.2023.04.05.03.18.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:18:33 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3893df93-d39b-11ed-b464-930f4c7d94ae DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E6NW9VhhS5fLeVwZeTyWWyTbAHfvPOC/r0zI8X/AYhw=; b=FrtFKE2hFxCwSIOxwL7fJNJgclFtRZYFCKSwPQeumlgt6bklL8ZJLOhaxRanBaGmBN sSSdwoBuo0PWQIPC5aVYpH3V4lrlZrxSnF6ec08aPzNngc+4NCJth/v+YEXjEI5hAYZ7 deplHkaFXLIdswcAyfQjoGU7HHGPGzJHJzztDL7n6LAkZeMYnyvPoi+3fXYTgBgP5XWs cPr7wmMyCDh4HsAHrXF/xlBABJq7EFQwNi0Rj4haWnYMHlXIAYY+Lsa8OGwO4Mt6ZR/d e7uyZyaesG4XjKKufoRM2SpXpgdAnFrSp25xtnMkjXzs/M6Ow7DNjd1C6Ovjn8q1Umho 74DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E6NW9VhhS5fLeVwZeTyWWyTbAHfvPOC/r0zI8X/AYhw=; b=QlO71eGYcc4/A839ZcUOtT1xhGgo6p6sBc0/SoL0yHAzIMQ2534YlBNBp/v1Tr4fai s3vVURIQcv4z0XHckrG+VVXXPGJ3guwo0ZYGtzdlP/F9OslCrk7a6uBWuLwPH3IFiRca Qmq3DXvB57qGFi/61LUjorru7kUl/50Y/OMz8j8tOf4MJIk8el54lkBT8Rv+aCPNuNu/ sXErcQeE+Chm3WRn/e1NHkM6aGfufph5Ci7HvR1BFJAEIp+ApEOifPcEB52ZxOt7NFjP O5KaYAgTE8DzLW/6tkpvcuiZ41x4EPYz59oomc7JclN1ipEOlpkpR83VtMQfuRIHYnGn 3O2g== X-Gm-Message-State: AAQBX9fEhyJijfAKsl7+kEZRdXE2m0VA9xBYCVwsI0j8AW0RQfIUgtT9 OxitiO7hgJWadZg4vPhur9TgRQ== X-Google-Smtp-Source: AKy350YkinPPwbt/c64vUzk9lM4SXacH8xjrAIzv8V1BeCK80tQHniLUzIE+5w/+4XbN335yprpGWw== X-Received: by 2002:a5d:4d11:0:b0:2ce:9819:1c1e with SMTP id z17-20020a5d4d11000000b002ce98191c1emr3913343wrt.30.1680689913858; Wed, 05 Apr 2023 03:18:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/14] accel: Fix a leak on Windows HAX Date: Wed, 5 Apr 2023 12:18:00 +0200 Message-Id: <20230405101811.76663-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689941870100001 hThread is only used on the error path in hax_kick_vcpu_thread(). Fixes: b0cb0a66d6 ("Plumb the HAXM-based hardware acceleration support") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/hax/hax-all.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 3e5992a63b..a2321a1eff 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -205,6 +205,9 @@ int hax_vcpu_destroy(CPUState *cpu) */ hax_close_fd(vcpu->fd); hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; +#ifdef _WIN32 + CloseHandle(cpu->hThread); +#endif g_free(vcpu); return 0; } --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680689947; cv=none; d=zohomail.com; s=zohoarc; b=geEbh2X1gK26LduPV3W3bRDAACT+3QndRKJ9MwWM2IbvNncfCO7kp6MC+sX9vxO37XyCYwy5MM4ssXeaba7ZRxVx/kyTHQ0WSfmll8T0+PCKN4q9sGw8JkQQJm28uZala8lAcHAsJ+4qaH4ZN539idstoxgGbhAcMVHhv+S1l5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680689947; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IGm3E04zIWsYk05zgucyUicl5+3W8OYlCuN37xDTmqU=; b=EFqx8SxNVtO0VtKRKxz3RMKT4nnrkxWME5TWuXg8t4tcM13/2A8wHaiKMd41u0uCIj9b/MG1OM03JTQPVUycjZDToS3tsIX5ZPuhVdqDGk89oc5eoGOO7dzpp6iSnxblgaQHTJpHTqYesXgAj0z3M8l2QQKwzSrvLe1ZNFvpD2M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 168068994716534.3381568974354; Wed, 5 Apr 2023 03:19:07 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.518395.804908 (Exim 4.92) (envelope-from ) id 1pk0Dx-0003Yv-Mj; Wed, 05 Apr 2023 10:18:41 +0000 Received: by outflank-mailman (output) from mailman id 518395.804908; Wed, 05 Apr 2023 10:18:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pk0Dx-0003Ym-Iu; Wed, 05 Apr 2023 10:18:41 +0000 Received: by outflank-mailman (input) for mailman id 518395; Wed, 05 Apr 2023 10:18:40 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pk0Dw-00024X-Nv for xen-devel@lists.xenproject.org; Wed, 05 Apr 2023 10:18:40 +0000 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [2a00:1450:4864:20::329]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 3c165dc3-d39b-11ed-85db-49a42c6b2330; Wed, 05 Apr 2023 12:18:40 +0200 (CEST) Received: by mail-wm1-x329.google.com with SMTP id m6-20020a05600c3b0600b003ee6e324b19so21676991wms.1 for ; Wed, 05 Apr 2023 03:18:40 -0700 (PDT) Received: from localhost.localdomain (4ab54-h01-176-184-52-81.dsl.sta.abo.bbox.fr. [176.184.52.81]) by smtp.gmail.com with ESMTPSA id l6-20020a1c7906000000b003ee4e99a8f6sm1696262wme.33.2023.04.05.03.18.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:18:39 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3c165dc3-d39b-11ed-85db-49a42c6b2330 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IGm3E04zIWsYk05zgucyUicl5+3W8OYlCuN37xDTmqU=; b=rTu1tRZPqV4LFx/UoOZi2WLzS6khixq6d/WYxFS7eNNn/OYGeFnv0qc3Qcr02VSKxy rb660oY/fmNu7J89tEYsSKeFFMuIPWe0bwl6jY9zC3o3nLjl9EKCdNxVkCbBuJ6lm5CH gjTz1i3s9XYei/E+itmN9I/+2jlgOY1BBVZJB9fjEYyywfgateusSwusPqpu7NrWhMR0 GMl837ggRVzo1kt3Z33apYrhv71R+7WptfZnBSbUKuQc75ogJNF4kCG2j8Ggv1YnBRCy yVn/ZgcJgjoRbF4Cbyz/wswjzVjQZxiYa1fX9y35/BD8s5WDn2b95Nx3tL6XSawRO0qk iJOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IGm3E04zIWsYk05zgucyUicl5+3W8OYlCuN37xDTmqU=; b=48W1T2IaEf288nn7yfly3SGwmytE2z05UcIbVEjvOhBS0U/It01nMMQxkNiLXdRXRn X6HieE5DWVJ0ug2s2PqgAK6QzXz1fJarjAqOuj5WOUYf9ASbNMUEuy2NasnmfVTYy0f1 42Rs0JXpeMyxtkrixDPuspTI6Ezayv68VfYgUa795y/W9Ahflxs2b5cm963dPvSOEyg+ dJqnGZPQNEqOwy/DuzZ8wPCRhQ2CaqCLwKXOySKq23Gft5zhc39k7M3vCLTPVGudiz1l WHVPDzfZzx+AqHEIMZyu/WXi6eFTLEg+3lBIQFJNasK0OOpI7vV6awsti9S99Ud755qy A6Xw== X-Gm-Message-State: AAQBX9fG1/zDNeZ119JRmWPGiH/38FJMyANdCrMbAzULANK4oLfjfBOb Xi2X8hwSreW61CXkMm9OSoRWmg== X-Google-Smtp-Source: AKy350ZDfAFPi7DjfgX/oekuSK5IMwY5EAU6LrxLx1bImlo8Bj5BMxd5ZdtWz6ZThOU3rdF/7XqStA== X-Received: by 2002:a1c:770e:0:b0:3ed:8780:f27b with SMTP id t14-20020a1c770e000000b003ed8780f27bmr4338493wmi.16.1680689919738; Wed, 05 Apr 2023 03:18:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/14] accel: Destroy HAX vCPU threads once done Date: Wed, 5 Apr 2023 12:18:01 +0200 Message-Id: <20230405101811.76663-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689947767100004 When the vCPU thread finished its processing, destroy it and signal its destruction to generic vCPU management layer. Add a sanity check for the vCPU accelerator context. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/hax/hax-accel-ops.c | 3 +++ target/i386/hax/hax-all.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index 18114fe34d..0157a628a3 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -53,6 +53,8 @@ static void *hax_cpu_thread_fn(void *arg) =20 qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); + hax_vcpu_destroy(cpu); + cpu_thread_signal_destroyed(cpu); rcu_unregister_thread(); return NULL; } @@ -69,6 +71,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); + assert(cpu->hax_vcpu); #ifdef _WIN32 cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index a2321a1eff..38a4323a3c 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -209,6 +209,7 @@ int hax_vcpu_destroy(CPUState *cpu) CloseHandle(cpu->hThread); #endif g_free(vcpu); + cpu->hax_vcpu =3D NULL; return 0; } =20 --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680689954; cv=none; d=zohomail.com; s=zohoarc; b=K5SqptAxRO1HGbO7UY2T57JG/YGLC52lUTwu0IdpmnmKPb/g4NuAudllOjQLxq3DtHwgEdqjpcVi9EdQXVCNde5icQ9uCeAYpjXDRdMFmmFbw8dNJrBDRutSEkDf6/oQSJub2Swi6mRDaP/XK4YJpGg4y7LyVAdrWVQhJJvAdYM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680689954; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JKKj8/4pIvX0Y2G0Iw2NvkVvuNOgIGf3wL1krYyOhFI=; b=BOPbXsIcu86uwNTNQ7FAzzwMlCynQjTO3QBa3EUPw7iROVF9gwgVajNCSYEJn+mNYbZkNJgA1ZRBtlNRtkZbiAf+sGkbqN1mPTC04MoPq9D2lEwjWChR7WFhgMKeOdm8cLawSlnOMfX3+b5fDiVBgTHkLM8UhsxZnnhbAYbM9ow= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1680689954772618.3976188694755; Wed, 5 Apr 2023 03:19:14 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.518400.804917 (Exim 4.92) (envelope-from ) id 1pk0E5-0004EL-Vm; Wed, 05 Apr 2023 10:18:49 +0000 Received: by outflank-mailman (output) from mailman id 518400.804917; Wed, 05 Apr 2023 10:18:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pk0E5-0004EE-Su; Wed, 05 Apr 2023 10:18:49 +0000 Received: by outflank-mailman (input) for mailman id 518400; Wed, 05 Apr 2023 10:18:49 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pk0E4-0002Na-RP for xen-devel@lists.xenproject.org; Wed, 05 Apr 2023 10:18:48 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 403c51b8-d39b-11ed-b464-930f4c7d94ae; Wed, 05 Apr 2023 12:18:47 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id j24so35697941wrd.0 for ; Wed, 05 Apr 2023 03:18:47 -0700 (PDT) Received: from localhost.localdomain (4ab54-h01-176-184-52-81.dsl.sta.abo.bbox.fr. [176.184.52.81]) by smtp.gmail.com with ESMTPSA id c1-20020adfef41000000b002d322b9a7f5sm14646618wrp.88.2023.04.05.03.18.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:18:46 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 403c51b8-d39b-11ed-b464-930f4c7d94ae DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689926; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JKKj8/4pIvX0Y2G0Iw2NvkVvuNOgIGf3wL1krYyOhFI=; b=zZVWJRJJOaN+7Gbu5U00rRVxIF+M1REi0nasLd2+TX7rCZ676M8HfGZvzPUiiR+jmJ LzK21sAAN+g/5CA7pY0t71M+JRU/D0i2mKppiG11wKsb+ATVhKWStv+h8AcYfYWJ7o7q ZkVpkMfk04QTu63lwsYX09N6qWIm7uJJV67xns5BXbF7sXdcTtMRBlCsegTqDBPUcmBh ARAhBXK711g76VGI42qECVpEmFzwZ0PK4jFw+pyEwqyKB+BJxwBLM0WD1/uRxXapkmvf Ej+a+b8eIjRl0xMwS3Wlq5n5DK62HsO8B/0gtpHvOMwDIRcustaLrz9inDPWuLWLPEfj UczQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689926; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JKKj8/4pIvX0Y2G0Iw2NvkVvuNOgIGf3wL1krYyOhFI=; b=gMbQmKSDOi+AYxv+OFNiSssECuzDxVZ4+jQ0vkHHd6sL12+i9rfOkQ3z9HIyzHKJEG a2kZl/t62U5ffqiujfStBt5Hq5t+Kx47ImZNQw986Rg6JSQ5nLDH3q2o2QYQuXuiHgIZ 2iNAshx14cRuF2GeAKAXDAb1oBzgfODR4DjyZhz6r1qx8CPm3KUfltkotAFKnkYvwrfq UeBIIf1UUmc1gNd9LLhOpX1FJGL9K7PiDEUjo/MoCRF37xTZLp1XuTlwtlYVL7ZeL43T yfOOvIVpkoJfaSrOZWxMCf/bw0/NWNkKyhbYZzKG5qvPdGxh+U6byCt6KA1Aw+uC7QpQ NEyQ== X-Gm-Message-State: AAQBX9fp/OrcSgArGhdq8SCnz89bmgYh+rQnvv7KegMyR02DqHm90Mgv /hJ4OcDAhyZfEnkFjhhw7oufog== X-Google-Smtp-Source: AKy350bkMz7m3CqlZANDFC+N8H247sFug5Oc9sidBbssiHByDywSp20m46NTY3RF7XV/gx2ANc24Hw== X-Received: by 2002:a5d:68ca:0:b0:2e4:bfa0:8c32 with SMTP id p10-20020a5d68ca000000b002e4bfa08c32mr3774527wrw.47.1680689926542; Wed, 05 Apr 2023 03:18:46 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Reinoud Zandijk , Sunil Muthuswamy Subject: [PATCH 05/14] accel: Rename 'hax_vcpu' as 'accel' in CPUState Date: Wed, 5 Apr 2023 12:18:02 +0200 Message-Id: <20230405101811.76663-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689955312100001 All accelerators will share a single opaque context in CPUState. Start by renaming 'hax_vcpu' as 'accelCPUState'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- target/i386/hax/hax-accel-ops.c | 2 +- target/i386/hax/hax-all.c | 18 +++++++++--------- target/i386/nvmm/nvmm-all.c | 6 +++--- target/i386/whpx/whpx-all.c | 6 +++--- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 397fd3ac68..193494cde4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -442,7 +442,7 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hax_vcpu_state *hax_vcpu; + struct hax_vcpu_state *accel; =20 struct hvf_vcpu_state *hvf; =20 diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index 0157a628a3..a8512efcd5 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -71,7 +71,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu->cpu_index); qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); - assert(cpu->hax_vcpu); + assert(cpu->accel); #ifdef _WIN32 cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 38a4323a3c..3865ff9419 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D env_cpu(env)->hax_vcpu; + struct hax_vcpu_state *vcpu =3D env_cpu(env)->accel; if (!vcpu) { return HAX_INVALID_FD; } @@ -188,7 +188,7 @@ int hax_vcpu_create(int id) =20 int hax_vcpu_destroy(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!hax_global.vm) { fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); @@ -209,7 +209,7 @@ int hax_vcpu_destroy(CPUState *cpu) CloseHandle(cpu->hThread); #endif g_free(vcpu); - cpu->hax_vcpu =3D NULL; + cpu->accel =3D NULL; return 0; } =20 @@ -223,7 +223,7 @@ int hax_init_vcpu(CPUState *cpu) exit(-1); } =20 - cpu->hax_vcpu =3D hax_global.vm->vcpus[cpu->cpu_index]; + cpu->accel =3D hax_global.vm->vcpus[cpu->cpu_index]; cpu->vcpu_dirty =3D true; qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr); =20 @@ -415,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 /* @@ -447,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) =20 void hax_raise_event(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!vcpu) { return; @@ -468,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) int ret =3D 0; CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct hax_vcpu_state *vcpu =3D cpu->hax_vcpu; + struct hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 if (!hax_enabled()) { @@ -1114,8 +1114,8 @@ void hax_reset_vcpu_state(void *opaque) { CPUState *cpu; for (cpu =3D first_cpu; cpu !=3D NULL; cpu =3D CPU_NEXT(cpu)) { - cpu->hax_vcpu->tunnel->user_event_pending =3D 0; - cpu->hax_vcpu->tunnel->ready_for_interrupt_injection =3D 0; + cpu->accel->tunnel->user_event_pending =3D 0; + cpu->accel->tunnel->ready_for_interrupt_injection =3D 0; } } =20 diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b75738ee9c..cf4f0af24b 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -52,7 +52,7 @@ static struct qemu_machine qemu_mach; static struct qemu_vcpu * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->hax_vcpu; + return (struct qemu_vcpu *)cpu->accel; } =20 static struct nvmm_machine * @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->hax_vcpu =3D (struct hax_vcpu_state *)qcpu; + cpu->accel =3D (struct hax_vcpu_state *)qcpu; =20 return 0; } @@ -1030,7 +1030,7 @@ nvmm_destroy_vcpu(CPUState *cpu) struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); - g_free(cpu->hax_vcpu); + g_free(cpu->accel); } =20 /* -----------------------------------------------------------------------= --- */ diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 52af81683c..d1ad6f156a 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -262,7 +262,7 @@ static bool whpx_has_xsave(void) =20 static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu) { - return (struct whpx_vcpu *)cpu->hax_vcpu; + return (struct whpx_vcpu *)cpu->accel; } =20 static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, @@ -2258,7 +2258,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->hax_vcpu =3D (struct hax_vcpu_state *)vcpu; + cpu->accel =3D (struct hax_vcpu_state *)vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id l18-20020adfe592000000b002c5534db60bsm14659802wrm.71.2023.04.05.03.18.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:18:56 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 461dd625-d39b-11ed-b464-930f4c7d94ae DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6tftOh0BEcl8WGCnB6MC//b/5zdxDYjL5goslSUZJws=; b=yPbFhCwGeiCV4thDFylzfI/HwDyG5hzAj4MOzixAzKF25y0uzdJIpFxXuplWi9vjHl /pOllACxcM9z8xuQDdRw6M+2mhe134Dj+vuHZkVEnkH+iEToGCJ/gsI/e1vCCyvskKgL u3Mvtb6MFtubWA04wRDH74PCwnCAY/i2SngbnxTxDSfmMlutOwruOtZ/lxg1P8mD8QYc drS8XHL8crBE+lDtcMRmYU91Oi0ecrSiQz2TIPt5ieGnpP+PuypBCXiw3EMqe02ST1rI wsMGZCOdiVWLzTUX7Ca+wgJTbV5lZ6+mNbhvpM8NJsdWCvazgFD200r/8aPIN7ho8VP6 onNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6tftOh0BEcl8WGCnB6MC//b/5zdxDYjL5goslSUZJws=; b=20XlBoaIgxqLyPHspG5cAGPtye59aQMVcmYsl32UwxVf4NrX+gOrYG5gtboAPSTAQC yLuyKS0TCWumPj7AuiDkxyYahWSDfVgQxMTJdz0CkM1xlPkX+bROXoWVMjk4MabqZ+Jh DRTiItiNZoFR/qJ/lSc5xGiDd3Qwk/tDNesNjh7ui6BeBSuzku0ae5AjJh1ooSv9YJ7D N0hW2w8Dy35GoEyulwi3XhedqgeM9UeA+dzszJsZFZGgURmUPGHvJoNcr5h6RWcYe2x/ ajvrYtqQfopbxUurulANys721/AF+LWZZD/OTx2fXpynL4a9bWn2sLZKKi7BxSNQeXlp xcRg== X-Gm-Message-State: AAQBX9fZa8rtByuIva3RTlYmd567w3Cayzb6nmFrIRcno2dR+5lt93qP UWm4JTVCVDdoQjJb6V1JieSAaw== X-Google-Smtp-Source: AKy350bSSR7dvtgFBRLgKNCzhtqOOQSU+0g5L1LOMUC3nb32jDJaawY9UmLjKaQ4gtEPNgL7gGWKbg== X-Received: by 2002:a5d:610a:0:b0:2d5:553a:93ac with SMTP id v10-20020a5d610a000000b002d5553a93acmr3978963wrt.7.1680689936532; Wed, 05 Apr 2023 03:18:56 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 06/14] accel: Use a typedef for struct hax_vcpu_state Date: Wed, 5 Apr 2023 12:18:03 +0200 Message-Id: <20230405101811.76663-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689967841100001 Use a type definition instead of explicit structure. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/hax/hax-i386.h | 10 +++++----- target/i386/hax/hax-all.c | 16 ++++++++-------- target/i386/hax/hax-posix.c | 4 ++-- target/i386/hax/hax-windows.c | 4 ++-- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index 409ebdb4af..3cb3b9bbd0 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -25,12 +25,12 @@ typedef HANDLE hax_fd; #endif =20 extern struct hax_state hax_global; -struct hax_vcpu_state { +typedef struct hax_vcpu_state { hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; unsigned char *iobuf; -}; +} hax_vcpu_state; =20 struct hax_state { hax_fd fd; /* the global hax device interface */ @@ -46,7 +46,7 @@ struct hax_vm { hax_fd fd; int id; int numvcpus; - struct hax_vcpu_state **vcpus; + hax_vcpu_state **vcpus; }; =20 /* Functions exported to host specific mode */ @@ -57,7 +57,7 @@ int valid_hax_tunnel_size(uint16_t size); int hax_mod_version(struct hax_state *hax, struct hax_module_version *vers= ion); int hax_inject_interrupt(CPUArchState *env, int vector); struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus); -int hax_vcpu_run(struct hax_vcpu_state *vcpu); +int hax_vcpu_run(hax_vcpu_state *vcpu); int hax_vcpu_create(int id); void hax_kick_vcpu_thread(CPUState *cpu); =20 @@ -76,7 +76,7 @@ int hax_host_create_vm(struct hax_state *hax, int *vm_id); hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id); int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid); hax_fd hax_host_open_vcpu(int vmid, int vcpuid); -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu); +int hax_host_setup_vcpu_channel(hax_vcpu_state *vcpu); hax_fd hax_mod_open(void); void hax_memory_init(void); =20 diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index 3865ff9419..a55b18f353 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -62,7 +62,7 @@ int valid_hax_tunnel_size(uint16_t size) =20 hax_fd hax_vcpu_get_fd(CPUArchState *env) { - struct hax_vcpu_state *vcpu =3D env_cpu(env)->accel; + hax_vcpu_state *vcpu =3D env_cpu(env)->accel; if (!vcpu) { return HAX_INVALID_FD; } @@ -136,7 +136,7 @@ static int hax_version_support(struct hax_state *hax) =20 int hax_vcpu_create(int id) { - struct hax_vcpu_state *vcpu =3D NULL; + hax_vcpu_state *vcpu =3D NULL; int ret; =20 if (!hax_global.vm) { @@ -149,7 +149,7 @@ int hax_vcpu_create(int id) return 0; } =20 - vcpu =3D g_new0(struct hax_vcpu_state, 1); + vcpu =3D g_new0(hax_vcpu_state, 1); =20 ret =3D hax_host_create_vcpu(hax_global.vm->fd, id); if (ret) { @@ -188,7 +188,7 @@ int hax_vcpu_create(int id) =20 int hax_vcpu_destroy(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!hax_global.vm) { fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu= _id); @@ -263,7 +263,7 @@ struct hax_vm *hax_vm_create(struct hax_state *hax, int= max_cpus) } =20 vm->numvcpus =3D max_cpus; - vm->vcpus =3D g_new0(struct hax_vcpu_state *, vm->numvcpus); + vm->vcpus =3D g_new0(hax_vcpu_state *, vm->numvcpus); for (i =3D 0; i < vm->numvcpus; i++) { vm->vcpus[i] =3D NULL; } @@ -415,7 +415,7 @@ static int hax_handle_io(CPUArchState *env, uint32_t df= , uint16_t port, static int hax_vcpu_interrupt(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 /* @@ -447,7 +447,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) =20 void hax_raise_event(CPUState *cpu) { - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; =20 if (!vcpu) { return; @@ -468,7 +468,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) int ret =3D 0; CPUState *cpu =3D env_cpu(env); X86CPU *x86_cpu =3D X86_CPU(cpu); - struct hax_vcpu_state *vcpu =3D cpu->accel; + hax_vcpu_state *vcpu =3D cpu->accel; struct hax_tunnel *ht =3D vcpu->tunnel; =20 if (!hax_enabled()) { diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c index ac1a51096e..8ee247845b 100644 --- a/target/i386/hax/hax-posix.c +++ b/target/i386/hax/hax-posix.c @@ -205,7 +205,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid) return fd; } =20 -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu) +int hax_host_setup_vcpu_channel(hax_vcpu_state *vcpu) { int ret; struct hax_tunnel_info info; @@ -227,7 +227,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *= vcpu) return 0; } =20 -int hax_vcpu_run(struct hax_vcpu_state *vcpu) +int hax_vcpu_run(hax_vcpu_state *vcpu) { return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); } diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 59afa213a6..08ec93a256 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -301,7 +301,7 @@ hax_fd hax_host_open_vcpu(int vmid, int vcpuid) return hDeviceVCPU; } =20 -int hax_host_setup_vcpu_channel(struct hax_vcpu_state *vcpu) +int hax_host_setup_vcpu_channel(hax_vcpu_state *vcpu) { hax_fd hDeviceVCPU =3D vcpu->fd; int ret; @@ -327,7 +327,7 @@ int hax_host_setup_vcpu_channel(struct hax_vcpu_state *= vcpu) return 0; } =20 -int hax_vcpu_run(struct hax_vcpu_state *vcpu) +int hax_vcpu_run(hax_vcpu_state *vcpu) { int ret; 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id f23-20020a7bcd17000000b003eb966d39desm1762763wmj.2.2023.04.05.03.19.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:03 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4a6f4b4b-d39b-11ed-85db-49a42c6b2330 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689944; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0bXZGRuYaUWuS+waIlKd8VQv2t6ejAS6CfkyaECLnt0=; b=LIHJIKyuI7acMvt8rBrVg6eWFKgBkrJ3/b0arkph/DUHa0BLbU93H3b1GIwH92R4Zy +uvzlTCyUDlYf/j4al5z+wQUHx97GbeXdG9kBiFdMAHyviECH6MqzuY0CNALDN8Ap5Kl ApXLzY1U62e1horWK6Vt/U+csJdBfLpJs0pQHuzAzmEZEThhQrNbsPj75PM04Up7HqEo 3/73NqiS9NmRAA8IVw8pYFlfJUzbpOMYXpCwDL0opeM+q2GUARMOBu22yoM5Hh8oWG8N qONWesA/cQ68zjyXExg7MhsK0M/t5sPv8yhjX2pllIkZYpVHgJWQ2hcKuv9wWGPJXdDK ogxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689944; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0bXZGRuYaUWuS+waIlKd8VQv2t6ejAS6CfkyaECLnt0=; b=WF0c0ek4QkPZ8AQoRDWY3zdt98WsSNb0Trd+pbXRgem+gdY/6mFFCD4sGD3FQutWQF hPfG5hVNX5ayeDIL321OzbKXi5sUhKW3xudxoQEXAm0xCdFDchAthvCsZ1tk2zyVM8Fn Yyv+B86xJyeK6GR6beAHwJ8is7HIdGV+slxP0xvDqE2YWJ4PoPTHfcGJqFgywxlFNFkt 1+rg0boZy8bn4wo1aaK2PuCcPTdCyp+ow/qalK93j0pqHKgp0+wcXzuW/NtG3bzGFW7H AM1OrlIQCEaBqwpb8aiynMKKklkUuVoDXqnmny0SlHVrff3TxkqkO59O/L86KLCG0JB8 /hig== X-Gm-Message-State: AAQBX9eEnmHpVNebFr7b2XZbQqYQhPscrSQPgaiuihRa9wFuCjr7X65E T29VFWxEbVcQddLhUuGUbnu2jwan/K7RUk0AvaY= X-Google-Smtp-Source: AKy350aOrY2Jw4wGetHTWaGkqVDR1/1hOaALytcr5CxarBrtXg4uhD0qN6hOdWeu8PVqJ7zVJHPs0g== X-Received: by 2002:a7b:ca48:0:b0:3ee:ed5:6115 with SMTP id m8-20020a7bca48000000b003ee0ed56115mr4226349wml.19.1680689943740; Wed, 05 Apr 2023 03:19:03 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Reinoud Zandijk , Sunil Muthuswamy Subject: [PATCH 07/14] accel: Rename struct hax_vcpu_state -> struct AccelvCPUState Date: Wed, 5 Apr 2023 12:18:04 +0200 Message-Id: <20230405101811.76663-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689974758100001 We want all accelerators to share the same opaque pointer in CPUState. Start with the HAX context, renaming its forward declarated structure 'hax_vcpu_state' as 'AccelvCPUState'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 7 +++---- target/i386/hax/hax-i386.h | 3 ++- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 193494cde4..173f47d24e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -235,8 +235,7 @@ typedef struct SavedIOTLB { =20 struct KVMState; struct kvm_run; - -struct hax_vcpu_state; +struct AccelvCPUState; struct hvf_vcpu_state; =20 /* work queue */ @@ -305,6 +304,7 @@ struct qemu_work_item; * @next_cpu: Next CPU sharing TB cache. * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. + * @accel: Pointer to accelerator specific state. * @kvm_fd: vCPU file descriptor for KVM. * @work_mutex: Lock to prevent multiple access to @work_list. * @work_list: List of pending asynchronous work. @@ -423,6 +423,7 @@ struct CPUState { uint32_t can_do_io; int32_t exception_index; =20 + struct AccelvCPUState *accel; /* shared by kvm, hax and hvf */ bool vcpu_dirty; =20 @@ -442,8 +443,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hax_vcpu_state *accel; - struct hvf_vcpu_state *hvf; =20 /* track IOMMUs whose translations we've cached in the TCG TLB */ diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index 3cb3b9bbd0..d11d43e857 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -25,7 +25,8 @@ typedef HANDLE hax_fd; #endif =20 extern struct hax_state hax_global; -typedef struct hax_vcpu_state { + +typedef struct AccelvCPUState { hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index cf4f0af24b..3c7bdd560f 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct hax_vcpu_state *)qcpu; + cpu->accel =3D (struct AccelvCPUState *)qcpu; =20 return 0; } diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d1ad6f156a..70eadb7f05 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2258,7 +2258,7 @@ int whpx_init_vcpu(CPUState *cpu) =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct hax_vcpu_state *)vcpu; + cpu->accel =3D (struct AccelvCPUState *)vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); =20 --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id y5-20020a1c4b05000000b003ede06f3178sm1730449wma.31.2023.04.05.03.19.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RAVav4ABEpIiF2Ib5SEI8jHJn5J3YAuyzrKJBGzco1s=; b=hHxXSS6O9+86vT2m6d0DTc+hiT8gaRNGAVM+7W9qw5K7dcdKYYbh0E7lvSzpkYn368 fOMNZZP/1e+qRYjuveniW+hqJPeXRIDEN0l73ChMXeJHLmaPOblTjTKGwBGBBShSS3FY MjxZ0uY781JiDGIyrZ2Wmf9jZfbEMqhXfcJrGMdfGEFfNJ40NRBoRK/JRBa+tS5fdI92 eU/ZF0jqD4wzOX6Sr/86Q1BA8EHQgHGTKipyyzmSWtpcvo657D+2/e3mC0kuVQ+XljSH s07gbWhPjhP4utq/Kj/s6MnBKF2BXRP7AOXf6kw6C44JcSBNEeM091V355Hm/Q/Y0H3V Xa9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RAVav4ABEpIiF2Ib5SEI8jHJn5J3YAuyzrKJBGzco1s=; b=OUngUbJGNQXtVf3JTT69r4npclrbK1pErGx5SRVnX72d6YC0VcRZDYGjFpc8ZgxFgR isUNcLtG+pCHmWtns74SEoqpGcRVQW/2nJLYoPCzWqrULg08gccy/+oixrtO3ZGp05Zj Ku3UhkGi24jI0JHYfeQfw3IjqUb2uXCOwkThoffiG+vF2TSbQJ4tC+1sSLcASgaFL1hw l2usIzNHvKZ0mMSBjC0gX1I9dR1m3vv/PGxPZzrFm3m9+W4AUdLTp1yPPgZ2YdgWbnLc /dN3E01h8+i9u6FOLBezArN1MDHTKqGYg+0VJGrKF4993jwqR68e8QKhfcFTaiLxY/BT tVqw== X-Gm-Message-State: AAQBX9f65xkT+v+V1QvfxWq+sgp8lOQ7oTrpmlFs53Qa+2OC73CetsXq M+DGAZ8hmClInOqp/yZIrGXD1hCwtjYnwDe/fMM= X-Google-Smtp-Source: AKy350Zr65D5G7Y2SXbNR//LfCiPeKcYs21bo5zZhAXH6JQLmNB2HwLRUfAeUMYH/5tXslpZRuo8zQ== X-Received: by 2002:a05:600c:28f:b0:3ea:bc08:b63e with SMTP id 15-20020a05600c028f00b003eabc08b63emr4378808wmk.2.1680689951840; Wed, 05 Apr 2023 03:19:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PATCH 08/14] accel: Move HAX hThread to accelerator context Date: Wed, 5 Apr 2023 12:18:05 +0200 Message-Id: <20230405101811.76663-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689981444100017 hThread variable is only used by the HAX accelerator, so move it to the accelerator specific context. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 1 - target/i386/hax/hax-i386.h | 3 +++ target/i386/hax/hax-accel-ops.c | 2 +- target/i386/hax/hax-all.c | 2 +- target/i386/hax/hax-windows.c | 2 +- 5 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 173f47d24e..8d27861ed5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -334,7 +334,6 @@ struct CPUState { =20 struct QemuThread *thread; #ifdef _WIN32 - HANDLE hThread; QemuSemaphore sem; #endif int thread_id; diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h index d11d43e857..15d16772db 100644 --- a/target/i386/hax/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -27,6 +27,9 @@ typedef HANDLE hax_fd; extern struct hax_state hax_global; =20 typedef struct AccelvCPUState { +#ifdef _WIN32 + HANDLE hThread; +#endif hax_fd fd; int vcpu_id; struct hax_tunnel *tunnel; diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-op= s.c index a8512efcd5..5031096760 100644 --- a/target/i386/hax/hax-accel-ops.c +++ b/target/i386/hax/hax-accel-ops.c @@ -73,7 +73,7 @@ static void hax_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); assert(cpu->accel); #ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); + cpu->accel->hThread =3D qemu_thread_get_handle(cpu->thread); #endif } =20 diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index a55b18f353..c9ccc411e9 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -206,7 +206,7 @@ int hax_vcpu_destroy(CPUState *cpu) hax_close_fd(vcpu->fd); hax_global.vm->vcpus[vcpu->vcpu_id] =3D NULL; #ifdef _WIN32 - CloseHandle(cpu->hThread); + CloseHandle(vcpu->hThread); #endif g_free(vcpu); cpu->accel =3D NULL; diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 08ec93a256..b907953321 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -476,7 +476,7 @@ void hax_kick_vcpu_thread(CPUState *cpu) */ cpu->exit_request =3D 1; if (!qemu_cpu_is_self(cpu)) { - if (!QueueUserAPC(dummy_apc_func, cpu->hThread, 0)) { + if (!QueueUserAPC(dummy_apc_func, cpu->accel->hThread, 0)) { fprintf(stderr, "%s: QueueUserAPC failed with error %lu\n", __func__, GetLastError()); exit(1); --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680689975; cv=none; d=zohomail.com; s=zohoarc; b=MZOvBd70xUc5hzCwunkx3G2n5ARiOkxBspmD20QWJhPk6l8fyCVzZEJ7EAhzmj37wdCGmbIT3159mK3qokJ9f9QUDXlHaLoktAzVpjBodyw2JWzBhv3E233xi2iefQ8khSFlawEuTfqNU+zJpBd9Mv3Edw+oJHxtN0j9ZDVTJb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680689975; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EBsjiWXEyjNdcnK7CdgNfH2aIDA7wl6BmVcuMNTGlRg=; b=Y6av1riNB1icDEEma1UIC9CzcNbFz+WiJmfgnezgajMEKDa741iIhfxARhd8fwIwnivu2VhhDOhLydLleJWKyp/Kjp/oah+lvXCV0oRSChETofIEb2yNQKSm7b4P7vsOSkBHbx/vY1dJLcFRWyKa+Zu4Olrhn2ZwVwR8BdBwYVs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680689975406555.9059050046036; Wed, 5 Apr 2023 03:19:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pk0Ee-0008Vq-T0; Wed, 05 Apr 2023 06:19:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pk0Ed-0008UN-Al for qemu-devel@nongnu.org; Wed, 05 Apr 2023 06:19:23 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pk0Ea-0003Nk-Jm for qemu-devel@nongnu.org; Wed, 05 Apr 2023 06:19:23 -0400 Received: by mail-wr1-x42f.google.com with SMTP id v1so35645599wrv.1 for ; Wed, 05 Apr 2023 03:19:20 -0700 (PDT) Received: from localhost.localdomain (4ab54-h01-176-184-52-81.dsl.sta.abo.bbox.fr. [176.184.52.81]) by smtp.gmail.com with ESMTPSA id s11-20020a5d424b000000b002e5f6f8fc4fsm14040108wrr.100.2023.04.05.03.19.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EBsjiWXEyjNdcnK7CdgNfH2aIDA7wl6BmVcuMNTGlRg=; b=ZCeEmGx5C1tuByO7Gk8190umAFm3Jq4q/3LEy8V4HB/sgDGk01PdV0MXcQqltklyu3 DW09L0fwCMzuVJZy82A0vSyQNKZSvZwE3Rakfj2hr1zvFY1eZeaEbcBCDOHIx7fy11jt /S2FM9gq9oJe4BBqhtdS5l+3uhXXNdnl7KuLkaG9eftfsUPFv3TGzexWOVF1sWTguVrY 838K9xTGvVrgnK3wGNr49BTbICPTkdgaMh9RIPXj5OJjY/e393NR9LtEmB+cM2VmI3zz RQrk9WLPd1wzBdC0E7STdPo8yjxVpnfYhSiLQXfXjBKsSb4Cc8fPtp7Mrl4DfK8dO1FF g35Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EBsjiWXEyjNdcnK7CdgNfH2aIDA7wl6BmVcuMNTGlRg=; b=tv03KwsR2lYzKQjOoG603JMDQgIqHc3IdU116vPI7hbPUCq0ir1yVptL8IK7dFMgn6 MpHl38QoBe4u76bqw6sDx+5blN05vHW5nkI2rZD5NdKepq2KNf8WzPkl+mzpmE2n31gw y9xyAh9LuYGubY3Cuh+3lbRwJgOb6D7wSAGnzFWlzLoaPTk6OGiApJgvlZaoG4o5tnNg ecUhX9o1GSkCBZ6aZH6Oxw1ToLPUulwEi+yQdvBe/P8DQ/wy2bNpYGDmcvnqS41oP1gs SWDIhDqdSmNTT9tC3xh4ipluJR2DW+5irju3KvZyfIFf1RsLFumGt0j9q8y6o8Q1Km+z 8xmg== X-Gm-Message-State: AAQBX9f148neTtBtgvB2QvXejGAiX6ToY4phPkx0g/yKRap1Ol1DCZga s3xb5REmAnl7iIExl+9D7vgwkSkZlj00ze98siw= X-Google-Smtp-Source: AKy350bqyCS4jO7cj3IxU6M9gEfWmwwxn91ShCFu07OvQwRL7AbHTBtXunKmonFyvH6AyOInd3xSpQ== X-Received: by 2002:adf:f004:0:b0:2cf:f01f:ed89 with SMTP id j4-20020adff004000000b002cff01fed89mr4200753wro.24.1680689958696; Wed, 05 Apr 2023 03:19:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Reinoud Zandijk Subject: [PATCH 09/14] accel: Allocate NVMM vCPU using g_try_FOO() Date: Wed, 5 Apr 2023 12:18:06 +0200 Message-Id: <20230405101811.76663-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689975913100003 g_malloc0() can not fail. Use g_try_malloc0() instead. https://developer-old.gnome.org/glib/stable/glib-Memory-Allocation.html#gli= b-Memory-Allocation.description Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/nvmm/nvmm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 3c7bdd560f..45fd318d23 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -942,7 +942,7 @@ nvmm_init_vcpu(CPUState *cpu) } } =20 - qcpu =3D g_malloc0(sizeof(*qcpu)); + qcpu =3D g_try_malloc0(sizeof(*qcpu)); if (qcpu =3D=3D NULL) { error_report("NVMM: Failed to allocate VCPU context."); return -ENOMEM; --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680689999; cv=none; d=zohomail.com; s=zohoarc; b=S0j07OCXpU4kaC+BuAlY3CMSfFOgj5mtHKu9m85ND3FaSLDoJz3AyYr9/Npvjf+42TsdqBMYadKUw5z+FRJyFd7WiW9Tjl0yhOSCAvHUWnTEqqsBWM2JrdQtUetpknnCVNP8VMj+b47cANmRadjshY5mzhx4oenQXYnENK41pRo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680689999; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zfz8X/GUHgutjcuWgCA2LWUZkCc4gRaFUTsRO6OH06g=; b=Q2dS4jucp+rouJQFaXiRlguMlDkaToxUpElRp6J31ftujHSVdl9AFR0yAhZIAs648u3nekOARHHjl/ICrs06yDd8qNa/vTygH5KYlxhzz0bQJG24Cpb5SoHg4u9U2bZy1miA4YN8MGx8SOqXkQK01hNk00Zans8dw3cqA4ZsDPE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680689999086528.0329280375822; Wed, 5 Apr 2023 03:19:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pk0Em-00013L-Mn; Wed, 05 Apr 2023 06:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pk0Ek-0000ta-Ve for qemu-devel@nongnu.org; Wed, 05 Apr 2023 06:19:31 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pk0Ei-0003SY-Ot for qemu-devel@nongnu.org; Wed, 05 Apr 2023 06:19:30 -0400 Received: by mail-wr1-x42f.google.com with SMTP id r11so35629429wrr.12 for ; Wed, 05 Apr 2023 03:19:28 -0700 (PDT) Received: from localhost.localdomain (4ab54-h01-176-184-52-81.dsl.sta.abo.bbox.fr. [176.184.52.81]) by smtp.gmail.com with ESMTPSA id q12-20020adff78c000000b002c5d3f0f737sm14591138wrp.30.2023.04.05.03.19.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zfz8X/GUHgutjcuWgCA2LWUZkCc4gRaFUTsRO6OH06g=; b=yL8zWIHfSIdBZYPkNDculPyk2YWRIlBQX8fQHgjeuSYeTxaloVwCCglH5DXA7/0zDg TZoThoM/7Yzk229VxX9xWe1sKCb9xPkVbKN8Rue8VJ9iqfCxkzpWDThAQYbFg2V+tT4n 0lFcGByrmLtNLB2oRBl4LbPvsUeFbnwE43+pzddA4+wnnvx5l0rEaM3ytpPw2h5NOvmZ DVCYR6+eBbGkSb54pQlKLGqI1fhY/v3/lWGMSe4bZ8LvxqbH70eUp/6qo6vPZ7mUdh5Y PeQA12GP5hcgxOvodwGCZ4f1KCUcAPsr/zlEr6sTgBGcMgExpeywl1vstjMaVXIEP1HP 4juw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zfz8X/GUHgutjcuWgCA2LWUZkCc4gRaFUTsRO6OH06g=; b=n1VyGn6qxx/KuGIFOHZZQk7L2rKX0RliU1JmPWTmSmZjVHfkxb1j5CwJsC8sgBZ1W4 cyIoaSohH7aTrQpr3rqRzCKBkrSksrhfh7q3zgTtmIy5sdMBApHUVux3Qxzh7oNdlQ7j t181bbH89ZK8sB9LCIl77DHwO8aNzmUFbhA6lgitDRybpTEI5fqeHJzSGR0/VlN1IXwW TyMY+bGnt5uT4P5gLjQnhD5Xce7rby41jLFHaaK101dz2Og9kK/x9uKraoKlRQ4yZ6hY IlX8VTacmdbUwdtg8F1lJnbX/uGg82d3l2t9MyDNEp97qaf7shdyIRgxSg/iIOk1xRWD w1Ng== X-Gm-Message-State: AAQBX9dqyEu2oO7EPPxkujaqE0F4aXPdvjlF2l1pR1Cd3Oh3wRxQ1jAh CVL3RICw4Vxu5aSGeutm2adJrNecTTwX4hCV9fI= X-Google-Smtp-Source: AKy350Zvml7eWtPRqrRcRnGg6qq51tcU3Hzdj52W85LNQPphjff69u1l2lWyWIRrXMamHJtWfSOkkw== X-Received: by 2002:adf:e48b:0:b0:2c7:6bb:fb7a with SMTP id i11-20020adfe48b000000b002c706bbfb7amr4270631wrm.54.1680689967157; Wed, 05 Apr 2023 03:19:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Reinoud Zandijk Subject: [PATCH 10/14] accel: Rename NVMM struct qemu_vcpu -> struct AccelvCPUState Date: Wed, 5 Apr 2023 12:18:07 +0200 Message-Id: <20230405101811.76663-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680689999508100002 We want all accelerators to share the same opaque pointer in CPUState. Rename NVMM 'qemu_vcpu' as 'AccelvCPUState'. Replace g_try_malloc0() by g_try_new0() for readability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/nvmm/nvmm-all.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 45fd318d23..97a7225598 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -26,7 +26,7 @@ =20 #include =20 -struct qemu_vcpu { +struct AccelvCPUState { struct nvmm_vcpu vcpu; uint8_t tpr; bool stop; @@ -49,10 +49,10 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static struct qemu_vcpu * +static struct AccelvCPUState * get_qemu_vcpu(CPUState *cpu) { - return (struct qemu_vcpu *)cpu->accel; + return cpu->accel; } =20 static struct nvmm_machine * @@ -86,7 +86,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +223,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +347,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +372,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +395,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +478,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +565,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +610,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +686,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +892,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(current_cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(current_cpu); #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -926,7 +926,7 @@ nvmm_init_vcpu(CPUState *cpu) struct nvmm_vcpu_conf_cpuid cpuid; struct nvmm_vcpu_conf_tpr tpr; Error *local_error =3D NULL; - struct qemu_vcpu *qcpu; + struct AccelvCPUState *qcpu; int ret, err; =20 nvmm_init_cpu_signals(); @@ -942,7 +942,7 @@ nvmm_init_vcpu(CPUState *cpu) } } =20 - qcpu =3D g_try_malloc0(sizeof(*qcpu)); + qcpu =3D g_try_new0(struct AccelvCPUState, 1); if (qcpu =3D=3D NULL) { error_report("NVMM: Failed to allocate VCPU context."); return -ENOMEM; @@ -995,7 +995,7 @@ nvmm_init_vcpu(CPUState *cpu) } =20 cpu->vcpu_dirty =3D true; - cpu->accel =3D (struct AccelvCPUState *)qcpu; + cpu->accel =3D qcpu; =20 return 0; } @@ -1027,7 +1027,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); g_free(cpu->accel); --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id d21-20020a1c7315000000b003ed1f6878a5sm1770353wmb.5.2023.04.05.03.19.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=reJpuebcoI5BKEfS88SjCkcplXXPmguVbMU9Olmibx0=; b=Q2+dqv8HKpPQKTf9cQJSeqsGPGkeqsXxu8v+C2JYWo/wkdpZHobUDc9N35z1UbQyXo 9C6lndVpWvjoGdquQUathNsJoiIiN7nJn3kgNVvT5T7tc01blota5eXmXHc1hE2a/9ew 2Wf7CCzhPcSAgNhjaTij8S5PpdLVkajwG2fdrCTckKDaeIUqcPO5ZI4SEhoPCSlpK/xc jQRVVytzUEGa2Ydc7bSMmlI+Bj89/EomAs72KzqL8mlaSY0qlyPq25y3stucFF3G2pSS /sRRUshA2hioO50En8HSMUOtDGPuoJV66S46OhB8lo7qSEotmJH2F75Zpnda8gdb6yr0 tHhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=reJpuebcoI5BKEfS88SjCkcplXXPmguVbMU9Olmibx0=; b=36IFppfqZwqfE9nRy4ogZDHz0j+7CAcPI6eoFYg/090jB3s+vLvxdRvNkYtHw6DA02 oUwlNxcBynzI95jSCTdnBJ/aHOzppPIQVR8nNHE7rOQk4T8zfBcOCvrg/lMm5ymy+2NA PYnuRf6OJcVuMTYHk3IEGR3kAMHO74So3DCl12SgfdWV1f21CkhWahp5jjhtjax8b81u nNp4YoRrHdkigIOJmF+TcZY7MqlqY5jVGuHGbbZS8i0fkMXyD8KoJymyDunHyai04rDp CcbBTT2s39BCAdUd1IqH8umzT9xIL5I1+CeuODsk6S9/L6b3QU68ik90XXWN411Tacrh xBIA== X-Gm-Message-State: AAQBX9cl2+I+Jf9z2hSdU2dMsBTSexDlTvXICrVc09drPdysPmIcr4T1 P0mOgkSfekqCkh5fLOFDpAPDHoMu5Oa7r0HVGY4= X-Google-Smtp-Source: AKy350ZAz7PsFWbSoWRxQBkCoHp/n/DjoRXVF/1COGNHcX9m4lAa529X6M54U1ZwDgyYhrM/EeN7Fw== X-Received: by 2002:a1c:7717:0:b0:3f0:48f4:8454 with SMTP id t23-20020a1c7717000000b003f048f48454mr4350332wmi.27.1680689974915; Wed, 05 Apr 2023 03:19:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Reinoud Zandijk Subject: [PATCH 11/14] accel: Inline NVMM get_qemu_vcpu() Date: Wed, 5 Apr 2023 12:18:08 +0200 Message-Id: <20230405101811.76663-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680690161960100003 No need for this helper to access the CPUState::accel field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/nvmm/nvmm-all.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 97a7225598..1c0168d83c 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -49,12 +49,6 @@ struct qemu_machine { static bool nvmm_allowed; static struct qemu_machine qemu_mach; =20 -static struct AccelvCPUState * -get_qemu_vcpu(CPUState *cpu) -{ - return cpu->accel; -} - static struct nvmm_machine * get_nvmm_mach(void) { @@ -86,7 +80,7 @@ nvmm_set_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_x64_state *state =3D vcpu->state; uint64_t bitmap; @@ -223,7 +217,7 @@ nvmm_get_registers(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -347,7 +341,7 @@ static bool nvmm_can_take_int(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); =20 @@ -372,7 +366,7 @@ nvmm_can_take_int(CPUState *cpu) static bool nvmm_can_take_nmi(CPUState *cpu) { - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; =20 /* * Contrary to INTs, NMIs always schedule an exit when they are @@ -395,7 +389,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -478,7 +472,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; @@ -565,7 +559,7 @@ static int nvmm_handle_rdmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -610,7 +604,7 @@ static int nvmm_handle_wrmsr(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_x64_state *state =3D vcpu->state; @@ -686,7 +680,7 @@ nvmm_vcpu_loop(CPUState *cpu) { CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); struct nvmm_vcpu_exit *exit =3D vcpu->exit; @@ -892,7 +886,7 @@ static void nvmm_ipi_signal(int sigcpu) { if (current_cpu) { - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(current_cpu); + struct AccelvCPUState *qcpu =3D current_cpu->accel; #if NVMM_USER_VERSION >=3D 2 struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; nvmm_vcpu_stop(vcpu); @@ -1027,7 +1021,7 @@ void nvmm_destroy_vcpu(CPUState *cpu) { struct nvmm_machine *mach =3D get_nvmm_mach(); - struct AccelvCPUState *qcpu =3D get_qemu_vcpu(cpu); + struct AccelvCPUState *qcpu =3D cpu->accel; =20 nvmm_vcpu_destroy(mach, &qcpu->vcpu); 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id n7-20020a05600c4f8700b003ee9c8cc631sm1780821wmq.23.2023.04.05.03.19.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S/MtLkEvv/mpFG8xdDJ5UGIDl6QuLPsc27INO07zRJs=; b=j3hNNVtnFSkeMmMMmVP7MwKIlYYAEqbhDpfKTMInG3a+9K0+YXceoJPZJ4jZAHCBFI VPa6eMgi/+9TXCgyr86xjuKK9t4zNhPlw7CAX0fvenTdKFSa3t+eBYp0hgH6m98d3/lR jnJJMwWe2cN5PCDDRMn3ZiOfvLvOx0KgfKGPNgpITrxaoDPAOFx1uqGJJWFNIk4jpdv7 NGGSO2xZQkFpOwy7mhzr21QREPPwjCH42qXvKwpRx5Hf1PwrV8q3x4WiQL9Zq/cJZpvA +TtnCQgltM297hRRmytaXGZhpTBrxwBYRmMmPEjntzUo7iHBOLTSWiIxfEFT8knJMWNo rgog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S/MtLkEvv/mpFG8xdDJ5UGIDl6QuLPsc27INO07zRJs=; b=Vk5iw77DRxAE6WXTVZfB5ameW24d6Ckz6xzWmoxJB5+R5nJHN5jVaVIYHLinXb0ErG ohfOIa945/NGsdqwHvZ940+pcucdmL4OdEExMY6MAIHoQkE8FFXLjGgd7GSrtDdkr50J CkoJKjr3gCdKjwVjkZEA8F2HMi3SFS9sSJK0atS+EnZFMAXCQC/eh+Ks5EdwPtNSbz9X g9b0aCpIXqmeemf8ffPsl3iiqAwsM8IQZWXobEM8UaZWP3SgET/Y/1f+3mMt3cngzSrc gUJHCXwwmEr4yaLnmU9H9hG5q4615cDyjACD0hmQUh7h844VeCdLg+J7yuYQ8ohQOaey Aieg== X-Gm-Message-State: AAQBX9cstxnrTWex5KIvBECebQF3I9oSQL1vFOg5r4/E28GjE0xeo7O8 o7u+DBrwcFTFZubNOI2EPtmFO3Q7Ph94InnEBhI= X-Google-Smtp-Source: AKy350ZceuduIKjGNIdlkcOLlYLJL5KbbisXjbggRXGoX4b3J2s4uJbs/AyE+v9R+USsxTJSDNjt2g== X-Received: by 2002:a1c:f707:0:b0:3ee:9909:acc8 with SMTP id v7-20020a1cf707000000b003ee9909acc8mr4174177wmh.32.1680689981231; Wed, 05 Apr 2023 03:19:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sunil Muthuswamy Subject: [PATCH 12/14] accel: Rename WHPX struct whpx_vcpu -> struct AccelvCPUState Date: Wed, 5 Apr 2023 12:18:09 +0200 Message-Id: <20230405101811.76663-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680690008028100003 We want all accelerators to share the same opaque pointer in CPUState. Rename WHPX 'whpx_vcpu' as 'AccelvCPUState'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/whpx/whpx-all.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 70eadb7f05..2372c4227a 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -229,7 +229,7 @@ typedef enum WhpxStepMode { WHPX_STEP_EXCLUSIVE, } WhpxStepMode; =20 -struct whpx_vcpu { +struct AccelvCPUState { WHV_EMULATOR_HANDLE emulator; bool window_registered; bool interruptable; @@ -260,9 +260,9 @@ static bool whpx_has_xsave(void) * VP support */ =20 -static struct whpx_vcpu *get_whpx_vcpu(CPUState *cpu) +static struct AccelvCPUState *get_whpx_vcpu(CPUState *cpu) { - return (struct whpx_vcpu *)cpu->accel; + return (struct AccelvCPUState *)cpu->accel; } =20 static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, @@ -390,7 +390,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -609,7 +609,7 @@ static void whpx_get_xcrs(CPUState *cpu) static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -892,7 +892,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = =3D { static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryMmioEmulation( @@ -917,7 +917,7 @@ static int whpx_handle_portio(CPUState *cpu, WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryIoEmulation( @@ -1417,7 +1417,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) * of QEMU, nor this port by calling WHvSetVirtualProcessorRegiste= rs(). * This is the most common case. */ - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); return vcpu->exit_ctx.VpContext.Rip; } else { /* @@ -1468,7 +1468,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; @@ -1590,7 +1590,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 static void whpx_vcpu_post_run(CPUState *cpu) { - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 @@ -1617,7 +1617,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) { CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { @@ -1656,7 +1656,7 @@ static int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); struct whpx_breakpoint *stepped_over_bp =3D NULL; WhpxStepMode exclusive_step_mode =3D WHPX_STEP_NONE; int ret; @@ -2154,7 +2154,7 @@ int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D NULL; + struct AccelvCPUState *vcpu =3D NULL; Error *local_error =3D NULL; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -2177,7 +2177,7 @@ int whpx_init_vcpu(CPUState *cpu) } } =20 - vcpu =3D g_new0(struct whpx_vcpu, 1); + vcpu =3D g_new0(struct AccelvCPUState, 1); =20 if (!vcpu) { error_report("WHPX: Failed to allocte VCPU context."); @@ -2296,7 +2296,7 @@ int whpx_vcpu_exec(CPUState *cpu) void whpx_destroy_vcpu(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id o7-20020adfe807000000b002e4cd2ec5c7sm14692347wrm.86.2023.04.05.03.19.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jksVpkvUC0Cd0t39UFdIwyYip+p/HLpViupo0kEzavo=; b=M14p41XBeC2pDOXONWRmVPh/g0bgtOaeo2kq2u+TWuJbxjfFyLRtQYnT6xjEliAwSd Gmn7vgNMSmnVxfuYpWs2aBjugNVuv4EcJIwJLGMmyZg0QDYfH3i/sc7Kh/q/3WK7qsdn F60Wv7glyCGVMo3BOtpHfdZkvOyzxwN+gH3+Hex9JK/WUrdLUi4yf74vk34hUq78UiYb AORBP6ycIQAo33OBYSJhlzh69AqqlN5KQ4LDwsQpdYmaxHN8h7YoC/jYUnRSJ6PAS/Fc moP7c9mQFfmYCYIySXHMkSb6ncs0eKD1DYTa0llVPqgHxXnFQBGyNcDmOUOFGwExmveQ mqGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jksVpkvUC0Cd0t39UFdIwyYip+p/HLpViupo0kEzavo=; b=RhpZZO9pyQJ9KE8mfBhMVlRbieGncSxNpACQETPRovtBuLCs3I3yTnpeGd6utlJzDJ tiEm1hy06ZRF9JIHhX/w6/EulW2CxVOce1ZSS0PO0+BB4kZ/RWnRMZi6RGhqimRTPYFn 4xpAIemBDq6plL/tKulmV27FiY4QF+vAtyCpnIOMCMeoDwJIbTHVM5y7PZKH57zQeP9G z5BDsm6v31JWfbO8WYtvrAmW3o3M0IhBGPokdt5BkiB10VCNcFSFpN981qGw1XxVGW+8 PRM8BNb/IfV38sBG1eRipILByrAJRr/T6NOK8MYoLTlDruVY+k5sbI6posO5FY7ruOTR ma5Q== X-Gm-Message-State: AAQBX9crHnjfUWtj3kSuu528N5JYOHo8/exvqyBUJ40cQpWrITMxT2jQ qHAruhgx+UJOgMocuu33CfkcgKCAjeg/htMaZ0M= X-Google-Smtp-Source: AKy350ab1egrbimBmhajh9GEqufBtAURJQuxG6H/Hs7JpaNOdz6mu7HJAmIyOPKcGGllVT4MOOnVWA== X-Received: by 2002:adf:df85:0:b0:2ce:a85f:1313 with SMTP id z5-20020adfdf85000000b002cea85f1313mr3358628wrl.35.1680689989199; Wed, 05 Apr 2023 03:19:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , xen-devel@lists.xenproject.org, kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sunil Muthuswamy Subject: [PATCH 13/14] accel: Inline WHPX get_whpx_vcpu() Date: Wed, 5 Apr 2023 12:18:10 +0200 Message-Id: <20230405101811.76663-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405101811.76663-1-philmd@linaro.org> References: <20230405101811.76663-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680690074438100001 No need for this helper to access the CPUState::accel field. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/whpx/whpx-all.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 2372c4227a..2cca6bc004 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -256,15 +256,6 @@ static bool whpx_has_xsave(void) return whpx_xsave_cap.XsaveSupport; } =20 -/* - * VP support - */ - -static struct AccelvCPUState *get_whpx_vcpu(CPUState *cpu) -{ - return (struct AccelvCPUState *)cpu->accel; -} - static WHV_X64_SEGMENT_REGISTER whpx_seg_q2h(const SegmentCache *qs, int v= 86, int r86) { @@ -390,7 +381,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -609,7 +600,7 @@ static void whpx_get_xcrs(CPUState *cpu) static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; @@ -892,7 +883,7 @@ static const WHV_EMULATOR_CALLBACKS whpx_emu_callbacks = =3D { static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryMmioEmulation( @@ -917,7 +908,7 @@ static int whpx_handle_portio(CPUState *cpu, WHV_X64_IO_PORT_ACCESS_CONTEXT *ctx) { HRESULT hr; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; WHV_EMULATOR_STATUS emu_status; =20 hr =3D whp_dispatch.WHvEmulatorTryIoEmulation( @@ -1417,7 +1408,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) * of QEMU, nor this port by calling WHvSetVirtualProcessorRegiste= rs(). * This is the most common case. */ - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; return vcpu->exit_ctx.VpContext.Rip; } else { /* @@ -1468,7 +1459,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; @@ -1590,7 +1581,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 static void whpx_vcpu_post_run(CPUState *cpu) { - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 @@ -1617,7 +1608,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) { CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { @@ -1656,7 +1647,7 @@ static int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; struct whpx_breakpoint *stepped_over_bp =3D NULL; WhpxStepMode exclusive_step_mode =3D WHPX_STEP_NONE; int ret; @@ -2296,7 +2287,7 @@ int whpx_vcpu_exec(CPUState *cpu) void whpx_destroy_vcpu(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; - struct AccelvCPUState *vcpu =3D get_whpx_vcpu(cpu); + struct AccelvCPUState *vcpu =3D cpu->accel; =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); --=20 2.38.1 From nobody Thu May 16 10:29:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Rename the 'hvf_vcpu_state' structure as 'AccelvCPUState'. Use the generic 'accel' field of CPUState instead of 'hvf'. Replace g_malloc0() by g_new0() for readability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 3 -- include/sysemu/hvf_int.h | 2 +- accel/hvf/hvf-accel-ops.c | 16 ++++----- target/arm/hvf/hvf.c | 70 +++++++++++++++++++-------------------- 4 files changed, 44 insertions(+), 47 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8d27861ed5..1dc5efe650 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -236,7 +236,6 @@ typedef struct SavedIOTLB { struct KVMState; struct kvm_run; struct AccelvCPUState; -struct hvf_vcpu_state; =20 /* work queue */ =20 @@ -442,8 +441,6 @@ struct CPUState { /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ bool prctl_unalign_sigbus; =20 - struct hvf_vcpu_state *hvf; - /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; }; diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 6545f7cd61..96ef51f4df 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -48,7 +48,7 @@ struct HVFState { }; extern HVFState *hvf_state; =20 -struct hvf_vcpu_state { +struct AccelvCPUState { uint64_t fd; void *exit; bool vtimer_masked; diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 24913ca9c4..06ca1d59a4 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -363,19 +363,19 @@ type_init(hvf_type_init); =20 static void hvf_vcpu_destroy(CPUState *cpu) { - hv_return_t ret =3D hv_vcpu_destroy(cpu->hvf->fd); + hv_return_t ret =3D hv_vcpu_destroy(cpu->accel->fd); assert_hvf_ok(ret); =20 hvf_arch_vcpu_destroy(cpu); - g_free(cpu->hvf); - cpu->hvf =3D NULL; + g_free(cpu->accel); + cpu->accel =3D NULL; } =20 static int hvf_init_vcpu(CPUState *cpu) { int r; =20 - cpu->hvf =3D g_malloc0(sizeof(*cpu->hvf)); + cpu->accel =3D g_new0(struct AccelvCPUState, 1); =20 /* init cpu signals */ struct sigaction sigact; @@ -384,13 +384,13 @@ static int hvf_init_vcpu(CPUState *cpu) sigact.sa_handler =3D dummy_signal; sigaction(SIG_IPI, &sigact, NULL); =20 - pthread_sigmask(SIG_BLOCK, NULL, &cpu->hvf->unblock_ipi_mask); - sigdelset(&cpu->hvf->unblock_ipi_mask, SIG_IPI); + pthread_sigmask(SIG_BLOCK, NULL, &cpu->accel->unblock_ipi_mask); + sigdelset(&cpu->accel->unblock_ipi_mask, SIG_IPI); =20 #ifdef __aarch64__ - r =3D hv_vcpu_create(&cpu->hvf->fd, (hv_vcpu_exit_t **)&cpu->hvf->exit= , NULL); + r =3D hv_vcpu_create(&cpu->accel->fd, (hv_vcpu_exit_t **)&cpu->accel->= exit, NULL); #else - r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT); + r =3D hv_vcpu_create((hv_vcpuid_t *)&cpu->accel->fd, HV_VCPU_DEFAULT); #endif cpu->vcpu_dirty =3D 1; assert_hvf_ok(r); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index ad65603445..b85648b61c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -366,29 +366,29 @@ int hvf_get_registers(CPUState *cpu) int i; =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val= ); *(uint64_t *)((void *)env + hvf_reg_match[i].offset) =3D val; assert_hvf_ok(ret); } =20 for (i =3D 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { - ret =3D hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].r= eg, + ret =3D hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i]= .reg, &fpval); memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpv= al)); assert_hvf_ok(ret); } =20 val =3D 0; - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val); assert_hvf_ok(ret); vfp_set_fpcr(env, val); =20 val =3D 0; - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val); assert_hvf_ok(ret); vfp_set_fpsr(env, val); =20 - ret =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val); + ret =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val); assert_hvf_ok(ret); pstate_write(env, val); =20 @@ -397,7 +397,7 @@ int hvf_get_registers(CPUState *cpu) continue; } =20 - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &= val); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= &val); assert_hvf_ok(ret); =20 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; @@ -420,24 +420,24 @@ int hvf_put_registers(CPUState *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); assert_hvf_ok(ret); } =20 for (i =3D 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) { memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpv= al)); - ret =3D hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].r= eg, + ret =3D hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i]= .reg, fpval); assert_hvf_ok(ret); } =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env)= ); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env)= ); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env)); + ret =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env)); assert_hvf_ok(ret); =20 aarch64_save_sp(env, arm_current_el(env)); @@ -449,11 +449,11 @@ int hvf_put_registers(CPUState *cpu) } =20 val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, v= al); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg,= val); assert_hvf_ok(ret); } =20 - ret =3D hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offs= et); + ret =3D hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_of= fset); assert_hvf_ok(ret); =20 return 0; @@ -474,7 +474,7 @@ static void hvf_set_reg(CPUState *cpu, int rt, uint64_t= val) flush_cpu_state(cpu); =20 if (rt < 31) { - r =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val); + r =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val); assert_hvf_ok(r); } } @@ -487,7 +487,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) flush_cpu_state(cpu); =20 if (rt < 31) { - r =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val); + r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val); assert_hvf_ok(r); } =20 @@ -629,22 +629,22 @@ int hvf_arch_init_vcpu(CPUState *cpu) assert(write_cpustate_to_list(arm_cpu, false)); =20 /* Set CP_NO_RAW system registers on init */ - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1, + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1, arm_cpu->midr); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1, + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1, arm_cpu->mp_affinity); assert_hvf_ok(ret); =20 - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, = &pfr); + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , &pfr); assert_hvf_ok(ret); pfr |=3D env->gicv3state ? (1 << 24) : 0; - ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, = pfr); + ret =3D hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1= , pfr); assert_hvf_ok(ret); =20 /* We're limited to underlying hardware caps, override internal versio= ns */ - ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, + ret =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL= 1, &arm_cpu->isar.id_aa64mmfr0); assert_hvf_ok(ret); =20 @@ -654,7 +654,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_kick_vcpu_thread(CPUState *cpu) { cpus_kick_thread(cpu); - hv_vcpus_exit(&cpu->hvf->fd, 1); + hv_vcpus_exit(&cpu->accel->fd, 1); } =20 static void hvf_raise_exception(CPUState *cpu, uint32_t excp, @@ -1191,13 +1191,13 @@ static int hvf_inject_interrupts(CPUState *cpu) { if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { trace_hvf_inject_fiq(); - hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ, + hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FI= Q, true); } =20 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { trace_hvf_inject_irq(); - hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ, + hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IR= Q, true); } =20 @@ -1231,7 +1231,7 @@ static void hvf_wait_for_ipi(CPUState *cpu, struct ti= mespec *ts) */ qatomic_mb_set(&cpu->thread_kicked, false); qemu_mutex_unlock_iothread(); - pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask); + pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask); qemu_mutex_lock_iothread(); } =20 @@ -1252,7 +1252,7 @@ static void hvf_wfi(CPUState *cpu) return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ct= l); assert_hvf_ok(r); =20 if (!(ctl & 1) || (ctl & 2)) { @@ -1261,7 +1261,7 @@ static void hvf_wfi(CPUState *cpu) return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cva= l); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &c= val); assert_hvf_ok(r); =20 ticks_to_sleep =3D cval - hvf_vtimer_val(); @@ -1294,12 +1294,12 @@ static void hvf_sync_vtimer(CPUState *cpu) uint64_t ctl; bool irq_state; =20 - if (!cpu->hvf->vtimer_masked) { + if (!cpu->accel->vtimer_masked) { /* We will get notified on vtimer changes by hvf, nothing to do */ return; } =20 - r =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl); + r =3D hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ct= l); assert_hvf_ok(r); =20 irq_state =3D (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS= )) =3D=3D @@ -1308,8 +1308,8 @@ static void hvf_sync_vtimer(CPUState *cpu) =20 if (!irq_state) { /* Timer no longer asserting, we can unmask it */ - hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); - cpu->hvf->vtimer_masked =3D false; + hv_vcpu_set_vtimer_mask(cpu->accel->fd, false); + cpu->accel->vtimer_masked =3D false; } } =20 @@ -1317,7 +1317,7 @@ int hvf_vcpu_exec(CPUState *cpu) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; - hv_vcpu_exit_t *hvf_exit =3D cpu->hvf->exit; + hv_vcpu_exit_t *hvf_exit =3D cpu->accel->exit; hv_return_t r; bool advance_pc =3D false; =20 @@ -1332,7 +1332,7 @@ int hvf_vcpu_exec(CPUState *cpu) flush_cpu_state(cpu); =20 qemu_mutex_unlock_iothread(); - assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd)); + assert_hvf_ok(hv_vcpu_run(cpu->accel->fd)); =20 /* handle VMEXIT */ uint64_t exit_reason =3D hvf_exit->reason; @@ -1346,7 +1346,7 @@ int hvf_vcpu_exec(CPUState *cpu) break; case HV_EXIT_REASON_VTIMER_ACTIVATED: qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1); - cpu->hvf->vtimer_masked =3D true; + cpu->accel->vtimer_masked =3D true; return 0; case HV_EXIT_REASON_CANCELED: /* we got kicked, no exit to process */ @@ -1457,10 +1457,10 @@ int hvf_vcpu_exec(CPUState *cpu) =20 flush_cpu_state(cpu); =20 - r =3D hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc); + r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); assert_hvf_ok(r); pc +=3D 4; - r =3D hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc); + r =3D hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc); assert_hvf_ok(r); } =20 --=20 2.38.1