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As a result, any device registers in the same pages as the start or the end of the MSIX table is not currently accessible, as the accesses are just dropped. Note the spec forbids such placing of registers, as the MSIX and PBA tables must be 4K isolated from any other registers: "If a Base Address register that maps address space for the MSI-X Table or MSI-X PBA also maps other usable address space that is not associated with MSI-X structures, locations (e.g., for CSRs) used in the other address space must not share any naturally aligned 4-KB address range with one where either MSI-X structure resides." Yet the 'Intel Wi-Fi 6 AX201' device on one of my boxes has registers in the same page as the MSIX table, and thus won't work on a PVH dom0 without this fix. In order to cope with the behavior passthrough any accesses that fall on the same page as the MSIX table (but don't fall between) it to the underlying hardware. Such forwarding also takes care of the PBA accesses in case the PBA is sharing a page with the MSIX table, so it allows to remove the code doing this handling in msix_{read,write}. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/drivers/vpci/msix.c | 259 +++++++++++++++++++++++++--------------- xen/drivers/vpci/vpci.c | 7 +- xen/include/xen/vpci.h | 6 +- 3 files changed, 175 insertions(+), 97 deletions(-) diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index bea0cc7aed..1b59c7fc14 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -27,6 +27,13 @@ ((addr) >=3D vmsix_table_addr(vpci, nr) && = \ (addr) < vmsix_table_addr(vpci, nr) + vmsix_table_size(vpci, nr)) =20 +#define VMSIX_ADDR_ADJACENT(addr, vpci, nr) \ + ((PFN_DOWN(addr) =3D=3D PFN_DOWN(vmsix_table_addr(vpci, nr)) && = \ + (addr) < vmsix_table_addr(vpci, nr)) || \ + (PFN_DOWN(addr) =3D=3D PFN_DOWN(vmsix_table_addr(vpci, nr) + = \ + vmsix_table_size(vpci, nr) - 1) && \ + (addr) >=3D vmsix_table_addr(vpci, nr) + vmsix_table_size(vpci, nr))) + static uint32_t cf_check control_read( const struct pci_dev *pdev, unsigned int reg, void *data) { @@ -145,11 +152,9 @@ static struct vpci_msix *msix_find(const struct domain= *d, unsigned long addr) list_for_each_entry ( msix, &d->arch.hvm.msix_tables, next ) { const struct vpci_bar *bars =3D msix->pdev->vpci->header.bars; - unsigned int i; =20 - for ( i =3D 0; i < ARRAY_SIZE(msix->tables); i++ ) - if ( bars[msix->tables[i] & PCI_MSIX_BIRMASK].enabled && - VMSIX_ADDR_IN_RANGE(addr, msix->pdev->vpci, i) ) + if ( bars[msix->tables[VPCI_MSIX_TABLE] & PCI_MSIX_BIRMASK].enable= d && + VMSIX_ADDR_IN_RANGE(addr, msix->pdev->vpci, VPCI_MSIX_TABLE) ) return msix; } =20 @@ -182,36 +187,38 @@ static struct vpci_msix_entry *get_entry(struct vpci_= msix *msix, return &msix->entries[(addr - start) / PCI_MSIX_ENTRY_SIZE]; } =20 -static void __iomem *get_pba(struct vpci *vpci) +static void __iomem *get_table(struct vpci *vpci, unsigned int slot) { struct vpci_msix *msix =3D vpci->msix; /* - * PBA will only be unmapped when the device is deassigned, so access = it + * MSIX will only be unmapped when the device is deassigned, so access= it * without holding the vpci lock. */ - void __iomem *pba =3D read_atomic(&msix->pba); + void __iomem *table =3D read_atomic(&msix->table[slot]); =20 - if ( likely(pba) ) - return pba; + if ( likely(table) ) + return table; =20 - pba =3D ioremap(vmsix_table_addr(vpci, VPCI_MSIX_PBA), - vmsix_table_size(vpci, VPCI_MSIX_PBA)); - if ( !pba ) - return read_atomic(&msix->pba); + table =3D ioremap(round_pgdown(vmsix_table_addr(vpci, VPCI_MSIX_TABLE)= + + (slot =3D=3D VPCI_MSIX_TBL_HEAD ? + 0 : vmsix_table_size(vpci, VPCI_MSIX_TAB= LE))), + PAGE_SIZE); + if ( !table ) + return read_atomic(&msix->table[slot]); =20 spin_lock(&vpci->lock); - if ( !msix->pba ) + if ( !msix->table[slot] ) { - write_atomic(&msix->pba, pba); + write_atomic(&msix->table[slot], table); spin_unlock(&vpci->lock); } else { spin_unlock(&vpci->lock); - iounmap(pba); + iounmap(table); } =20 - return read_atomic(&msix->pba); + return read_atomic(&msix->table[slot]); } =20 static int cf_check msix_read( @@ -230,45 +237,6 @@ static int cf_check msix_read( if ( !access_allowed(msix->pdev, addr, len) ) return X86EMUL_OKAY; =20 - if ( VMSIX_ADDR_IN_RANGE(addr, msix->pdev->vpci, VPCI_MSIX_PBA) ) - { - struct vpci *vpci =3D msix->pdev->vpci; - unsigned int idx =3D addr - vmsix_table_addr(vpci, VPCI_MSIX_PBA); - const void __iomem *pba =3D get_pba(vpci); - - /* - * Access to PBA. - * - * TODO: note that this relies on having the PBA identity mapped t= o the - * guest address space. If this changes the address will need to be - * translated. - */ - if ( !pba ) - { - gprintk(XENLOG_WARNING, - "%pp: unable to map MSI-X PBA, report all pending\n", - &msix->pdev->sbdf); - return X86EMUL_OKAY; - } - - switch ( len ) - { - case 4: - *data =3D readl(pba + idx); - break; - - case 8: - *data =3D readq(pba + idx); - break; - - default: - ASSERT_UNREACHABLE(); - break; - } - - return X86EMUL_OKAY; - } - spin_lock(&msix->pdev->vpci->lock); entry =3D get_entry(msix, addr); offset =3D addr & (PCI_MSIX_ENTRY_SIZE - 1); @@ -317,43 +285,6 @@ static int cf_check msix_write( if ( !access_allowed(msix->pdev, addr, len) ) return X86EMUL_OKAY; =20 - if ( VMSIX_ADDR_IN_RANGE(addr, msix->pdev->vpci, VPCI_MSIX_PBA) ) - { - struct vpci *vpci =3D msix->pdev->vpci; - unsigned int idx =3D addr - vmsix_table_addr(vpci, VPCI_MSIX_PBA); - const void __iomem *pba =3D get_pba(vpci); - - if ( !is_hardware_domain(d) ) - /* Ignore writes to PBA for DomUs, it's behavior is undefined.= */ - return X86EMUL_OKAY; - - if ( !pba ) - { - /* Unable to map the PBA, ignore write. */ - gprintk(XENLOG_WARNING, - "%pp: unable to map MSI-X PBA, write ignored\n", - &msix->pdev->sbdf); - return X86EMUL_OKAY; - } - - switch ( len ) - { - case 4: - writel(data, pba + idx); - break; - - case 8: - writeq(data, pba + idx); - break; - - default: - ASSERT_UNREACHABLE(); - break; - } - - return X86EMUL_OKAY; - } - spin_lock(&msix->pdev->vpci->lock); entry =3D get_entry(msix, addr); offset =3D addr & (PCI_MSIX_ENTRY_SIZE - 1); @@ -438,6 +369,145 @@ static const struct hvm_mmio_ops vpci_msix_table_ops = =3D { .write =3D msix_write, }; =20 +const static struct vpci_msix *adjacent_find(const struct domain *d, + unsigned long addr) +{ + const struct vpci_msix *msix; + + list_for_each_entry ( msix, &d->arch.hvm.msix_tables, next ) + /* + * So far vPCI only traps accesses to the MSIX table, but not the = PBA + * explicitly, and hence we only need to check for the hole create= d by + * the MSIX table. + * + * If the PBA table is also trapped, the check here should be expa= nded + * to take it into account. + */ + if ( VMSIX_ADDR_ADJACENT(addr, msix->pdev->vpci, VPCI_MSIX_TABLE) ) + return msix; + + return NULL; +} + +static int cf_check adjacent_accept(struct vcpu *v, unsigned long addr) +{ + return !!adjacent_find(v->domain, addr); +} + +static int cf_check adjacent_read( + struct vcpu *v, unsigned long addr, unsigned int len, unsigned long *d= ata) +{ + const struct domain *d =3D v->domain; + const struct vpci_msix *msix =3D adjacent_find(d, addr); + const void __iomem *mem; + paddr_t msix_tbl; + struct vpci *vpci; + + *data =3D ~0ul; + + if ( !msix ) + return X86EMUL_RETRY; + + vpci =3D msix->pdev->vpci; + msix_tbl =3D vmsix_table_addr(vpci, VPCI_MSIX_TABLE); + + if ( addr + len > round_pgup(msix_tbl + + vmsix_table_size(vpci, VPCI_MSIX_TABLE)) ) + return X86EMUL_OKAY; + + mem =3D get_table(vpci, + PFN_DOWN(addr) =3D=3D PFN_DOWN(msix_tbl) ? VPCI_MSIX_T= BL_HEAD + : VPCI_MSIX_TBL_T= AIL); + if ( !mem ) + return X86EMUL_OKAY; + + switch ( len ) + { + case 1: + *data =3D readb(mem + PAGE_OFFSET(addr)); + break; + + case 2: + *data =3D readw(mem + PAGE_OFFSET(addr)); + break; + + case 4: + *data =3D readl(mem + PAGE_OFFSET(addr)); + break; + + case 8: + *data =3D readq(mem + PAGE_OFFSET(addr)); + break; + + default: + ASSERT_UNREACHABLE(); + } + + return X86EMUL_OKAY; +} + +static int cf_check adjacent_write( + struct vcpu *v, unsigned long addr, unsigned int len, unsigned long da= ta) +{ + const struct domain *d =3D v->domain; + const struct vpci_msix *msix =3D adjacent_find(d, addr); + void __iomem *mem; + paddr_t msix_tbl; + struct vpci *vpci; + + if ( !msix ) + return X86EMUL_RETRY; + + vpci =3D msix->pdev->vpci; + msix_tbl =3D vmsix_table_addr(vpci, VPCI_MSIX_TABLE); + + if ( addr + len > round_pgup(msix_tbl + + vmsix_table_size(vpci, VPCI_MSIX_TABLE)) ) + return X86EMUL_OKAY; + + if ( (VMSIX_ADDR_IN_RANGE(addr, vpci, VPCI_MSIX_PBA) || + VMSIX_ADDR_IN_RANGE(addr + len - 1, vpci, VPCI_MSIX_PBA)) && + !is_hardware_domain(d) ) + /* Ignore writes to PBA for DomUs, it's undefined behavior. */ + return X86EMUL_OKAY; + + mem =3D get_table(vpci, + PFN_DOWN(addr) =3D=3D PFN_DOWN(msix_tbl) ? VPCI_MSIX_T= BL_HEAD + : VPCI_MSIX_TBL_T= AIL); + if ( !mem ) + return X86EMUL_OKAY; + + switch ( len ) + { + case 1: + writeb(data, mem + PAGE_OFFSET(addr)); + break; + + case 2: + writew(data, mem + PAGE_OFFSET(addr)); + break; + + case 4: + writel(data, mem + PAGE_OFFSET(addr)); + break; + + case 8: + writeq(data, mem + PAGE_OFFSET(addr)); + break; + + default: + ASSERT_UNREACHABLE(); + } + + return X86EMUL_OKAY; +} + +static const struct hvm_mmio_ops vpci_msix_adj_ops =3D { + .check =3D adjacent_accept, + .read =3D adjacent_read, + .write =3D adjacent_write, +}; + int vpci_make_msix_hole(const struct pci_dev *pdev) { struct domain *d =3D pdev->domain; @@ -530,7 +600,10 @@ static int cf_check init_msix(struct pci_dev *pdev) } =20 if ( list_empty(&d->arch.hvm.msix_tables) ) + { register_mmio_handler(d, &vpci_msix_table_ops); + register_mmio_handler(d, &vpci_msix_adj_ops); + } =20 pdev->vpci->msix =3D msix; list_add(&msix->next, &d->arch.hvm.msix_tables); diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 6d48d496bb..652807a4a4 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -54,9 +54,12 @@ void vpci_remove_device(struct pci_dev *pdev) spin_unlock(&pdev->vpci->lock); if ( pdev->vpci->msix ) { + unsigned int i; + list_del(&pdev->vpci->msix->next); - if ( pdev->vpci->msix->pba ) - iounmap(pdev->vpci->msix->pba); + for ( i =3D 0; i < ARRAY_SIZE(pdev->vpci->msix->table); i++ ) + if ( pdev->vpci->msix->table[i] ) + iounmap(pdev->vpci->msix->table[i]); } xfree(pdev->vpci->msix); xfree(pdev->vpci->msi); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index d8acfeba8a..b1ea312778 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -133,8 +133,10 @@ struct vpci { bool enabled : 1; /* Masked? */ bool masked : 1; - /* PBA map */ - void __iomem *pba; + /* Partial table map. */ +#define VPCI_MSIX_TBL_HEAD 0 +#define VPCI_MSIX_TBL_TAIL 1 + void __iomem *table[2]; /* Entries. */ struct vpci_msix_entry { uint64_t addr; --=20 2.39.0