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d="scan'208";a="97090717" From: Sergey Dyasli To: CC: Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Sergey Dyasli Subject: [PATCH v5] x86/ucode/AMD: late load the patch on every logical thread Date: Thu, 23 Feb 2023 17:39:24 +0000 Message-ID: <20230223173924.11815-1-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1677174031284100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently late ucode loading is performed only on the first core of CPU siblings. But according to the latest recommendation from AMD, late ucode loading should happen on every logical thread/core on AMD CPUs. To achieve that, introduce is_cpu_primary() helper which will consider every logical cpu as "primary" when running on AMD CPUs. Also include Hygon in the check for future-proofing. Signed-off-by: Sergey Dyasli Reviewed-by: Jan Beulich --- v5: - refactored the code by adding is_cpu_primary() helper - include Hygon cpus into the check v4: - new patch --- xen/arch/x86/cpu/microcode/core.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index ba6e7b42c6..cfa2d5053a 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -276,6 +276,20 @@ static bool microcode_update_cache(struct microcode_pa= tch *patch) return true; } =20 +/* Returns true if ucode should be loaded on a given cpu */ +static bool is_cpu_primary(unsigned int cpu) +{ + if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + /* Load ucode on every logical thread/core */ + return true; + + /* Intel CPUs should load ucode only on the first core of SMT siblings= */ + if ( cpu =3D=3D cpumask_first(per_cpu(cpu_sibling_mask, cpu)) ) + return true; + + return false; +} + /* Wait for a condition to be met with a timeout (us). */ static int wait_for_condition(bool (*func)(unsigned int data), unsigned int data, unsigned int timeout) @@ -382,7 +396,7 @@ static int primary_thread_work(const struct microcode_p= atch *patch) static int cf_check microcode_nmi_callback( const struct cpu_user_regs *regs, int cpu) { - unsigned int primary =3D cpumask_first(this_cpu(cpu_sibling_mask)); + bool primary_cpu =3D is_cpu_primary(cpu); int ret; =20 /* System-generated NMI, leave to main handler */ @@ -395,10 +409,10 @@ static int cf_check microcode_nmi_callback( * ucode_in_nmi. */ if ( cpu =3D=3D cpumask_first(&cpu_online_map) || - (!ucode_in_nmi && cpu =3D=3D primary) ) + (!ucode_in_nmi && primary_cpu) ) return 0; =20 - if ( cpu =3D=3D primary ) + if ( primary_cpu ) ret =3D primary_thread_work(nmi_patch); else ret =3D secondary_nmi_work(); @@ -549,7 +563,7 @@ static int cf_check do_microcode_update(void *patch) */ if ( cpu =3D=3D cpumask_first(&cpu_online_map) ) ret =3D control_thread_fn(patch); - else if ( cpu =3D=3D cpumask_first(this_cpu(cpu_sibling_mask)) ) + else if ( is_cpu_primary(cpu) ) ret =3D primary_thread_fn(patch); else ret =3D secondary_thread_fn(); @@ -642,7 +656,7 @@ static long cf_check microcode_update_helper(void *data) /* Calculate the number of online CPU core */ nr_cores =3D 0; for_each_online_cpu(cpu) - if ( cpu =3D=3D cpumask_first(per_cpu(cpu_sibling_mask, cpu)) ) + if ( is_cpu_primary(cpu) ) nr_cores++; =20 printk(XENLOG_INFO "%u cores are to update their microcode\n", nr_core= s); --=20 2.17.1