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d="scan'208";a="97740141" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 1/3] x86/traps: Move do_general_protection() earlier Date: Mon, 20 Feb 2023 11:59:54 +0000 Message-ID: <20230220115956.1522728-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230220115956.1522728-1-andrew.cooper3@citrix.com> References: <20230220115956.1522728-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1676894475643100001 ... in order to clean up the declarations without needing to forward declare it for handle_gdt_ldt_mapping_fault() No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/traps.c | 157 +++++++++++++++++++++---------------------- 1 file changed, 78 insertions(+), 79 deletions(-) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index cade9e12f8fa..7fb0c54f884e 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1301,6 +1301,84 @@ void do_int3(struct cpu_user_regs *regs) pv_inject_hw_exception(TRAP_int3, X86_EVENT_NO_EC); } =20 +void do_general_protection(struct cpu_user_regs *regs) +{ +#ifdef CONFIG_PV + struct vcpu *v =3D current; +#endif + + if ( regs->error_code & X86_XEC_EXT ) + goto hardware_gp; + + if ( !guest_mode(regs) ) + goto gp_in_kernel; + +#ifdef CONFIG_PV + /* + * Cunning trick to allow arbitrary "INT n" handling. + * + * We set DPL =3D=3D 0 on all vectors in the IDT. This prevents any IN= T + * instruction from trapping to the appropriate vector, when that migh= t not + * be expected by Xen or the guest OS. For example, that entry might b= e for + * a fault handler (unlike traps, faults don't increment EIP), or might + * expect an error code on the stack (which a software trap never + * provides), or might be a hardware interrupt handler that doesn't li= ke + * being called spuriously. + * + * Instead, a GPF occurs with the faulting IDT vector in the error cod= e. + * Bit 1 is set to indicate that an IDT entry caused the fault. Bit 0 = is + * clear (which got already checked above) to indicate that it's a sof= tware + * fault, not a hardware one. + * + * NOTE: Vectors 3 and 4 are dealt with from their own handler. This is + * okay because they can only be triggered by an explicit DPL-checked + * instruction. The DPL specified by the guest OS for these vectors is= NOT + * CHECKED!! + */ + if ( regs->error_code & X86_XEC_IDT ) + { + /* This fault must be due to instruction. */ + uint8_t vector =3D regs->error_code >> 3; + const struct trap_info *ti =3D &v->arch.pv.trap_ctxt[vector]; + + if ( permit_softint(TI_GET_DPL(ti), v, regs) ) + { + regs->rip +=3D 2; + pv_inject_sw_interrupt(vector); + return; + } + } + else if ( is_pv_32bit_vcpu(v) && regs->error_code ) + { + pv_emulate_gate_op(regs); + return; + } + + /* Emulate some simple privileged and I/O instructions. */ + if ( (regs->error_code =3D=3D 0) && + pv_emulate_privileged_op(regs) ) + { + trace_trap_one_addr(TRC_PV_EMULATE_PRIVOP, regs->rip); + return; + } + + /* Pass on GPF as is. */ + pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + return; +#endif + + gp_in_kernel: + if ( likely(extable_fixup(regs, true)) ) + return; + + hardware_gp: + if ( debugger_trap_fatal(TRAP_gp_fault, regs) ) + return; + + show_execution_state(regs); + panic("GENERAL PROTECTION FAULT\n[error_code=3D%04x]\n", regs->error_c= ode); +} + #ifdef CONFIG_PV static int handle_ldt_mapping_fault(unsigned int offset, struct cpu_user_regs *regs) @@ -1666,85 +1744,6 @@ void __init do_early_page_fault(struct cpu_user_regs= *regs) } } =20 -void do_general_protection(struct cpu_user_regs *regs) -{ -#ifdef CONFIG_PV - struct vcpu *v =3D current; -#endif - - if ( regs->error_code & X86_XEC_EXT ) - goto hardware_gp; - - if ( !guest_mode(regs) ) - goto gp_in_kernel; - -#ifdef CONFIG_PV - /* - * Cunning trick to allow arbitrary "INT n" handling. - * - * We set DPL =3D=3D 0 on all vectors in the IDT. This prevents any IN= T - * instruction from trapping to the appropriate vector, when that migh= t not - * be expected by Xen or the guest OS. For example, that entry might b= e for - * a fault handler (unlike traps, faults don't increment EIP), or might - * expect an error code on the stack (which a software trap never - * provides), or might be a hardware interrupt handler that doesn't li= ke - * being called spuriously. - * - * Instead, a GPF occurs with the faulting IDT vector in the error cod= e. - * Bit 1 is set to indicate that an IDT entry caused the fault. Bit 0 = is - * clear (which got already checked above) to indicate that it's a sof= tware - * fault, not a hardware one. - * - * NOTE: Vectors 3 and 4 are dealt with from their own handler. This is - * okay because they can only be triggered by an explicit DPL-checked - * instruction. The DPL specified by the guest OS for these vectors is= NOT - * CHECKED!! - */ - if ( regs->error_code & X86_XEC_IDT ) - { - /* This fault must be due to instruction. */ - uint8_t vector =3D regs->error_code >> 3; - const struct trap_info *ti =3D &v->arch.pv.trap_ctxt[vector]; - - if ( permit_softint(TI_GET_DPL(ti), v, regs) ) - { - regs->rip +=3D 2; - pv_inject_sw_interrupt(vector); - return; - } - } - else if ( is_pv_32bit_vcpu(v) && regs->error_code ) - { - pv_emulate_gate_op(regs); - return; - } - - /* Emulate some simple privileged and I/O instructions. */ - if ( (regs->error_code =3D=3D 0) && - pv_emulate_privileged_op(regs) ) - { - trace_trap_one_addr(TRC_PV_EMULATE_PRIVOP, regs->rip); - return; - } - - /* Pass on GPF as is. */ - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); - return; -#endif - - gp_in_kernel: - - if ( likely(extable_fixup(regs, true)) ) - return; - - hardware_gp: - if ( debugger_trap_fatal(TRAP_gp_fault, regs) ) - return; - - show_execution_state(regs); - panic("GENERAL PROTECTION FAULT\n[error_code=3D%04x]\n", regs->error_c= ode); -} - static bool pci_serr_cont; =20 static bool pci_serr_nmicont(void) --=20 2.30.2 From nobody Sun May 12 20:52:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1676894468; cv=none; d=zohomail.com; s=zohoarc; b=XESRF3B8JyiHvkGHl127xhJC6NkC0qk4hEVb2KYrFcY4W7MQYFKTYhQu4Ma6um4XDh2htEcnbj33n7dFxIPOVDc+zvlOs631Rvaiu0JECGZ+gv9GQfnxsQ5nS1p79bZ8T++XhtW4j5KrfBNMvcsdh+O3VQZmmhF8LKL1Mw+yg50= ARC-Message-Signature: i=1; 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d="scan'208";a="97740134" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Konrad Rzeszutek Wilk , Ross Lagerwall Subject: [PATCH 2/3] x86/entry: Rework the exception entrypoints Date: Mon, 20 Feb 2023 11:59:55 +0000 Message-ID: <20230220115956.1522728-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230220115956.1522728-1-andrew.cooper3@citrix.com> References: <20230220115956.1522728-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1676894469439100002 This fixes two issues preventing livepatching. First, that #PF and NMI fall through into other functions, and second to add ELF metadata. Use a macro to generate the entrypoints programatically, rather than opencoding them all. Switch to using the architectural short names. Remove the DECLARE_TRAP_HANDLER{,_CONST}() infrastructure. Only NMI/#MC are referenced externally (and NMI will cease to be soon, as part of adding FRED support). Move the entrypoint declarations into the respective traps.c whe= re they're used, rather than keeping them visible across ~all of Xen. Drop the long-stale comment at the top of init_idt_traps(). It's mostly discussing a 32bit Xen. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Konrad Rzeszutek Wilk CC: Ross Lagerwall --- xen/arch/x86/include/asm/processor.h | 34 +------ xen/arch/x86/pv/traps.c | 2 + xen/arch/x86/traps.c | 70 ++++++++----- xen/arch/x86/x86_64/entry.S | 147 +++++++++------------------ 4 files changed, 95 insertions(+), 158 deletions(-) diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index b95d2483212a..8725e0df11e9 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -476,38 +476,8 @@ extern void mtrr_bp_init(void); =20 void mcheck_init(struct cpuinfo_x86 *c, bool_t bsp); =20 -#define DECLARE_TRAP_HANDLER(_name) \ - void _name(void); \ - void do_ ## _name(struct cpu_user_regs *regs) -#define DECLARE_TRAP_HANDLER_CONST(_name) \ - void _name(void); \ - void do_ ## _name(const struct cpu_user_regs *regs) - -DECLARE_TRAP_HANDLER(divide_error); -DECLARE_TRAP_HANDLER(debug); -DECLARE_TRAP_HANDLER_CONST(nmi); -DECLARE_TRAP_HANDLER(int3); -DECLARE_TRAP_HANDLER(overflow); -DECLARE_TRAP_HANDLER(bounds); -DECLARE_TRAP_HANDLER(invalid_op); -DECLARE_TRAP_HANDLER(device_not_available); -DECLARE_TRAP_HANDLER(double_fault); -DECLARE_TRAP_HANDLER(invalid_TSS); -DECLARE_TRAP_HANDLER(segment_not_present); -DECLARE_TRAP_HANDLER(stack_segment); -DECLARE_TRAP_HANDLER(general_protection); -DECLARE_TRAP_HANDLER(page_fault); -DECLARE_TRAP_HANDLER(early_page_fault); -DECLARE_TRAP_HANDLER(coprocessor_error); -DECLARE_TRAP_HANDLER(simd_coprocessor_error); -DECLARE_TRAP_HANDLER_CONST(machine_check); -DECLARE_TRAP_HANDLER(alignment_check); -DECLARE_TRAP_HANDLER(entry_CP); - -DECLARE_TRAP_HANDLER(entry_int82); - -#undef DECLARE_TRAP_HANDLER_CONST -#undef DECLARE_TRAP_HANDLER +void do_nmi(const struct cpu_user_regs *regs); +void do_machine_check(const struct cpu_user_regs *regs); =20 void trap_nop(void); =20 diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 97fe54b5ee5a..21f4860f7832 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -144,6 +144,8 @@ static void cf_check nmi_softirq(void) *v_ptr =3D NULL; } =20 +void entry_int82(void); + void __init pv_trap_init(void) { #ifdef CONFIG_PV32 diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 7fb0c54f884e..bfd335777177 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2184,35 +2184,49 @@ void percpu_traps_init(void) wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); } =20 +/* Exception entries */ +void entry_DE(void); +void entry_DB(void); +void entry_NMI(void); +void entry_BP(void); +void entry_OF(void); +void entry_BR(void); +void entry_UD(void); +void entry_NM(void); +void entry_DF(void); +void entry_TS(void); +void entry_NP(void); +void entry_SS(void); +void entry_GP(void); +void early_page_fault(void); +void entry_PF(void); +void entry_MF(void); +void entry_AC(void); +void entry_MC(void); +void entry_XM(void); +void entry_CP(void); + void __init init_idt_traps(void) { - /* - * Note that interrupt gates are always used, rather than trap gates. = We - * must have interrupts disabled until DS/ES/FS/GS are saved because t= he - * first activation must have the "bad" value(s) for these registers a= nd - * we may lose them if another activation is installed before they are - * saved. The page-fault handler also needs interrupts disabled until = %cr2 - * has been read and saved on the stack. - */ - set_intr_gate(TRAP_divide_error,÷_error); - set_intr_gate(TRAP_debug,&debug); - set_intr_gate(TRAP_nmi,&nmi); - set_swint_gate(TRAP_int3,&int3); /* usable from all privileges= */ - set_swint_gate(TRAP_overflow,&overflow); /* usable from all privileges= */ - set_intr_gate(TRAP_bounds,&bounds); - set_intr_gate(TRAP_invalid_op,&invalid_op); - set_intr_gate(TRAP_no_device,&device_not_available); - set_intr_gate(TRAP_double_fault,&double_fault); - set_intr_gate(TRAP_invalid_tss,&invalid_TSS); - set_intr_gate(TRAP_no_segment,&segment_not_present); - set_intr_gate(TRAP_stack_error,&stack_segment); - set_intr_gate(TRAP_gp_fault,&general_protection); - set_intr_gate(TRAP_page_fault,&early_page_fault); - set_intr_gate(TRAP_copro_error,&coprocessor_error); - set_intr_gate(TRAP_alignment_check,&alignment_check); - set_intr_gate(TRAP_machine_check,&machine_check); - set_intr_gate(TRAP_simd_error,&simd_coprocessor_error); - set_intr_gate(X86_EXC_CP, entry_CP); + set_intr_gate (X86_EXC_DE, entry_DE); + set_intr_gate (X86_EXC_DB, entry_DB); + set_intr_gate (X86_EXC_NMI, entry_NMI); + set_swint_gate(X86_EXC_BP, entry_BP); + set_swint_gate(X86_EXC_OF, entry_OF); + set_intr_gate (X86_EXC_BR, entry_BR); + set_intr_gate (X86_EXC_UD, entry_UD); + set_intr_gate (X86_EXC_NM, entry_NM); + set_intr_gate (X86_EXC_DF, entry_DF); + set_intr_gate (X86_EXC_TS, entry_TS); + set_intr_gate (X86_EXC_NP, entry_NP); + set_intr_gate (X86_EXC_SS, entry_SS); + set_intr_gate (X86_EXC_GP, entry_GP); + set_intr_gate (X86_EXC_PF, early_page_fault); + set_intr_gate (X86_EXC_MF, entry_MF); + set_intr_gate (X86_EXC_AC, entry_AC); + set_intr_gate (X86_EXC_MC, entry_MC); + set_intr_gate (X86_EXC_XM, entry_XM); + set_intr_gate (X86_EXC_CP, entry_CP); =20 /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ enable_each_ist(idt_table); @@ -2231,7 +2245,7 @@ void __init trap_init(void) unsigned int vector; =20 /* Replace early pagefault with real pagefault handler. */ - set_intr_gate(TRAP_page_fault, &page_fault); + set_intr_gate(X86_EXC_PF, entry_PF); =20 pv_trap_init(); =20 diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index ae012851819a..6d7c15ce4371 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -142,6 +142,50 @@ process_trap: =20 .section .text.entry, "ax", @progbits =20 +.macro IDT_ENTRY vec label handler +ENTRY(\label) + ENDBR64 + .if ((1 << \vec) & X86_EXC_HAVE_EC) =3D=3D 0 + push $0 + .endif + movl $\vec, 4(%rsp) + jmp \handler + + .type \label, @function + .size \label, . - \label +.endm + +.macro ENTRY vec label + IDT_ENTRY \vec \label handle_exception +.endm +.macro ENTRY_IST vec label + IDT_ENTRY \vec \label handle_ist_exception +.endm + + +ENTRY X86_EXC_DE entry_DE /* 00 Divide Error */ +ENTRY_IST X86_EXC_DB entry_DB /* 01 Debug Exception */ +ENTRY_IST X86_EXC_NMI entry_NMI /* 02 Non-Maskable Interrupt */ +ENTRY X86_EXC_BP entry_BP /* 03 Breakpoint (int3) */ +ENTRY X86_EXC_OF entry_OF /* 04 Overflow (into) */ +ENTRY X86_EXC_BR entry_BR /* 05 Bound Range */ +ENTRY X86_EXC_UD entry_UD /* 06 Undefined Opcode */ +ENTRY X86_EXC_NM entry_NM /* 07 No Maths (Device Not Present) */ +/* _IST X86_EXC_DF entry_DF 08 Double Fault - Handled specially */ +/* X86_EXC_CSO entry_CSO 09 Coprocessor Segment Override - Autog= en */ +ENTRY X86_EXC_TS entry_TS /* 10 Invalid TSS */ +ENTRY X86_EXC_NP entry_NP /* 11 Segment Not Present */ +ENTRY X86_EXC_SS entry_SS /* 12 Stack Segment Fault */ +ENTRY X86_EXC_GP entry_GP /* 13 General Protection Fault */ +ENTRY X86_EXC_PF entry_PF /* 14 Page Fault */ +/* X86_EXC_SPV entry_SPV 15 PIC Spurious Interrupt Vector - Auto= gen */ +ENTRY X86_EXC_MF entry_MF /* 16 Maths Fault (x87 FPU) */ +ENTRY X86_EXC_AC entry_AC /* 17 Alignment Check */ +ENTRY_IST X86_EXC_MC entry_MC /* 18 Machine Check */ +ENTRY X86_EXC_XM entry_XM /* 19 SIMD Maths Fault */ +/* X86_EXC_VE entry_VE 20 Virtualisation Exception - Not imple= mented */ +ENTRY X86_EXC_CP entry_CP /* 21 Control-flow Protection */ + /* %rbx: struct vcpu, interrupts disabled */ restore_all_guest: ASSERT_INTERRUPTS_DISABLED @@ -707,9 +751,6 @@ ENTRY(common_interrupt) mov %bl, STACK_CPUINFO_FIELD(use_pv_cr3)(%r14) jmp ret_from_intr =20 -ENTRY(page_fault) - ENDBR64 - movl $TRAP_page_fault,4(%rsp) /* No special register assumptions. */ GLOBAL(handle_exception) ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP @@ -882,91 +923,7 @@ FATAL_exception_with_ints_disabled: call fatal_trap BUG /* fatal_trap() shouldn't return. */ =20 -ENTRY(divide_error) - ENDBR64 - pushq $0 - movl $TRAP_divide_error,4(%rsp) - jmp handle_exception - -ENTRY(coprocessor_error) - ENDBR64 - pushq $0 - movl $TRAP_copro_error,4(%rsp) - jmp handle_exception - -ENTRY(simd_coprocessor_error) - ENDBR64 - pushq $0 - movl $TRAP_simd_error,4(%rsp) - jmp handle_exception - -ENTRY(device_not_available) - ENDBR64 - pushq $0 - movl $TRAP_no_device,4(%rsp) - jmp handle_exception - -ENTRY(debug) - ENDBR64 - pushq $0 - movl $TRAP_debug,4(%rsp) - jmp handle_ist_exception - -ENTRY(int3) - ENDBR64 - pushq $0 - movl $TRAP_int3,4(%rsp) - jmp handle_exception - -ENTRY(overflow) - ENDBR64 - pushq $0 - movl $TRAP_overflow,4(%rsp) - jmp handle_exception - -ENTRY(bounds) - ENDBR64 - pushq $0 - movl $TRAP_bounds,4(%rsp) - jmp handle_exception - -ENTRY(invalid_op) - ENDBR64 - pushq $0 - movl $TRAP_invalid_op,4(%rsp) - jmp handle_exception - -ENTRY(invalid_TSS) - ENDBR64 - movl $TRAP_invalid_tss,4(%rsp) - jmp handle_exception - -ENTRY(segment_not_present) - ENDBR64 - movl $TRAP_no_segment,4(%rsp) - jmp handle_exception - -ENTRY(stack_segment) - ENDBR64 - movl $TRAP_stack_error,4(%rsp) - jmp handle_exception - -ENTRY(general_protection) - ENDBR64 - movl $TRAP_gp_fault,4(%rsp) - jmp handle_exception - -ENTRY(alignment_check) - ENDBR64 - movl $TRAP_alignment_check,4(%rsp) - jmp handle_exception - -ENTRY(entry_CP) - ENDBR64 - movl $X86_EXC_CP, 4(%rsp) - jmp handle_exception - -ENTRY(double_fault) +ENTRY(entry_DF) ENDBR64 movl $TRAP_double_fault,4(%rsp) /* Set AC to reduce chance of further SMAP faults */ @@ -991,10 +948,10 @@ ENTRY(double_fault) call do_double_fault BUG /* do_double_fault() shouldn't return. */ =20 -ENTRY(nmi) - ENDBR64 - pushq $0 - movl $TRAP_nmi,4(%rsp) + .type entry_DF, @function + .size entry_DF, . - entry_DF + + handle_ist_exception: ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP SAVE_ALL @@ -1120,12 +1077,6 @@ handle_ist_exception: jmp restore_all_xen #endif =20 -ENTRY(machine_check) - ENDBR64 - pushq $0 - movl $TRAP_machine_check,4(%rsp) - jmp handle_ist_exception - /* No op trap handler. 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d="scan'208";a="97740136" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 3/3] x86/treewide: Drop the TRAP_* legacy names Date: Mon, 20 Feb 2023 11:59:56 +0000 Message-ID: <20230220115956.1522728-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230220115956.1522728-1-andrew.cooper3@citrix.com> References: <20230220115956.1522728-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1676894475657100002 We have two naming schemes for exceptions - X86_EXC_?? which use the archtiectural abbreviations, and TRAP_* which is a mix of terminology and nonstandard abbrevations. Switch to X86_EXC_* uniformly. No funcational change, confirmed by diffing the disassembly. Only 7 binary changes, and they're all __LINE__ being passed into printk(). Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu This is a bit of a large patch, but its treewide cleanup and splitting it up by major subsystem doesn't make it easier to review. Diffing the disassmeb= ly is by far the easiest way to confirm no functional change. --- xen/arch/x86/cpu/mcheck/vmce.c | 2 +- xen/arch/x86/cpuid.c | 6 +- xen/arch/x86/crash.c | 6 +- xen/arch/x86/domain.c | 2 +- xen/arch/x86/extable.c | 8 +-- xen/arch/x86/hvm/emulate.c | 17 +++--- xen/arch/x86/hvm/hvm.c | 61 ++++++++++---------- xen/arch/x86/hvm/io.c | 2 +- xen/arch/x86/hvm/svm/emulate.c | 2 +- xen/arch/x86/hvm/svm/intr.c | 2 +- xen/arch/x86/hvm/svm/nestedsvm.c | 32 +++++------ xen/arch/x86/hvm/svm/svm.c | 76 ++++++++++++------------- xen/arch/x86/hvm/svm/vmcb.c | 4 +- xen/arch/x86/hvm/vm_event.c | 10 ++-- xen/arch/x86/hvm/vmx/intr.c | 2 +- xen/arch/x86/hvm/vmx/realmode.c | 16 +++--- xen/arch/x86/hvm/vmx/vmcs.c | 4 +- xen/arch/x86/hvm/vmx/vmx.c | 79 +++++++++++++------------- xen/arch/x86/hvm/vmx/vvmx.c | 28 ++++----- xen/arch/x86/include/asm/domain.h | 2 +- xen/arch/x86/include/asm/hvm/hvm.h | 8 +-- xen/arch/x86/include/asm/processor.h | 44 +++----------- xen/arch/x86/include/asm/x86-defns.h | 2 + xen/arch/x86/machine_kexec.c | 2 +- xen/arch/x86/mm.c | 2 +- xen/arch/x86/mm/mem_access.c | 2 +- xen/arch/x86/mm/shadow/hvm.c | 2 +- xen/arch/x86/mm/shadow/multi.c | 10 ++-- xen/arch/x86/pv/callback.c | 6 +- xen/arch/x86/pv/emul-gate-op.c | 34 +++++------ xen/arch/x86/pv/emul-inv-op.c | 2 +- xen/arch/x86/pv/emul-priv-op.c | 14 ++--- xen/arch/x86/pv/emulate.c | 2 +- xen/arch/x86/pv/iret.c | 2 +- xen/arch/x86/pv/ro-page-fault.c | 4 +- xen/arch/x86/pv/traps.c | 10 ++-- xen/arch/x86/traps.c | 34 +++++------ xen/arch/x86/x86_64/compat/entry.S | 12 ++-- xen/arch/x86/x86_64/entry.S | 20 +++---- xen/arch/x86/x86_emulate.c | 10 ++-- xen/arch/x86/x86_emulate/x86_emulate.h | 4 +- 41 files changed, 278 insertions(+), 309 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index af30811afd44..6f1a7e4de013 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -414,7 +414,7 @@ int inject_vmce(struct domain *d, int vcpu) continue; =20 if ( (is_hvm_domain(d) || - pv_trap_callback_registered(v, TRAP_machine_check)) && + pv_trap_callback_registered(v, X86_EXC_MC)) && !test_and_set_bool(v->arch.mce_pending) ) { mce_printk(MCE_VERBOSE, "MCE: inject vMCE to %pv\n", v); diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index b22725c492e7..49d401216ed3 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -1040,7 +1040,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, /* OSXSAVE clear in policy. Fast-forward CR4 back in. */ if ( (v->arch.pv.ctrlreg[4] & X86_CR4_OSXSAVE) || (p->basic.xsave && - regs->entry_vector =3D=3D TRAP_invalid_op && + regs->entry_vector =3D=3D X86_EXC_UD && guest_kernel_mode(v, regs) && (read_cr4() & X86_CR4_OSXSAVE)) ) res->c |=3D cpufeat_mask(X86_FEATURE_OSXSAVE); @@ -1076,7 +1076,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, * emulated CPUID from a faulted CPUID by whether a #UD or= #GP * fault is currently being serviced. Yuck... */ - if ( cpu_has_monitor && regs->entry_vector =3D=3D TRAP_gp_= fault ) + if ( cpu_has_monitor && regs->entry_vector =3D=3D X86_EXC_= GP ) res->c |=3D cpufeat_mask(X86_FEATURE_MONITOR); =20 /* @@ -1101,7 +1101,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, regs =3D guest_cpu_user_regs(); if ( is_pv_domain(d) && is_hardware_domain(d) && guest_kernel_mode(v, regs) && cpu_has_monitor && - regs->entry_vector =3D=3D TRAP_gp_fault ) + regs->entry_vector =3D=3D X86_EXC_GP ) *res =3D raw_cpuid_policy.basic.raw[5]; break; =20 diff --git a/xen/arch/x86/crash.c b/xen/arch/x86/crash.c index 7850f0af2473..a789416ca3ae 100644 --- a/xen/arch/x86/crash.c +++ b/xen/arch/x86/crash.c @@ -60,7 +60,7 @@ static int noreturn cf_check do_nmi_crash( * This update is safe from a security point of view, as this * pcpu is never going to try to sysret back to a PV vcpu. */ - set_ist(&idt_tables[cpu][TRAP_machine_check], IST_NONE); + set_ist(&idt_tables[cpu][X86_EXC_MC], IST_NONE); =20 kexec_crash_save_cpu(); __stop_this_cpu(); @@ -130,9 +130,9 @@ static void nmi_shootdown_cpus(void) * Disable IST for MCEs to avoid stack corruption race conditions, and * change the NMI handler to a nop to avoid deviation from this codepa= th. */ - _set_gate_lower(&idt_tables[cpu][TRAP_nmi], + _set_gate_lower(&idt_tables[cpu][X86_EXC_NMI], SYS_DESC_irq_gate, 0, &trap_nop); - set_ist(&idt_tables[cpu][TRAP_machine_check], IST_NONE); + set_ist(&idt_tables[cpu][X86_EXC_MC], IST_NONE); =20 set_nmi_callback(do_nmi_crash); smp_send_nmi_allbutself(); diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index db3ebf062dab..d56920b733df 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -112,7 +112,7 @@ void play_dead(void) local_irq_disable(); =20 /* Change the NMI handler to a nop (see comment below). */ - _set_gate_lower(&idt_tables[cpu][TRAP_nmi], SYS_DESC_irq_gate, 0, + _set_gate_lower(&idt_tables[cpu][X86_EXC_NMI], SYS_DESC_irq_gate, 0, &trap_nop); =20 /* diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c index 4913c4a6dd5d..5253ae41434b 100644 --- a/xen/arch/x86/extable.c +++ b/xen/arch/x86/extable.c @@ -135,15 +135,15 @@ static int __init cf_check stub_selftest(void) } tests[] __initconst =3D { #define endbr64 0xf3, 0x0f, 0x1e, 0xfa { .opc =3D { endbr64, 0x0f, 0xb9, 0xc3, 0xc3 }, /* ud1 */ - .res.fields.trapnr =3D TRAP_invalid_op }, + .res.fields.trapnr =3D X86_EXC_UD }, { .opc =3D { endbr64, 0x90, 0x02, 0x00, 0xc3 }, /* nop; add (%rax)= ,%al */ .rax =3D 0x0123456789abcdef, - .res.fields.trapnr =3D TRAP_gp_fault }, + .res.fields.trapnr =3D X86_EXC_GP }, { .opc =3D { endbr64, 0x02, 0x04, 0x04, 0xc3 }, /* add (%rsp,%rax)= ,%al */ .rax =3D 0xfedcba9876543210, - .res.fields.trapnr =3D TRAP_stack_error }, + .res.fields.trapnr =3D X86_EXC_SS }, { .opc =3D { endbr64, 0xcc, 0xc3, 0xc3, 0xc3 }, /* int3 */ - .res.fields.trapnr =3D TRAP_int3 }, + .res.fields.trapnr =3D X86_EXC_BP }, #undef endbr64 }; unsigned long addr =3D this_cpu(stubs.addr) + STUB_BUF_SIZE / 2; diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index 95364deb1996..adb3b084b3b7 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -910,9 +910,8 @@ static int hvmemul_virtual_to_linear( * determine the kind of exception (#GP or #TS) in that case. */ if ( is_x86_user_segment(seg) ) - x86_emul_hw_exception((seg =3D=3D x86_seg_ss) - ? TRAP_stack_error - : TRAP_gp_fault, 0, &hvmemul_ctxt->ctxt); + x86_emul_hw_exception((seg =3D=3D x86_seg_ss) ? X86_EXC_SS : X86_E= XC_GP, + 0, &hvmemul_ctxt->ctxt); =20 return X86EMUL_EXCEPTION; } @@ -2227,7 +2226,7 @@ static int cf_check hvmemul_write_cr( } =20 if ( rc =3D=3D X86EMUL_EXCEPTION ) - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); =20 return rc; } @@ -2263,7 +2262,7 @@ static int cf_check hvmemul_read_msr( int rc =3D hvm_msr_read_intercept(reg, val); =20 if ( rc =3D=3D X86EMUL_EXCEPTION ) - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); =20 return rc; } @@ -2276,7 +2275,7 @@ static int cf_check hvmemul_write_msr( int rc =3D hvm_msr_write_intercept(reg, val, true); =20 if ( rc =3D=3D X86EMUL_EXCEPTION ) - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); =20 return rc; } @@ -2530,7 +2529,7 @@ static int cf_check hvmemul_tlb_op( paging_invlpg(current, addr); else { - x86_emul_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC, ctxt); + x86_emul_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC, ctxt); rc =3D X86EMUL_EXCEPTION; } break; @@ -2548,7 +2547,7 @@ static int cf_check hvmemul_vmfunc( return X86EMUL_UNHANDLEABLE; rc =3D alternative_call(hvm_funcs.altp2m_vcpu_emulate_vmfunc, ctxt->re= gs); if ( rc =3D=3D X86EMUL_EXCEPTION ) - x86_emul_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC, ctxt); + x86_emul_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC, ctxt); =20 return rc; } @@ -2676,7 +2675,7 @@ static int _hvm_emulate_one(struct hvm_emulate_ctxt *= hvmemul_ctxt, } =20 if ( hvmemul_ctxt->ctxt.retire.singlestep ) - hvm_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); =20 new_intr_shadow =3D hvmemul_ctxt->intr_shadow; =20 diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5c1e64189600..bab0ed5d2d6a 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -256,25 +256,25 @@ int hvm_event_needs_reinjection(uint8_t type, uint8_t= vector) uint8_t hvm_combine_hw_exceptions(uint8_t vec1, uint8_t vec2) { const unsigned int contributory_exceptions =3D - (1 << TRAP_divide_error) | - (1 << TRAP_invalid_tss) | - (1 << TRAP_no_segment) | - (1 << TRAP_stack_error) | - (1 << TRAP_gp_fault); + (1 << X86_EXC_DE) | + (1 << X86_EXC_TS) | + (1 << X86_EXC_NP) | + (1 << X86_EXC_SS) | + (1 << X86_EXC_GP); const unsigned int page_faults =3D - (1 << TRAP_page_fault) | - (1 << TRAP_virtualisation); + (1 << X86_EXC_PF) | + (1 << X86_EXC_VE); =20 /* Exception during double-fault delivery always causes a triple fault= . */ - if ( vec1 =3D=3D TRAP_double_fault ) + if ( vec1 =3D=3D X86_EXC_DF ) { hvm_triple_fault(); - return TRAP_double_fault; /* dummy return */ + return X86_EXC_DF; /* dummy return */ } =20 /* Exception during page-fault delivery always causes a double fault. = */ if ( (1u << vec1) & page_faults ) - return TRAP_double_fault; + return X86_EXC_DF; =20 /* Discard the first exception if it's benign or if we now have a #PF.= */ if ( !((1u << vec1) & contributory_exceptions) || @@ -282,7 +282,7 @@ uint8_t hvm_combine_hw_exceptions(uint8_t vec1, uint8_t= vec2) return vec2; =20 /* Cannot combine the exceptions: double fault. */ - return TRAP_double_fault; + return X86_EXC_DF; } =20 void hvm_set_rdtsc_exiting(struct domain *d, bool_t enable) @@ -1700,7 +1700,7 @@ void hvm_inject_event(const struct x86_event *event) struct vcpu *curr =3D current; const uint8_t vector =3D event->vector; const bool has_ec =3D ((event->type =3D=3D X86_EVENTTYPE_HW_EXCEPTION)= && - (vector < 32) && ((TRAP_HAVE_EC & (1u << vector))= )); + (vector < 32) && ((X86_EXC_HAVE_EC & (1u << vecto= r)))); =20 ASSERT(vector =3D=3D event->vector); /* Confirm no truncation. */ if ( has_ec ) @@ -1782,7 +1782,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned l= ong gla, return -1; case NESTEDHVM_PAGEFAULT_MMIO: if ( !handle_mmio() ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return 1; case NESTEDHVM_PAGEFAULT_L0_ERROR: /* gpa is now translated to l1 guest address, update gfn. */ @@ -1799,7 +1799,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned l= ong gla, if ( !nestedhvm_vcpu_in_guestmode(curr) && hvm_mmio_internal(gpa) ) { if ( !handle_mmio_with_translation(gla, gpa >> PAGE_SHIFT, npfec) ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); rc =3D 1; goto out; } @@ -1926,7 +1926,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned l= ong gla, (p2m_is_discard_write(p2mt) || (p2mt =3D=3D p2m_ioreq_server))) ) { if ( !handle_mmio_with_translation(gla, gpa >> PAGE_SHIFT, npfec) ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); rc =3D 1; goto out_put_gfn; } @@ -2034,7 +2034,7 @@ int hvm_handle_xsetbv(u32 index, u64 new_bv) =20 rc =3D x86emul_write_xcr(index, new_bv, NULL); if ( rc !=3D X86EMUL_OKAY ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 return rc; } @@ -2167,7 +2167,7 @@ int hvm_mov_to_cr(unsigned int cr, unsigned int gpr) } =20 if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 return rc; =20 @@ -2817,7 +2817,7 @@ static int task_switch_load_seg( seg_desc_t *pdesc =3D NULL, desc; u8 dpl, rpl; bool_t writable; - int fault_type =3D TRAP_invalid_tss; + int fault_type =3D X86_EXC_TS; struct vcpu *v =3D current; =20 if ( eflags & X86_EFLAGS_VM ) @@ -2910,8 +2910,7 @@ static int task_switch_load_seg( /* Segment present in memory? */ if ( !(desc.b & _SEGMENT_P) ) { - fault_type =3D (seg !=3D x86_seg_ss) ? TRAP_no_segment - : TRAP_stack_error; + fault_type =3D (seg !=3D x86_seg_ss) ? X86_EXC_NP : X86_EXC_SS; goto fault; } } while ( !(desc.b & 0x100) && /* Ensure Accessed flag is set */ @@ -3008,9 +3007,9 @@ void hvm_task_switch( =20 if ( ((tss_sel & 0xfff8) + 7) > gdt.limit ) { - hvm_inject_hw_exception((taskswitch_reason =3D=3D TSW_iret) ? - TRAP_invalid_tss : TRAP_gp_fault, - tss_sel & 0xfff8); + hvm_inject_hw_exception( + (taskswitch_reason =3D=3D TSW_iret) ? X86_EXC_TS : X86_EXC_GP, + tss_sel & 0xfff8); goto out; } =20 @@ -3037,20 +3036,20 @@ void hvm_task_switch( if ( tr.type !=3D ((taskswitch_reason =3D=3D TSW_iret) ? 0xb : 0x9) ) { hvm_inject_hw_exception( - (taskswitch_reason =3D=3D TSW_iret) ? TRAP_invalid_tss : TRAP_= gp_fault, + (taskswitch_reason =3D=3D TSW_iret) ? X86_EXC_TS : X86_EXC_GP, tss_sel & 0xfff8); goto out; } =20 if ( !tr.p ) { - hvm_inject_hw_exception(TRAP_no_segment, tss_sel & 0xfff8); + hvm_inject_hw_exception(X86_EXC_NP, tss_sel & 0xfff8); goto out; } =20 if ( tr.limit < (sizeof(tss)-1) ) { - hvm_inject_hw_exception(TRAP_invalid_tss, tss_sel & 0xfff8); + hvm_inject_hw_exception(X86_EXC_TS, tss_sel & 0xfff8); goto out; } =20 @@ -3119,7 +3118,7 @@ void hvm_task_switch( =20 rc =3D hvm_set_cr3(tss.cr3, false, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) goto out; =20 @@ -3203,7 +3202,7 @@ void hvm_task_switch( } =20 if ( (tss.trace & 1) && !exn_raised ) - hvm_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); =20 out: hvm_unmap_entry(optss_desc); @@ -3478,7 +3477,7 @@ int hvm_vmexit_cpuid(struct cpu_user_regs *regs, unsi= gned int inst_len) if ( curr->arch.msrs->misc_features_enables.cpuid_faulting && hvm_get_cpl(curr) > 0 ) { - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return 1; /* Don't advance the guest IP! */ } =20 @@ -3855,7 +3854,7 @@ void hvm_ud_intercept(struct cpu_user_regs *regs) =20 if ( !should_emulate ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 @@ -3863,7 +3862,7 @@ void hvm_ud_intercept(struct cpu_user_regs *regs) { case X86EMUL_UNHANDLEABLE: case X86EMUL_UNIMPLEMENTED: - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); break; case X86EMUL_EXCEPTION: hvm_inject_event(&ctxt.ctxt.event); diff --git a/xen/arch/x86/hvm/io.c b/xen/arch/x86/hvm/io.c index 5ae209d3b6b3..ae2feebd79e4 100644 --- a/xen/arch/x86/hvm/io.c +++ b/xen/arch/x86/hvm/io.c @@ -78,7 +78,7 @@ bool hvm_emulate_one_insn(hvm_emulate_validate_t *validat= e, const char *descr) =20 case X86EMUL_UNRECOGNIZED: hvm_dump_emulation_state(XENLOG_G_WARNING, descr, &ctxt, rc); - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); break; =20 case X86EMUL_EXCEPTION: diff --git a/xen/arch/x86/hvm/svm/emulate.c b/xen/arch/x86/hvm/svm/emulate.c index 16fc134883cf..4661cde44968 100644 --- a/xen/arch/x86/hvm/svm/emulate.c +++ b/xen/arch/x86/hvm/svm/emulate.c @@ -112,7 +112,7 @@ unsigned int svm_get_insn_len(struct vcpu *v, unsigned = int instr_enc) hvm_dump_emulation_state(XENLOG_G_WARNING, "SVM Insn len", &ctxt, X86EMUL_UNHANDLEABLE); =20 - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return 0; } =20 diff --git a/xen/arch/x86/hvm/svm/intr.c b/xen/arch/x86/hvm/svm/intr.c index 9525f3559392..5aa723979c88 100644 --- a/xen/arch/x86/hvm/svm/intr.c +++ b/xen/arch/x86/hvm/svm/intr.c @@ -47,7 +47,7 @@ static void svm_inject_nmi(struct vcpu *v) event.raw =3D 0; event.v =3D true; event.type =3D X86_EVENTTYPE_NMI; - event.vector =3D TRAP_nmi; + event.vector =3D X86_EXC_NMI; =20 ASSERT(!vmcb->event_inj.v); vmcb->event_inj =3D event; diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nested= svm.c index 9f5f35f16aff..1d7fe493cffc 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -194,7 +194,7 @@ static uint64_t nestedsvm_fpu_vmentry(uint64_t n1cr0, * Sync FPU state with l2 guest. */ vcr0 |=3D X86_CR0_TS; - n2vmcb->_exception_intercepts |=3D (1U << TRAP_no_device); + n2vmcb->_exception_intercepts |=3D (1U << X86_EXC_NM); } else if ( !(vcr0 & X86_CR0_TS) && (n2vmcb->_cr0 & X86_CR0_TS) ) { @@ -203,7 +203,7 @@ static uint64_t nestedsvm_fpu_vmentry(uint64_t n1cr0, * Sync FPU state with l2 guest. */ vcr0 &=3D ~X86_CR0_TS; - n2vmcb->_exception_intercepts &=3D ~(1U << TRAP_no_device); + n2vmcb->_exception_intercepts &=3D ~(1U << X86_EXC_NM); } =20 return vcr0; @@ -219,7 +219,7 @@ static void nestedsvm_fpu_vmexit(struct vmcb_struct *n1= vmcb, * Sync FPU state with l1 guest. */ n1vmcb->_cr0 |=3D X86_CR0_TS; - n1vmcb->_exception_intercepts |=3D (1U << TRAP_no_device); + n1vmcb->_exception_intercepts |=3D (1U << X86_EXC_NM); } else if ( !(n1cr0 & X86_CR0_TS) && (n1vmcb->_cr0 & X86_CR0_TS) ) { @@ -228,7 +228,7 @@ static void nestedsvm_fpu_vmexit(struct vmcb_struct *n1= vmcb, * Sync FPU state with l1 guest. */ n1vmcb->_cr0 &=3D ~X86_CR0_TS; - n1vmcb->_exception_intercepts &=3D ~(1U << TRAP_no_device); + n1vmcb->_exception_intercepts &=3D ~(1U << X86_EXC_NM); } } =20 @@ -283,7 +283,7 @@ static int nsvm_vcpu_hostrestore(struct vcpu *v, struct= cpu_user_regs *regs) v->arch.hvm.guest_efer =3D n1vmcb->_efer; rc =3D hvm_set_efer(n1vmcb->_efer); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_efer failed, rc: %u\n", rc); =20 @@ -291,7 +291,7 @@ static int nsvm_vcpu_hostrestore(struct vcpu *v, struct= cpu_user_regs *regs) v->arch.hvm.guest_cr[4] =3D n1vmcb->_cr4; rc =3D hvm_set_cr4(n1vmcb->_cr4, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr4 failed, rc: %u\n", rc); =20 @@ -302,7 +302,7 @@ static int nsvm_vcpu_hostrestore(struct vcpu *v, struct= cpu_user_regs *regs) n1vmcb->rflags &=3D ~X86_EFLAGS_VM; rc =3D hvm_set_cr0(n1vmcb->_cr0 | X86_CR0_PE, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr0 failed, rc: %u\n", rc); svm->ns_cr0 =3D v->arch.hvm.guest_cr[0]; @@ -335,7 +335,7 @@ static int nsvm_vcpu_hostrestore(struct vcpu *v, struct= cpu_user_regs *regs) } rc =3D hvm_set_cr3(n1vmcb->_cr3, false, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr3 failed, rc: %u\n", rc); =20 @@ -557,7 +557,7 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) v->arch.hvm.guest_efer =3D ns_vmcb->_efer; rc =3D hvm_set_efer(ns_vmcb->_efer); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_efer failed, rc: %u\n", rc); =20 @@ -565,7 +565,7 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) v->arch.hvm.guest_cr[4] =3D ns_vmcb->_cr4; rc =3D hvm_set_cr4(ns_vmcb->_cr4, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr4 failed, rc: %u\n", rc); =20 @@ -575,7 +575,7 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) v->arch.hvm.guest_cr[0] =3D ns_vmcb->_cr0; rc =3D hvm_set_cr0(cr0, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr0 failed, rc: %u\n", rc); =20 @@ -594,7 +594,7 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) /* hvm_set_cr3() below sets v->arch.hvm.guest_cr[3] for us. */ rc =3D hvm_set_cr3(ns_vmcb->_cr3, false, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr3 failed, rc: %u\n", rc); } @@ -610,7 +610,7 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) /* hvm_set_cr3() below sets v->arch.hvm.guest_cr[3] for us. */ rc =3D hvm_set_cr3(ns_vmcb->_cr3, false, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr3 failed, rc: %u\n", rc); } @@ -788,7 +788,7 @@ nsvm_vcpu_vmrun(struct vcpu *v, struct cpu_user_regs *r= egs) default: gdprintk(XENLOG_ERR, "nsvm_vcpu_vmentry failed, injecting #UD\n"); - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); /* Must happen after hvm_inject_hw_exception or it doesn't work ri= ght. */ nv->nv_vmswitch_in_progress =3D 0; return 1; @@ -1579,7 +1579,7 @@ void svm_vmexit_do_stgi(struct cpu_user_regs *regs, s= truct vcpu *v) */ if ( !nestedhvm_enabled(v->domain) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 @@ -1600,7 +1600,7 @@ void svm_vmexit_do_clgi(struct cpu_user_regs *regs, s= truct vcpu *v) =20 if ( !nsvm_efer_svm_enabled(v) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index fa7325720328..a9903c36bdda 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -91,7 +91,7 @@ static DEFINE_SPINLOCK(osvw_lock); static void svm_crash_or_fault(struct vcpu *v) { if ( vmcb_get_cpl(v->arch.hvm.svm.vmcb) ) - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); else domain_crash(v->domain); } @@ -118,7 +118,7 @@ void __update_guest_eip(struct cpu_user_regs *regs, uns= igned int inst_len) curr->arch.hvm.svm.vmcb->int_stat.intr_shadow =3D 0; =20 if ( regs->eflags & X86_EFLAGS_TF ) - hvm_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } =20 static void cf_check svm_cpu_down(void) @@ -133,7 +133,7 @@ static void svm_fpu_enter(struct vcpu *v) vcpu_restore_fpu_lazy(v); vmcb_set_exception_intercepts( n1vmcb, - vmcb_get_exception_intercepts(n1vmcb) & ~(1U << TRAP_no_device)); + vmcb_get_exception_intercepts(n1vmcb) & ~(1U << X86_EXC_NM)); } =20 static void cf_check svm_fpu_leave(struct vcpu *v) @@ -153,7 +153,7 @@ static void cf_check svm_fpu_leave(struct vcpu *v) { vmcb_set_exception_intercepts( n1vmcb, - vmcb_get_exception_intercepts(n1vmcb) | (1U << TRAP_no_device)= ); + vmcb_get_exception_intercepts(n1vmcb) | (1U << X86_EXC_NM)); vmcb_set_cr0(n1vmcb, vmcb_get_cr0(n1vmcb) | X86_CR0_TS); } } @@ -601,9 +601,9 @@ static void cf_check svm_cpuid_policy_changed(struct vc= pu *v) =20 if ( opt_hvm_fep || (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor)= ) - bitmap |=3D (1U << TRAP_invalid_op); + bitmap |=3D (1U << X86_EXC_UD); else - bitmap &=3D ~(1U << TRAP_invalid_op); + bitmap &=3D ~(1U << X86_EXC_UD); =20 vmcb_set_exception_intercepts(vmcb, bitmap); =20 @@ -1039,8 +1039,8 @@ static void noreturn cf_check svm_do_resume(void) =20 v->arch.hvm.debug_state_latch =3D debug_state; vmcb_set_exception_intercepts( - vmcb, debug_state ? (intercepts | (1U << TRAP_int3)) - : (intercepts & ~(1U << TRAP_int3))); + vmcb, debug_state ? (intercepts | (1U << X86_EXC_BP)) + : (intercepts & ~(1U << X86_EXC_BP))); } =20 if ( v->arch.hvm.svm.launch_core !=3D smp_processor_id() ) @@ -1227,7 +1227,7 @@ static void svm_emul_swint_injection(struct x86_event= *event) const struct vmcb_struct *vmcb =3D curr->arch.hvm.svm.vmcb; const struct cpu_user_regs *regs =3D guest_cpu_user_regs(); unsigned int trap =3D event->vector, type =3D event->type; - unsigned int fault =3D TRAP_gp_fault, ec =3D 0; + unsigned int fault =3D X86_EXC_GP, ec =3D 0; pagefault_info_t pfinfo; struct segment_register cs, idtr; unsigned int idte_size, idte_offset; @@ -1273,7 +1273,7 @@ static void svm_emul_swint_injection(struct x86_event= *event) { if ( rc =3D=3D HVMTRANS_bad_linear_to_gfn ) { - fault =3D TRAP_page_fault; + fault =3D X86_EXC_PF; ec =3D pfinfo.ec; event->cr2 =3D pfinfo.linear; } @@ -1309,7 +1309,7 @@ static void svm_emul_swint_injection(struct x86_event= *event) /* Is this entry present? */ if ( !(idte.b & (1u << 15)) ) { - fault =3D TRAP_no_segment; + fault =3D X86_EXC_NP; goto raise_exception; } =20 @@ -1350,14 +1350,14 @@ static void cf_check svm_inject_event(const struct = x86_event *event) =20 switch ( _event.vector | -(_event.type =3D=3D X86_EVENTTYPE_SW_INTERRU= PT) ) { - case TRAP_debug: + case X86_EXC_DB: if ( regs->eflags & X86_EFLAGS_TF ) { __restore_debug_registers(vmcb, curr); vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | DR_STEP); } /* fall through */ - case TRAP_int3: + case X86_EXC_BP: if ( curr->domain->debugger_attached ) { /* Debug/Int3: Trap to debugger. */ @@ -1366,7 +1366,7 @@ static void cf_check svm_inject_event(const struct x8= 6_event *event) } break; =20 - case TRAP_page_fault: + case X86_EXC_PF: ASSERT(_event.type =3D=3D X86_EVENTTYPE_HW_EXCEPTION); curr->arch.hvm.guest_cr[2] =3D _event.cr2; vmcb_set_cr2(vmcb, _event.cr2); @@ -1377,7 +1377,7 @@ static void cf_check svm_inject_event(const struct x8= 6_event *event) { _event.vector =3D hvm_combine_hw_exceptions( eventinj.vector, _event.vector); - if ( _event.vector =3D=3D TRAP_double_fault ) + if ( _event.vector =3D=3D X86_EXC_DF ) _event.error_code =3D 0; } =20 @@ -1450,7 +1450,7 @@ static void cf_check svm_inject_event(const struct x8= 6_event *event) ASSERT(!eventinj.ev || eventinj.ec =3D=3D (uint16_t)eventinj.ec); vmcb->event_inj =3D eventinj; =20 - if ( _event.vector =3D=3D TRAP_page_fault && + if ( _event.vector =3D=3D X86_EXC_PF && _event.type =3D=3D X86_EVENTTYPE_HW_EXCEPTION ) HVMTRACE_LONG_2D(PF_INJECT, _event.error_code, TRC_PAR_LONG(_event.cr2)); @@ -1785,7 +1785,7 @@ static void cf_check svm_fpu_dirty_intercept(void) { /* Check if l1 guest must make FPU ready for the l2 guest */ if ( v->arch.hvm.guest_cr[0] & X86_CR0_TS ) - hvm_inject_hw_exception(TRAP_no_device, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_NM, X86_EVENT_NO_EC); else vmcb_set_cr0(n1vmcb, vmcb_get_cr0(n1vmcb) & ~X86_CR0_TS); return; @@ -2229,7 +2229,7 @@ static void svm_do_msr_access(struct cpu_user_regs *r= egs) if ( rc =3D=3D X86EMUL_OKAY ) __update_guest_eip(regs, inst_len); else if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); } =20 static void svm_vmexit_do_hlt(struct vmcb_struct *vmcb, @@ -2252,7 +2252,7 @@ static void svm_vmexit_do_rdtsc(struct cpu_user_regs = *regs, bool rdtscp) =20 if ( rdtscp && !currd->arch.cpuid->extd.rdtscp ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 @@ -2290,14 +2290,14 @@ svm_vmexit_do_vmrun(struct cpu_user_regs *regs, { if ( !nsvm_efer_svm_enabled(v) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 if ( !nestedsvm_vmcb_map(v, vmcbaddr) ) { gdprintk(XENLOG_ERR, "VMRUN: mapping vmcb failed, injecting #GP\n"= ); - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return; } =20 @@ -2343,7 +2343,7 @@ svm_vmexit_do_vmload(struct vmcb_struct *vmcb, =20 if ( !nsvm_efer_svm_enabled(v) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 @@ -2352,7 +2352,7 @@ svm_vmexit_do_vmload(struct vmcb_struct *vmcb, { gdprintk(XENLOG_ERR, "VMLOAD: mapping failed, injecting #GP\n"); - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return; } =20 @@ -2378,7 +2378,7 @@ svm_vmexit_do_vmsave(struct vmcb_struct *vmcb, =20 if ( !nsvm_efer_svm_enabled(v) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 @@ -2387,7 +2387,7 @@ svm_vmexit_do_vmsave(struct vmcb_struct *vmcb, { gdprintk(XENLOG_ERR, "VMSAVE: mapping vmcb failed, injecting #GP\n"); - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return; } =20 @@ -2777,7 +2777,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) if ( rc < 0 ) goto unexpected_exit_type; if ( !rc ) - hvm_inject_exception(TRAP_debug, + hvm_inject_exception(X86_EXC_DB, trap_type, insn_len, X86_EVENT_NO_EC); } else @@ -2794,7 +2794,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) { /* AMD Vol2, 15.11: INT3, INTO, BOUND intercepts do not update= RIP. */ __update_guest_eip(regs, insn_len); - current->arch.gdbsx_vcpu_event =3D TRAP_int3; + current->arch.gdbsx_vcpu_event =3D X86_EXC_BP; domain_pause_for_debugger(); } else @@ -2806,7 +2806,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) if ( rc < 0 ) goto unexpected_exit_type; if ( !rc ) - hvm_inject_exception(TRAP_int3, + hvm_inject_exception(X86_EXC_BP, X86_EVENTTYPE_SW_EXCEPTION, insn_len, X86_EVENT_NO_EC); } @@ -2847,8 +2847,8 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) } =20 case VMEXIT_EXCEPTION_AC: - HVMTRACE_1D(TRAP, TRAP_alignment_check); - hvm_inject_hw_exception(TRAP_alignment_check, vmcb->exitinfo1); + HVMTRACE_1D(TRAP, X86_EXC_AC); + hvm_inject_hw_exception(X86_EXC_AC, vmcb->exitinfo1); break; =20 case VMEXIT_EXCEPTION_UD: @@ -2901,8 +2901,8 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) * semantics. */ case X86_EVENTTYPE_HW_EXCEPTION: - if ( vmcb->exit_int_info.vector =3D=3D TRAP_int3 || - vmcb->exit_int_info.vector =3D=3D TRAP_overflow ) + if ( vmcb->exit_int_info.vector =3D=3D X86_EXC_BP || + vmcb->exit_int_info.vector =3D=3D X86_EXC_OF ) break; /* Fallthrough */ case X86_EVENTTYPE_EXT_INTR: @@ -2958,7 +2958,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) __update_guest_eip(regs, vmcb->exitinfo2 - vmcb->rip); } else if ( !hvm_emulate_one_insn(x86_insn_is_portio, "port I/O") ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); break; =20 case VMEXIT_CR0_READ ... VMEXIT_CR15_READ: @@ -2966,7 +2966,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) if ( cpu_has_svm_decode && (vmcb->exitinfo1 & (1ULL << 63)) ) svm_vmexit_do_cr_access(vmcb, regs); else if ( !hvm_emulate_one_insn(x86_insn_is_cr_access, "CR access"= ) ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); break; =20 case VMEXIT_INVLPG: @@ -2976,13 +2976,13 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) __update_guest_eip(regs, vmcb->nextrip - vmcb->rip); } else if ( !hvm_emulate_one_insn(is_invlpg, "invlpg") ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); break; =20 case VMEXIT_INVLPGA: if ( !nsvm_efer_svm_enabled(v) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); break; } if ( (insn_len =3D svm_get_insn_len(v, INSTR_INVLPGA)) =3D=3D 0 ) @@ -3023,7 +3023,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) case VMEXIT_MWAIT: case VMEXIT_SKINIT: case VMEXIT_RDPRU: - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); break; =20 case VMEXIT_VMRUN: @@ -3044,7 +3044,7 @@ void svm_vmexit_handler(struct cpu_user_regs *regs) =20 case VMEXIT_XSETBV: if ( vmcb_get_cpl(vmcb) ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); else if ( (insn_len =3D svm_get_insn_len(v, INSTR_XSETBV)) && hvm_handle_xsetbv(regs->ecx, msr_fold(regs)) =3D=3D X86E= MUL_OKAY ) __update_guest_eip(regs, insn_len); diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index 305d4767e387..ba06acf2ee99 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -140,7 +140,7 @@ static int construct_vmcb(struct vcpu *v) =20 vmcb->_exception_intercepts =3D HVM_TRAP_MASK | - (v->arch.fully_eager_fpu ? 0 : (1U << TRAP_no_device)); + (v->arch.fully_eager_fpu ? 0 : (1U << X86_EXC_NM)); =20 if ( paging_mode_hap(v->domain) ) { @@ -164,7 +164,7 @@ static int construct_vmcb(struct vcpu *v) } else { - vmcb->_exception_intercepts |=3D (1U << TRAP_page_fault); + vmcb->_exception_intercepts |=3D (1U << X86_EXC_PF); } =20 if ( cpu_has_pause_filter ) diff --git a/xen/arch/x86/hvm/vm_event.c b/xen/arch/x86/hvm/vm_event.c index 19aac19bc354..3b064bcfade5 100644 --- a/xen/arch/x86/hvm/vm_event.c +++ b/xen/arch/x86/hvm/vm_event.c @@ -87,7 +87,7 @@ void hvm_vm_event_do_resume(struct vcpu *v) VM_EVENT_FLAG_SET_EMUL_INSN_DATA ) kind =3D EMUL_KIND_SET_CONTEXT_INSN; =20 - hvm_emulate_one_vm_event(kind, TRAP_invalid_op, + hvm_emulate_one_vm_event(kind, X86_EXC_UD, X86_EVENT_NO_EC); =20 v->arch.vm_event->emulate_flags =3D 0; @@ -96,7 +96,7 @@ void hvm_vm_event_do_resume(struct vcpu *v) if ( unlikely(w->do_write.cr0) ) { if ( hvm_set_cr0(w->cr0, false) =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 w->do_write.cr0 =3D 0; } @@ -104,7 +104,7 @@ void hvm_vm_event_do_resume(struct vcpu *v) if ( unlikely(w->do_write.cr4) ) { if ( hvm_set_cr4(w->cr4, false) =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 w->do_write.cr4 =3D 0; } @@ -112,7 +112,7 @@ void hvm_vm_event_do_resume(struct vcpu *v) if ( unlikely(w->do_write.cr3) ) { if ( hvm_set_cr3(w->cr3, w->cr3_noflush, false) =3D=3D X86EMUL_EXC= EPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 w->do_write.cr3 =3D 0; } @@ -121,7 +121,7 @@ void hvm_vm_event_do_resume(struct vcpu *v) { if ( hvm_msr_write_intercept(w->msr, w->value, false) =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 w->do_write.msr =3D 0; } diff --git a/xen/arch/x86/hvm/vmx/intr.c b/xen/arch/x86/hvm/vmx/intr.c index 6a8316de0e25..87fb537b7c05 100644 --- a/xen/arch/x86/hvm/vmx/intr.c +++ b/xen/arch/x86/hvm/vmx/intr.c @@ -328,7 +328,7 @@ void vmx_intr_assist(void) } else if ( intack.source =3D=3D hvm_intsrc_mce ) { - hvm_inject_hw_exception(TRAP_machine_check, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_MC, X86_EVENT_NO_EC); } else if ( cpu_has_vmx_virtual_intr_delivery && intack.source !=3D hvm_intsrc_pic && diff --git a/xen/arch/x86/hvm/vmx/realmode.c b/xen/arch/x86/hvm/vmx/realmod= e.c index 4ac93e081015..ff44ddcfa627 100644 --- a/xen/arch/x86/hvm/vmx/realmode.c +++ b/xen/arch/x86/hvm/vmx/realmode.c @@ -48,21 +48,21 @@ static void realmode_deliver_exception( if ( insn_len !=3D 0 ) { insn_len =3D 0; - vector =3D TRAP_gp_fault; + vector =3D X86_EXC_GP; goto again; } =20 /* Exception or hardware interrupt. */ switch ( vector ) { - case TRAP_double_fault: + case X86_EXC_DF: hvm_triple_fault(); return; - case TRAP_gp_fault: - vector =3D TRAP_double_fault; + case X86_EXC_GP: + vector =3D X86_EXC_DF; goto again; default: - vector =3D TRAP_gp_fault; + vector =3D X86_EXC_GP; goto again; } } @@ -116,14 +116,14 @@ void vmx_realmode_emulate_one(struct hvm_emulate_ctxt= *hvmemul_ctxt) if ( curr->arch.hvm.guest_cr[0] & X86_CR0_PE ) goto fail; =20 - realmode_deliver_exception(TRAP_invalid_op, 0, hvmemul_ctxt); + realmode_deliver_exception(X86_EXC_UD, 0, hvmemul_ctxt); } =20 if ( rc =3D=3D X86EMUL_EXCEPTION ) { if ( unlikely(curr->domain->debugger_attached) && - ((hvmemul_ctxt->ctxt.event.vector =3D=3D TRAP_debug) || - (hvmemul_ctxt->ctxt.event.vector =3D=3D TRAP_int3)) ) + ((hvmemul_ctxt->ctxt.event.vector =3D=3D X86_EXC_DB) || + (hvmemul_ctxt->ctxt.event.vector =3D=3D X86_EXC_BP)) ) { domain_pause_for_debugger(); } diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index e1c268789e7e..dbf7d3bef6a9 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1293,8 +1293,8 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(VMCS_LINK_POINTER, ~0UL); =20 v->arch.hvm.vmx.exception_bitmap =3D HVM_TRAP_MASK - | (paging_mode_hap(d) ? 0 : (1U << TRAP_page_fault)) - | (v->arch.fully_eager_fpu ? 0 : (1U << TRAP_no_device)); + | (paging_mode_hap(d) ? 0 : (1U << X86_EXC_PF)) + | (v->arch.fully_eager_fpu ? 0 : (1U << X86_EXC_NM)); =20 if ( cpu_has_vmx_notify_vm_exiting ) __vmwrite(NOTIFY_WINDOW, vm_notify_window); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 0ec33bcc184b..7f1ccc2b4c68 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -789,9 +789,9 @@ static void cf_check vmx_cpuid_policy_changed(struct vc= pu *v) =20 if ( opt_hvm_fep || (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor)= ) - v->arch.hvm.vmx.exception_bitmap |=3D (1U << TRAP_invalid_op); + v->arch.hvm.vmx.exception_bitmap |=3D (1U << X86_EXC_UD); else - v->arch.hvm.vmx.exception_bitmap &=3D ~(1U << TRAP_invalid_op); + v->arch.hvm.vmx.exception_bitmap &=3D ~(1U << X86_EXC_UD); =20 vmx_vmcs_enter(v); vmx_update_exception_bitmap(v); @@ -1071,7 +1071,7 @@ static int cf_check vmx_load_vmcs_ctxt(struct vcpu *v= , struct hvm_hw_cpu *ctxt) static void vmx_fpu_enter(struct vcpu *v) { vcpu_restore_fpu_lazy(v); - v->arch.hvm.vmx.exception_bitmap &=3D ~(1u << TRAP_no_device); + v->arch.hvm.vmx.exception_bitmap &=3D ~(1u << X86_EXC_NM); vmx_update_exception_bitmap(v); v->arch.hvm.vmx.host_cr0 &=3D ~X86_CR0_TS; __vmwrite(HOST_CR0, v->arch.hvm.vmx.host_cr0); @@ -1098,7 +1098,7 @@ static void cf_check vmx_fpu_leave(struct vcpu *v) { v->arch.hvm.hw_cr[0] |=3D X86_CR0_TS; __vmwrite(GUEST_CR0, v->arch.hvm.hw_cr[0]); - v->arch.hvm.vmx.exception_bitmap |=3D (1u << TRAP_no_device); + v->arch.hvm.vmx.exception_bitmap |=3D (1u << X86_EXC_NM); vmx_update_exception_bitmap(v); } } @@ -1616,9 +1616,9 @@ static void cf_check vmx_update_host_cr3(struct vcpu = *v) void vmx_update_debug_state(struct vcpu *v) { if ( v->arch.hvm.debug_state_latch ) - v->arch.hvm.vmx.exception_bitmap |=3D 1U << TRAP_int3; + v->arch.hvm.vmx.exception_bitmap |=3D 1U << X86_EXC_BP; else - v->arch.hvm.vmx.exception_bitmap &=3D ~(1U << TRAP_int3); + v->arch.hvm.vmx.exception_bitmap &=3D ~(1U << X86_EXC_BP); =20 vmx_vmcs_enter(v); vmx_update_exception_bitmap(v); @@ -2000,7 +2000,7 @@ void vmx_inject_nmi(void) nvmx_enqueue_n2_exceptions (v,=20 INTR_INFO_VALID_MASK | MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK) | - MASK_INSR(TRAP_nmi, INTR_INFO_VECTOR_MASK), + MASK_INSR(X86_EXC_NMI, INTR_INFO_VECTOR_MASK), X86_EVENT_NO_EC, hvm_intsrc_nmi); return; } @@ -2025,14 +2025,14 @@ static void cf_check vmx_inject_event(const struct = x86_event *event) =20 switch ( _event.vector | -(_event.type =3D=3D X86_EVENTTYPE_SW_INTERRU= PT) ) { - case TRAP_debug: + case X86_EXC_DB: if ( guest_cpu_user_regs()->eflags & X86_EFLAGS_TF ) { __restore_debug_registers(curr); write_debugreg(6, read_debugreg(6) | DR_STEP); } if ( !nestedhvm_vcpu_in_guestmode(curr) || - !nvmx_intercepts_exception(curr, TRAP_debug, _event.error_cod= e) ) + !nvmx_intercepts_exception(curr, X86_EXC_DB, _event.error_cod= e) ) { unsigned long val; =20 @@ -2044,7 +2044,7 @@ static void cf_check vmx_inject_event(const struct x8= 6_event *event) if ( cpu_has_monitor_trap_flag ) break; /* fall through */ - case TRAP_int3: + case X86_EXC_BP: if ( curr->domain->debugger_attached ) { /* Debug/Int3: Trap to debugger. */ @@ -2053,7 +2053,7 @@ static void cf_check vmx_inject_event(const struct x8= 6_event *event) } break; =20 - case TRAP_page_fault: + case X86_EXC_PF: ASSERT(_event.type =3D=3D X86_EVENTTYPE_HW_EXCEPTION); curr->arch.hvm.guest_cr[2] =3D _event.cr2; break; @@ -2070,7 +2070,7 @@ static void cf_check vmx_inject_event(const struct x8= 6_event *event) { _event.vector =3D hvm_combine_hw_exceptions( (uint8_t)intr_info, _event.vector); - if ( _event.vector =3D=3D TRAP_double_fault ) + if ( _event.vector =3D=3D X86_EXC_DF ) _event.error_code =3D 0; } =20 @@ -2090,7 +2090,7 @@ static void cf_check vmx_inject_event(const struct x8= 6_event *event) else __vmx_inject_exception(_event.vector, _event.type, _event.error_co= de); =20 - if ( (_event.vector =3D=3D TRAP_page_fault) && + if ( (_event.vector =3D=3D X86_EXC_PF) && (_event.type =3D=3D X86_EVENTTYPE_HW_EXCEPTION) ) HVMTRACE_LONG_2D(PF_INJECT, _event.error_code, TRC_PAR_LONG(curr->arch.hvm.guest_cr[2])); @@ -2445,7 +2445,7 @@ static bool cf_check vmx_vcpu_emulate_ve(struct vcpu = *v) __vmread(GUEST_PHYSICAL_ADDRESS, &veinfo->gpa); vmx_vmcs_exit(v); =20 - hvm_inject_hw_exception(TRAP_virtualisation, + hvm_inject_hw_exception(X86_EXC_VE, X86_EVENT_NO_EC); =20 out: @@ -3077,7 +3077,7 @@ void update_guest_eip(void) } =20 if ( regs->eflags & X86_EFLAGS_TF ) - hvm_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } =20 static void cf_check vmx_fpu_dirty_intercept(void) @@ -3175,7 +3175,7 @@ static int vmx_cr_access(cr_access_qual_t qual) HVMTRACE_LONG_1D(LMSW, value); =20 if ( (rc =3D hvm_set_cr0(value, true)) =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 return rc; } @@ -4093,9 +4093,9 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) __vmread(VM_EXIT_INTR_INFO, &intr_info); BUG_ON(!(intr_info & INTR_INFO_VALID_MASK)); vector =3D intr_info & INTR_INFO_VECTOR_MASK; - if ( vector =3D=3D TRAP_machine_check ) + if ( vector =3D=3D X86_EXC_MC ) do_machine_check(regs); - if ( (vector =3D=3D TRAP_nmi) && + if ( (vector =3D=3D X86_EXC_NMI) && ((intr_info & INTR_INFO_INTR_TYPE_MASK) =3D=3D MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK)) ) { @@ -4192,9 +4192,8 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) switch ( exit_reason ) { case EXIT_REASON_EXCEPTION_NMI: - if ( vector !=3D TRAP_page_fault - && vector !=3D TRAP_nmi=20 - && vector !=3D TRAP_machine_check )=20 + if ( vector !=3D X86_EXC_PF && vector !=3D X86_EXC_NMI && + vector !=3D X86_EXC_MC ) { default: perfc_incr(realmode_exits); @@ -4243,14 +4242,14 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) */ if ( unlikely(intr_info & INTR_INFO_NMI_UNBLOCKED_BY_IRET) && !(idtv_info & INTR_INFO_VALID_MASK) && - (vector !=3D TRAP_double_fault) ) + (vector !=3D X86_EXC_DF) ) undo_nmis_unblocked_by_iret(); =20 perfc_incra(cause_vector, vector); =20 switch ( vector ) { - case TRAP_debug: + case X86_EXC_DB: /* * Updates DR6 where debugger can peek (See 3B 23.2.1, * Table 23-1, "Exit Qualification for Debug Exceptions"). @@ -4317,7 +4316,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) else domain_pause_for_debugger(); break; - case TRAP_int3: + case X86_EXC_BP: HVMTRACE_1D(TRAP, vector); if ( !v->domain->debugger_attached ) { @@ -4338,15 +4337,15 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) else { update_guest_eip(); /* Safe: INT3 */ - v->arch.gdbsx_vcpu_event =3D TRAP_int3; + v->arch.gdbsx_vcpu_event =3D X86_EXC_BP; domain_pause_for_debugger(); } break; - case TRAP_no_device: + case X86_EXC_NM: HVMTRACE_1D(TRAP, vector); vmx_fpu_dirty_intercept(); break; - case TRAP_page_fault: + case X86_EXC_PF: __vmread(EXIT_QUALIFICATION, &exit_qualification); __vmread(VM_EXIT_INTR_ERROR_CODE, &ecode); regs->error_code =3D ecode; @@ -4371,22 +4370,22 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) =20 hvm_inject_page_fault(regs->error_code, exit_qualification); break; - case TRAP_alignment_check: + case X86_EXC_AC: HVMTRACE_1D(TRAP, vector); vmx_propagate_intr(intr_info); break; - case TRAP_nmi: + case X86_EXC_NMI: if ( MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK) !=3D X86_EVENTTYPE_NMI ) goto exit_and_crash; HVMTRACE_0D(NMI); /* Already handled above. */ break; - case TRAP_machine_check: + case X86_EXC_MC: HVMTRACE_0D(MCE); /* Already handled above. */ break; - case TRAP_invalid_op: + case X86_EXC_UD: HVMTRACE_1D(TRAP, vector); hvm_ud_intercept(regs); break; @@ -4467,7 +4466,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) case EXIT_REASON_RDTSCP: if ( !currd->arch.cpuid->extd.rdtscp ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); break; } =20 @@ -4508,7 +4507,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) break; =20 case X86EMUL_EXCEPTION: - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); break; } break; @@ -4522,7 +4521,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) break; =20 case X86EMUL_EXCEPTION: - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); break; } break; @@ -4544,7 +4543,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) =20 case EXIT_REASON_VMFUNC: if ( vmx_vmfunc_intercept(regs) !=3D X86EMUL_OKAY ) - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); else update_guest_eip(); break; @@ -4558,7 +4557,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) * as far as vmexit. */ WARN_ON(exit_reason =3D=3D EXIT_REASON_GETSEC); - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); break; =20 case EXIT_REASON_TPR_BELOW_THRESHOLD: @@ -4566,7 +4565,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) =20 case EXIT_REASON_APIC_ACCESS: if ( !vmx_handle_eoi_write() && !handle_mmio() ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); break; =20 case EXIT_REASON_EOI_INDUCED: @@ -4583,7 +4582,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) { /* INS, OUTS */ if ( !hvm_emulate_one_insn(x86_insn_is_portio, "port I/O") ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); } else { @@ -4714,7 +4713,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) gprintk(XENLOG_ERR, "Unexpected vmexit: reason %lu\n", exit_reason= ); =20 if ( vmx_get_cpl() ) - hvm_inject_hw_exception(TRAP_invalid_op, + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); else domain_crash(v->domain); @@ -4745,7 +4744,7 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) { __vmread(VM_ENTRY_INTR_INFO, &intr_info); if ( !(intr_info & INTR_INFO_VALID_MASK) ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); /* Need to fix rIP nevertheless. */ if ( mode =3D=3D 8 ) regs->rip =3D (long)(regs->rip << (64 - VADDR_BITS)) >> diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 674cdabb0736..27221fdb733b 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -474,7 +474,7 @@ static int decode_vmx_inst(struct cpu_user_regs *regs, return X86EMUL_OKAY; =20 gp_fault: - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return X86EMUL_EXCEPTION; } =20 @@ -526,7 +526,7 @@ bool cf_check nvmx_intercepts_exception( exception_bitmap =3D get_vvmcs(v, EXCEPTION_BITMAP); r =3D exception_bitmap & (1 << vector) ? 1: 0; =20 - if ( vector =3D=3D TRAP_page_fault ) + if ( vector =3D=3D X86_EXC_PF ) { pfec_match =3D get_vvmcs(v, PAGE_FAULT_ERROR_CODE_MATCH); pfec_mask =3D get_vvmcs(v, PAGE_FAULT_ERROR_CODE_MASK); @@ -1100,15 +1100,15 @@ static void load_shadow_guest_state(struct vcpu *v) =20 rc =3D hvm_set_cr4(get_vvmcs(v, GUEST_CR4), true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 rc =3D hvm_set_cr0(get_vvmcs(v, GUEST_CR0), true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 rc =3D hvm_set_cr3(get_vvmcs(v, GUEST_CR3), false, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 control =3D get_vvmcs(v, VM_ENTRY_CONTROLS); if ( control & VM_ENTRY_LOAD_GUEST_PAT ) @@ -1118,7 +1118,7 @@ static void load_shadow_guest_state(struct vcpu *v) rc =3D hvm_msr_write_intercept(MSR_CORE_PERF_GLOBAL_CTRL, get_vvmcs(v, GUEST_PERF_GLOBAL_CTRL),= false); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); } =20 hvm_set_tsc_offset(v, v->arch.hvm.cache_tsc_offset, 0); @@ -1314,15 +1314,15 @@ static void load_vvmcs_host_state(struct vcpu *v) =20 rc =3D hvm_set_cr4(get_vvmcs(v, HOST_CR4), true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 rc =3D hvm_set_cr0(get_vvmcs(v, HOST_CR0), true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 rc =3D hvm_set_cr3(get_vvmcs(v, HOST_CR3), false, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); =20 control =3D get_vvmcs(v, VM_EXIT_CONTROLS); if ( control & VM_EXIT_LOAD_HOST_PAT ) @@ -1332,7 +1332,7 @@ static void load_vvmcs_host_state(struct vcpu *v) rc =3D hvm_msr_write_intercept(MSR_CORE_PERF_GLOBAL_CTRL, get_vvmcs(v, HOST_PERF_GLOBAL_CTRL), = true); if ( rc =3D=3D X86EMUL_EXCEPTION ) - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); } =20 hvm_set_tsc_offset(v, v->arch.hvm.cache_tsc_offset, 0); @@ -2083,13 +2083,13 @@ int nvmx_handle_vmx_insn(struct cpu_user_regs *regs= , unsigned int exit_reason) (vmx_guest_x86_mode(curr) < (hvm_long_mode_active(curr) ? 8 : 2))= || (exit_reason !=3D EXIT_REASON_VMXON && !nvmx_vcpu_in_vmx(curr)) ) { - hvm_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return X86EMUL_EXCEPTION; } =20 if ( vmx_get_cpl() > 0 ) { - hvm_inject_hw_exception(TRAP_gp_fault, 0); + hvm_inject_hw_exception(X86_EXC_GP, 0); return X86EMUL_EXCEPTION; } =20 @@ -2464,12 +2464,12 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *re= gs, * decided by L0 and L1 exception bitmap, if the vetor is set by * both, L0 has priority on #PF and #NM, L1 has priority on others */ - if ( vector =3D=3D TRAP_page_fault ) + if ( vector =3D=3D X86_EXC_PF ) { if ( paging_mode_hap(v->domain) ) nvcpu->nv_vmexit_pending =3D 1; } - else if ( vector =3D=3D TRAP_no_device ) + else if ( vector =3D=3D X86_EXC_NM ) { if ( v->fpu_dirtied ) nvcpu->nv_vmexit_pending =3D 1; diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index b5354c367750..296a1ee79127 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -722,7 +722,7 @@ static inline void pv_inject_hw_exception(unsigned int = vector, int errcode) static inline void pv_inject_page_fault(int errcode, unsigned long cr2) { const struct x86_event event =3D { - .vector =3D TRAP_page_fault, + .vector =3D X86_EXC_PF, .type =3D X86_EVENTTYPE_HW_EXCEPTION, .error_code =3D errcode, .cr2 =3D cr2, diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 43d3fc249887..258e0a1f2931 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -540,7 +540,7 @@ static inline void hvm_inject_hw_exception(unsigned int= vector, int errcode) static inline void hvm_inject_page_fault(int errcode, unsigned long cr2) { struct x86_event event =3D { - .vector =3D TRAP_page_fault, + .vector =3D X86_EXC_PF, .type =3D X86_EVENTTYPE_HW_EXCEPTION, .error_code =3D errcode, .cr2 =3D cr2, @@ -564,9 +564,9 @@ static inline void hvm_invlpg(struct vcpu *v, unsigned = long linear) (X86_CR4_VMXE | X86_CR4_PAE | X86_CR4_MCE)) =20 /* These exceptions must always be intercepted. */ -#define HVM_TRAP_MASK ((1U << TRAP_debug) | \ - (1U << TRAP_alignment_check) | \ - (1U << TRAP_machine_check)) +#define HVM_TRAP_MASK ((1U << X86_EXC_DB) | \ + (1U << X86_EXC_AC) | \ + (1U << X86_EXC_MC)) =20 /* Called in boot/resume paths. Must cope with no HVM support. */ static inline int hvm_cpu_up(void) diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/as= m/processor.h index 8725e0df11e9..2095d9a4e28d 100644 --- a/xen/arch/x86/include/asm/processor.h +++ b/xen/arch/x86/include/asm/processor.h @@ -17,34 +17,6 @@ #include #include =20 -/* - * Trap/fault mnemonics. - */ -#define TRAP_divide_error 0 -#define TRAP_debug 1 -#define TRAP_nmi 2 -#define TRAP_int3 3 -#define TRAP_overflow 4 -#define TRAP_bounds 5 -#define TRAP_invalid_op 6 -#define TRAP_no_device 7 -#define TRAP_double_fault 8 -#define TRAP_copro_seg 9 -#define TRAP_invalid_tss 10 -#define TRAP_no_segment 11 -#define TRAP_stack_error 12 -#define TRAP_gp_fault 13 -#define TRAP_page_fault 14 -#define TRAP_spurious_int 15 -#define TRAP_copro_error 16 -#define TRAP_alignment_check 17 -#define TRAP_machine_check 18 -#define TRAP_simd_error 19 -#define TRAP_virtualisation 20 -#define TRAP_nr 32 - -#define TRAP_HAVE_EC X86_EXC_HAVE_EC - /* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ= . */ /* NB. Same as VGCF_in_syscall. No bits in common with any other TRAP_ def= n. */ #define TRAP_syscall 256 @@ -431,18 +403,18 @@ static inline void set_ist(idt_entry_t *idt, unsigned= int ist) =20 static inline void enable_each_ist(idt_entry_t *idt) { - set_ist(&idt[TRAP_double_fault], IST_DF); - set_ist(&idt[TRAP_nmi], IST_NMI); - set_ist(&idt[TRAP_machine_check], IST_MCE); - set_ist(&idt[TRAP_debug], IST_DB); + set_ist(&idt[X86_EXC_DF], IST_DF); + set_ist(&idt[X86_EXC_NMI], IST_NMI); + set_ist(&idt[X86_EXC_MC], IST_MCE); + set_ist(&idt[X86_EXC_DB], IST_DB); } =20 static inline void disable_each_ist(idt_entry_t *idt) { - set_ist(&idt[TRAP_double_fault], IST_NONE); - set_ist(&idt[TRAP_nmi], IST_NONE); - set_ist(&idt[TRAP_machine_check], IST_NONE); - set_ist(&idt[TRAP_debug], IST_NONE); + set_ist(&idt[X86_EXC_DF], IST_NONE); + set_ist(&idt[X86_EXC_NMI], IST_NONE); + set_ist(&idt[X86_EXC_MC], IST_NONE); + set_ist(&idt[X86_EXC_DB], IST_NONE); } =20 #define IDT_ENTRIES 256 diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/as= m/x86-defns.h index fe1caba6f819..e350227e57eb 100644 --- a/xen/arch/x86/include/asm/x86-defns.h +++ b/xen/arch/x86/include/asm/x86-defns.h @@ -147,6 +147,8 @@ #define X86_EXC_VC 29 /* VMM Communication */ #define X86_EXC_SX 30 /* Security Exception */ =20 +#define X86_EXC_NUM 32 /* 32 reserved vectors */ + /* Bitmap of exceptions which have error codes. */ #define X86_EXC_HAVE_EC \ ((1u << X86_EXC_DF) | (1u << X86_EXC_TS) | (1u << X86_EXC_NP) | \ diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c index 1dd0c9aad802..d50772ad6ca3 100644 --- a/xen/arch/x86/machine_kexec.c +++ b/xen/arch/x86/machine_kexec.c @@ -170,7 +170,7 @@ void machine_kexec(struct kexec_image *image) { if ( idt_tables[i] =3D=3D NULL ) continue; - _update_gate_addr_lower(&idt_tables[i][TRAP_machine_check], &trap_= nop); + _update_gate_addr_lower(&idt_tables[i][X86_EXC_MC], &trap_nop); } =20 /* Reset CPUID masking and faulting to the host's default. */ diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 0fe14faa5fa7..8e6d000950f8 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -1232,7 +1232,7 @@ void put_page_from_l1e(l1_pgentry_t l1e, struct domai= n *l1e_owner) gprintk(XENLOG_WARNING, "Attempt to implicitly unmap %pd's grant PTE %" PRIpte "\n= ", l1e_owner, l1e_get_intpte(l1e)); - pv_inject_hw_exception(TRAP_gp_fault, 0); + pv_inject_hw_exception(X86_EXC_GP, 0); } #endif =20 diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index f3aed9fcc966..676d92297368 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -219,7 +219,7 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gl= a, npfec.kind =3D=3D npfec_kind_in_gpt ) { v->arch.vm_event->send_event =3D true; - hvm_emulate_one_vm_event(EMUL_KIND_NORMAL, TRAP_invalid_op, X86_EV= ENT_NO_EC); + hvm_emulate_one_vm_event(EMUL_KIND_NORMAL, X86_EXC_UD, X86_EVENT_N= O_EC); v->arch.vm_event->send_event =3D false; =20 return true; diff --git a/xen/arch/x86/mm/shadow/hvm.c b/xen/arch/x86/mm/shadow/hvm.c index 88c3c16322f2..1bc24e41ba12 100644 --- a/xen/arch/x86/mm/shadow/hvm.c +++ b/xen/arch/x86/mm/shadow/hvm.c @@ -98,7 +98,7 @@ static int hvm_translate_virtual_addr( */ if ( is_x86_user_segment(seg) ) x86_emul_hw_exception( - (seg =3D=3D x86_seg_ss) ? TRAP_stack_error : TRAP_gp_fault, + (seg =3D=3D x86_seg_ss) ? X86_EXC_SS : X86_EXC_GP, 0, &sh_ctxt->ctxt); return X86EMUL_EXCEPTION; } diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 5f3e175bbe03..252fede87d7f 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -2745,9 +2745,9 @@ static int cf_check sh_page_fault( * stream under Xen's feet. */ if ( emul_ctxt.ctxt.event.type =3D=3D X86_EVENTTYPE_HW_EXCEPTION && - ((emul_ctxt.ctxt.event.vector =3D=3D TRAP_page_fault) || - (((emul_ctxt.ctxt.event.vector =3D=3D TRAP_gp_fault) || - (emul_ctxt.ctxt.event.vector =3D=3D TRAP_stack_error)) && + ((emul_ctxt.ctxt.event.vector =3D=3D X86_EXC_PF) || + (((emul_ctxt.ctxt.event.vector =3D=3D X86_EXC_GP) || + (emul_ctxt.ctxt.event.vector =3D=3D X86_EXC_SS)) && emul_ctxt.ctxt.event.error_code =3D=3D 0)) ) hvm_inject_event(&emul_ctxt.ctxt.event); else @@ -2809,7 +2809,7 @@ static int cf_check sh_page_fault( #endif =20 if ( emul_ctxt.ctxt.retire.singlestep ) - hvm_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); =20 #if GUEST_PAGING_LEVELS =3D=3D 3 /* PAE guest */ /* @@ -2850,7 +2850,7 @@ static int cf_check sh_page_fault( TRACE_SHADOW_PATH_FLAG(TRCE_SFLAG_EMULATION_LAST_FAILED); =20 if ( emul_ctxt.ctxt.retire.singlestep ) - hvm_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); =20 break; /* Don't emulate again if we failed! */ } diff --git a/xen/arch/x86/pv/callback.c b/xen/arch/x86/pv/callback.c index 067ee3b795d0..ca3bc30e91ba 100644 --- a/xen/arch/x86/pv/callback.c +++ b/xen/arch/x86/pv/callback.c @@ -29,12 +29,12 @@ static int register_guest_nmi_callback(unsigned long ad= dress) { struct vcpu *curr =3D current; struct domain *d =3D curr->domain; - struct trap_info *t =3D &curr->arch.pv.trap_ctxt[TRAP_nmi]; + struct trap_info *t =3D &curr->arch.pv.trap_ctxt[X86_EXC_NMI]; =20 if ( !is_canonical_address(address) ) return -EINVAL; =20 - t->vector =3D TRAP_nmi; + t->vector =3D X86_EXC_NMI; t->flags =3D 0; t->cs =3D (is_pv_32bit_domain(d) ? FLAT_COMPAT_KERNEL_CS : FLAT_KERNEL_CS); @@ -54,7 +54,7 @@ static int register_guest_nmi_callback(unsigned long addr= ess) static void unregister_guest_nmi_callback(void) { struct vcpu *curr =3D current; - struct trap_info *t =3D &curr->arch.pv.trap_ctxt[TRAP_nmi]; + struct trap_info *t =3D &curr->arch.pv.trap_ctxt[X86_EXC_NMI]; =20 memset(t, 0, sizeof(*t)); } diff --git a/xen/arch/x86/pv/emul-gate-op.c b/xen/arch/x86/pv/emul-gate-op.c index 758a20ad9df4..9524982e7d2d 100644 --- a/xen/arch/x86/pv/emul-gate-op.c +++ b/xen/arch/x86/pv/emul-gate-op.c @@ -185,12 +185,12 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) (((ar >> 13) & 3) < (regs->cs & 3)) || ((ar & _SEGMENT_TYPE) !=3D 0xc00) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } if ( !(ar & _SEGMENT_P) ) { - pv_inject_hw_exception(TRAP_no_segment, regs->error_code); + pv_inject_hw_exception(X86_EXC_NP, regs->error_code); return; } dpl =3D (ar >> 13) & 3; @@ -206,7 +206,7 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) !(ar & _SEGMENT_P) || !(ar & _SEGMENT_CODE) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } =20 @@ -219,7 +219,7 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) if ( PTR_ERR(state) =3D=3D -X86EMUL_EXCEPTION ) pv_inject_event(&ctxt.ctxt.event); else - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } =20 @@ -268,7 +268,7 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) (opnd_sel & ~3) !=3D regs->error_code || dpl < (opnd_sel & 3) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } =20 @@ -279,17 +279,17 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) ((ar >> 13) & 3) > (regs->cs & 3) : ((ar >> 13) & 3) !=3D (regs->cs & 3)) ) { - pv_inject_hw_exception(TRAP_gp_fault, sel); + pv_inject_hw_exception(X86_EXC_GP, sel); return; } if ( !(ar & _SEGMENT_P) ) { - pv_inject_hw_exception(TRAP_no_segment, sel); + pv_inject_hw_exception(X86_EXC_NP, sel); return; } if ( off > limit ) { - pv_inject_hw_exception(TRAP_gp_fault, 0); + pv_inject_hw_exception(X86_EXC_GP, 0); return; } =20 @@ -316,7 +316,7 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) /* Inner stack known only for kernel ring. */ if ( (sel & 3) !=3D GUEST_KERNEL_RPL(v->domain) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } esp =3D v->arch.pv.kernel_sp; @@ -328,19 +328,19 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) (ar & _SEGMENT_CODE) || !(ar & _SEGMENT_WR) ) { - pv_inject_hw_exception(TRAP_invalid_tss, ss & ~3); + pv_inject_hw_exception(X86_EXC_TS, ss & ~3); return; } if ( !(ar & _SEGMENT_P) || !check_stack_limit(ar, limit, esp, (4 + nparm) * 4) ) { - pv_inject_hw_exception(TRAP_stack_error, ss & ~3); + pv_inject_hw_exception(X86_EXC_SS, ss & ~3); return; } stkp =3D (unsigned int *)(unsigned long)((unsigned int)base + = esp); if ( !compat_access_ok(stkp - 4 - nparm, 16 + nparm * 4) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } push(regs->ss); @@ -356,12 +356,12 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) (ar & _SEGMENT_CODE) || !(ar & _SEGMENT_WR) || !check_stack_limit(ar, limit, esp + nparm * 4, nparm = * 4) ) - return pv_inject_hw_exception(TRAP_gp_fault, regs->err= or_code); + return pv_inject_hw_exception(X86_EXC_GP, regs->error_= code); ustkp =3D (unsigned int *)(unsigned long) ((unsigned int)base + regs->esp + nparm * 4); if ( !compat_access_ok(ustkp - nparm, 0 + nparm * 4) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code= ); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } do @@ -387,18 +387,18 @@ void pv_emulate_gate_op(struct cpu_user_regs *regs) if ( !pv_emul_read_descriptor(ss, v, &base, &limit, &ar, 0) || ((ar >> 13) & 3) !=3D (sel & 3) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } if ( !check_stack_limit(ar, limit, esp, 2 * 4) ) { - pv_inject_hw_exception(TRAP_stack_error, 0); + pv_inject_hw_exception(X86_EXC_SS, 0); return; } stkp =3D (unsigned int *)(unsigned long)((unsigned int)base + = esp); if ( !compat_access_ok(stkp - 2, 2 * 4) ) { - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; } } diff --git a/xen/arch/x86/pv/emul-inv-op.c b/xen/arch/x86/pv/emul-inv-op.c index 2c07eed9a092..32eb34e1a291 100644 --- a/xen/arch/x86/pv/emul-inv-op.c +++ b/xen/arch/x86/pv/emul-inv-op.c @@ -57,7 +57,7 @@ static int emulate_forced_invalid_op(struct cpu_user_regs= *regs) !guest_kernel_mode(current, regs) ) { regs->rip =3D eip; - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return EXCRET_fault_fixed; } =20 diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 5da00e24e4ff..5ef8c184ed66 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -609,8 +609,7 @@ static int pv_emul_virt_to_linear(unsigned long base, u= nsigned long offset, rc =3D X86EMUL_EXCEPTION; =20 if ( unlikely(rc =3D=3D X86EMUL_EXCEPTION) ) - x86_emul_hw_exception(seg !=3D x86_seg_ss ? TRAP_gp_fault - : TRAP_stack_error, + x86_emul_hw_exception(seg !=3D x86_seg_ss ? X86_EXC_GP : X86_EXC_S= S, 0, ctxt); =20 return rc; @@ -645,7 +644,7 @@ static int cf_check rep_ins( (sreg.type & (_SEGMENT_CODE >> 8)) || !(sreg.type & (_SEGMENT_WR >> 8)) ) { - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); return X86EMUL_EXCEPTION; } =20 @@ -711,8 +710,7 @@ static int cf_check rep_outs( ((sreg.type & (_SEGMENT_CODE >> 8)) && !(sreg.type & (_SEGMENT_WR >> 8))) ) { - x86_emul_hw_exception(seg !=3D x86_seg_ss ? TRAP_gp_fault - : TRAP_stack_error, + x86_emul_hw_exception(seg !=3D x86_seg_ss ? X86_EXC_GP : X86_EXC_S= S, 0, ctxt); return X86EMUL_EXCEPTION; } @@ -893,7 +891,7 @@ static int cf_check read_msr( if ( (ret =3D guest_rdmsr(curr, reg, val)) !=3D X86EMUL_UNHANDLEABLE ) { if ( ret =3D=3D X86EMUL_EXCEPTION ) - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); =20 goto done; } @@ -1041,7 +1039,7 @@ static int cf_check write_msr( if ( (ret =3D guest_wrmsr(curr, reg, val)) !=3D X86EMUL_UNHANDLEABLE ) { if ( ret =3D=3D X86EMUL_EXCEPTION ) - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); =20 return ret; } @@ -1376,7 +1374,7 @@ int pv_emulate_privileged_op(struct cpu_user_regs *re= gs) { curr->arch.dr6 |=3D ctxt.bpmatch | DR_STATUS_RESERVED_ONE; if ( !(curr->arch.pv.trap_bounce.flags & TBF_EXCEPTION) ) - pv_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } /* fall through */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/emulate.c b/xen/arch/x86/pv/emulate.c index 0a7907ec5e84..2eff77c577e5 100644 --- a/xen/arch/x86/pv/emulate.c +++ b/xen/arch/x86/pv/emulate.c @@ -86,7 +86,7 @@ void pv_emul_instruction_done(struct cpu_user_regs *regs,= unsigned long rip) if ( regs->eflags & X86_EFLAGS_TF ) { current->arch.dr6 |=3D DR_STEP | DR_STATUS_RESERVED_ONE; - pv_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } } =20 diff --git a/xen/arch/x86/pv/iret.c b/xen/arch/x86/pv/iret.c index 316a23e77eb7..d3a1fb2c685b 100644 --- a/xen/arch/x86/pv/iret.c +++ b/xen/arch/x86/pv/iret.c @@ -186,7 +186,7 @@ int compat_iret(void) regs->esp =3D ksp; regs->ss =3D v->arch.pv.kernel_ss; =20 - ti =3D &v->arch.pv.trap_ctxt[TRAP_gp_fault]; + ti =3D &v->arch.pv.trap_ctxt[X86_EXC_GP]; if ( TI_GET_IF(ti) ) eflags &=3D ~X86_EFLAGS_IF; regs->eflags &=3D ~(X86_EFLAGS_VM|X86_EFLAGS_RF| diff --git a/xen/arch/x86/pv/ro-page-fault.c b/xen/arch/x86/pv/ro-page-faul= t.c index 5963f5ee2d51..d1fdbff0e909 100644 --- a/xen/arch/x86/pv/ro-page-fault.c +++ b/xen/arch/x86/pv/ro-page-fault.c @@ -390,7 +390,7 @@ int pv_ro_page_fault(unsigned long addr, struct cpu_use= r_regs *regs) * or a guest playing with the instruction stream under Xen's feet. */ if ( ctxt.event.type =3D=3D X86_EVENTTYPE_HW_EXCEPTION && - ctxt.event.vector =3D=3D TRAP_page_fault ) + ctxt.event.vector =3D=3D X86_EXC_PF ) pv_inject_event(&ctxt.event); else gdprintk(XENLOG_WARNING, @@ -400,7 +400,7 @@ int pv_ro_page_fault(unsigned long addr, struct cpu_use= r_regs *regs) /* Fallthrough */ case X86EMUL_OKAY: if ( ctxt.retire.singlestep ) - pv_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); =20 /* Fallthrough */ case X86EMUL_RETRY: diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c index 21f4860f7832..e3e030a5051b 100644 --- a/xen/arch/x86/pv/traps.c +++ b/xen/arch/x86/pv/traps.c @@ -43,7 +43,7 @@ void pv_inject_event(const struct x86_event *event) if ( event->type =3D=3D X86_EVENTTYPE_HW_EXCEPTION ) { ASSERT(vector < 32); - use_error_code =3D TRAP_HAVE_EC & (1u << vector); + use_error_code =3D X86_EXC_HAVE_EC & (1u << vector); } else { @@ -63,7 +63,7 @@ void pv_inject_event(const struct x86_event *event) tb->eip =3D ti->address; =20 if ( event->type =3D=3D X86_EVENTTYPE_HW_EXCEPTION && - vector =3D=3D TRAP_page_fault ) + vector =3D=3D X86_EXC_PF ) { curr->arch.pv.ctrlreg[2] =3D event->cr2; arch_set_cr2(curr, event->cr2); @@ -93,7 +93,7 @@ void pv_inject_event(const struct x86_event *event) "Unhandled: vec %u, %s[%04x]\n", vector, vector_name(vector), error_code); =20 - if ( vector =3D=3D TRAP_page_fault ) + if ( vector =3D=3D X86_EXC_PF ) show_page_walk(event->cr2); } } @@ -107,7 +107,7 @@ bool set_guest_machinecheck_trapbounce(void) struct vcpu *curr =3D current; struct trap_bounce *tb =3D &curr->arch.pv.trap_bounce; =20 - pv_inject_hw_exception(TRAP_machine_check, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_MC, X86_EVENT_NO_EC); tb->flags &=3D ~TBF_EXCEPTION; /* not needed for MCE delivery path */ =20 return !null_trap_bounce(curr, tb); @@ -122,7 +122,7 @@ bool set_guest_nmi_trapbounce(void) struct vcpu *curr =3D current; struct trap_bounce *tb =3D &curr->arch.pv.trap_bounce; =20 - pv_inject_hw_exception(TRAP_nmi, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_NMI, X86_EVENT_NO_EC); tb->flags &=3D ~TBF_EXCEPTION; /* not needed for NMI delivery path */ =20 return !null_trap_bounce(curr, tb); diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index bfd335777177..25a0c666cc14 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -805,7 +805,7 @@ void fatal_trap(const struct cpu_user_regs *regs, bool = show_remote) =20 show_execution_state(regs); =20 - if ( trapnr =3D=3D TRAP_page_fault ) + if ( trapnr =3D=3D X86_EXC_PF ) show_page_walk(read_cr2()); =20 if ( show_remote ) @@ -944,7 +944,7 @@ void do_trap(struct cpu_user_regs *regs) if ( guest_mode(regs) ) { pv_inject_hw_exception(trapnr, - (TRAP_HAVE_EC & (1u << trapnr)) + (X86_EXC_HAVE_EC & (1u << trapnr)) ? regs->error_code : X86_EVENT_NO_EC); return; } @@ -1176,7 +1176,7 @@ void do_invalid_op(struct cpu_user_regs *regs) if ( likely(guest_mode(regs)) ) { if ( pv_emulate_invalid_op(regs) ) - pv_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); return; } =20 @@ -1241,7 +1241,7 @@ void do_invalid_op(struct cpu_user_regs *regs) case BUGFRAME_bug: printk("Xen BUG at %s%s:%d\n", prefix, filename, lineno); =20 - if ( debugger_trap_fatal(TRAP_invalid_op, regs) ) + if ( debugger_trap_fatal(X86_EXC_UD, regs) ) return; =20 show_execution_state(regs); @@ -1256,7 +1256,7 @@ void do_invalid_op(struct cpu_user_regs *regs) printk("Assertion '%s' failed at %s%s:%d\n", predicate, prefix, filename, lineno); =20 - if ( debugger_trap_fatal(TRAP_invalid_op, regs) ) + if ( debugger_trap_fatal(X86_EXC_UD, regs) ) return; =20 show_execution_state(regs); @@ -1268,11 +1268,11 @@ void do_invalid_op(struct cpu_user_regs *regs) if ( likely(extable_fixup(regs, true)) ) return; =20 - if ( debugger_trap_fatal(TRAP_invalid_op, regs) ) + if ( debugger_trap_fatal(X86_EXC_UD, regs) ) return; =20 show_execution_state(regs); - panic("FATAL TRAP: vector =3D %d (invalid opcode)\n", TRAP_invalid_op); + panic("FATAL TRAP: vector =3D %d (invalid opcode)\n", X86_EXC_UD); } =20 void do_int3(struct cpu_user_regs *regs) @@ -1284,7 +1284,7 @@ void do_int3(struct cpu_user_regs *regs) if ( likely(extable_fixup(regs, true)) ) return; =20 - if ( !debugger_trap_fatal(TRAP_int3, regs) ) + if ( !debugger_trap_fatal(X86_EXC_BP, regs) ) printk(XENLOG_DEBUG "Hit embedded breakpoint at %p [%ps]\n", _p(regs->rip), _p(regs->rip)); =20 @@ -1293,12 +1293,12 @@ void do_int3(struct cpu_user_regs *regs) =20 if ( guest_kernel_mode(curr, regs) && curr->domain->debugger_attached ) { - curr->arch.gdbsx_vcpu_event =3D TRAP_int3; + curr->arch.gdbsx_vcpu_event =3D X86_EXC_BP; domain_pause_for_debugger(); return; } =20 - pv_inject_hw_exception(TRAP_int3, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_BP, X86_EVENT_NO_EC); } =20 void do_general_protection(struct cpu_user_regs *regs) @@ -1363,7 +1363,7 @@ void do_general_protection(struct cpu_user_regs *regs) } =20 /* Pass on GPF as is. */ - pv_inject_hw_exception(TRAP_gp_fault, regs->error_code); + pv_inject_hw_exception(X86_EXC_GP, regs->error_code); return; #endif =20 @@ -1372,7 +1372,7 @@ void do_general_protection(struct cpu_user_regs *regs) return; =20 hardware_gp: - if ( debugger_trap_fatal(TRAP_gp_fault, regs) ) + if ( debugger_trap_fatal(X86_EXC_GP, regs) ) return; =20 show_execution_state(regs); @@ -1410,7 +1410,7 @@ static int handle_ldt_mapping_fault(unsigned int offs= et, { uint16_t ec =3D (offset & ~(X86_XEC_EXT | X86_XEC_IDT)) | X86_= XEC_TI; =20 - pv_inject_hw_exception(TRAP_gp_fault, ec); + pv_inject_hw_exception(X86_EXC_GP, ec); } else /* else pass the #PF back, with adjusted %cr2. */ @@ -1698,7 +1698,7 @@ void do_page_fault(struct cpu_user_regs *regs) } =20 fatal: - if ( debugger_trap_fatal(TRAP_page_fault, regs) ) + if ( debugger_trap_fatal(X86_EXC_PF, regs) ) return; =20 show_execution_state(regs); @@ -1945,7 +1945,7 @@ void do_device_not_available(struct cpu_user_regs *re= gs) =20 if ( curr->arch.pv.ctrlreg[0] & X86_CR0_TS ) { - pv_inject_hw_exception(TRAP_no_device, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_NM, X86_EVENT_NO_EC); curr->arch.pv.ctrlreg[0] &=3D ~X86_CR0_TS; } else @@ -2009,7 +2009,7 @@ void do_debug(struct cpu_user_regs *regs) return; } #endif - if ( !debugger_trap_fatal(TRAP_debug, regs) ) + if ( !debugger_trap_fatal(X86_EXC_DB, regs) ) { WARN(); regs->eflags &=3D ~X86_EFLAGS_TF; @@ -2077,7 +2077,7 @@ void do_debug(struct cpu_user_regs *regs) return; } =20 - pv_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); + pv_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } =20 void do_entry_CP(struct cpu_user_regs *regs) diff --git a/xen/arch/x86/x86_64/compat/entry.S b/xen/arch/x86/x86_64/compa= t/entry.S index b86d38d1c50d..bd5abd8040bd 100644 --- a/xen/arch/x86/x86_64/compat/entry.S +++ b/xen/arch/x86/x86_64/compat/entry.S @@ -208,13 +208,13 @@ ENTRY(compat_syscall) leal (,%rcx,TBF_INTERRUPT),%ecx UNLIKELY_START(z, compat_syscall_gpf) movq VCPU_trap_ctxt(%rbx),%rdi - movl $TRAP_gp_fault,UREGS_entry_vector(%rsp) + movl $X86_EXC_GP, UREGS_entry_vector(%rsp) subl $2,UREGS_rip(%rsp) /* %r12 is still zero at this point. */ mov %r12d, TRAPBOUNCE_error_code(%rdx) - movl TRAP_gp_fault * TRAPINFO_sizeof + TRAPINFO_eip(%rdi),%eax - movzwl TRAP_gp_fault * TRAPINFO_sizeof + TRAPINFO_cs(%rdi),%esi - testb $4,TRAP_gp_fault * TRAPINFO_sizeof + TRAPINFO_flags(%rdi) + movl X86_EXC_GP * TRAPINFO_sizeof + TRAPINFO_eip(%rdi),%eax + movzwl X86_EXC_GP * TRAPINFO_sizeof + TRAPINFO_cs(%rdi),%esi + testb $4, X86_EXC_GP * TRAPINFO_sizeof + TRAPINFO_flags(%rdi) setnz %cl leal TBF_EXCEPTION|TBF_EXCEPTION_ERRCODE(,%rcx,TBF_INTERRUPT),%ecx UNLIKELY_END(compat_syscall_gpf) @@ -226,9 +226,9 @@ UNLIKELY_END(compat_syscall_gpf) ENTRY(compat_sysenter) CR4_PV32_RESTORE movq VCPU_trap_ctxt(%rbx),%rcx - cmpb $TRAP_gp_fault,UREGS_entry_vector(%rsp) + cmpb $X86_EXC_GP, UREGS_entry_vector(%rsp) movzwl VCPU_sysenter_sel(%rbx),%eax - movzwl TRAP_gp_fault * TRAPINFO_sizeof + TRAPINFO_cs(%rcx),%ecx + movzwl X86_EXC_GP * TRAPINFO_sizeof + TRAPINFO_cs(%rcx),%ecx cmovel %ecx,%eax testl $~3,%eax movl $FLAT_COMPAT_USER_SS,UREGS_ss(%rsp) diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S index 6d7c15ce4371..16acd01c6087 100644 --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -413,10 +413,10 @@ UNLIKELY_END(sysenter_nt_set) leal (,%rcx,TBF_INTERRUPT),%ecx UNLIKELY_START(z, sysenter_gpf) movq VCPU_trap_ctxt(%rbx),%rsi - movl $TRAP_gp_fault,UREGS_entry_vector(%rsp) + movl $X86_EXC_GP, UREGS_entry_vector(%rsp) movl %eax,TRAPBOUNCE_error_code(%rdx) - movq TRAP_gp_fault * TRAPINFO_sizeof + TRAPINFO_eip(%rsi),%rax - testb $4,TRAP_gp_fault * TRAPINFO_sizeof + TRAPINFO_flags(%rsi) + movq X86_EXC_GP * TRAPINFO_sizeof + TRAPINFO_eip(%rsi),%rax + testb $4, X86_EXC_GP * TRAPINFO_sizeof + TRAPINFO_flags(%rsi) setnz %cl leal TBF_EXCEPTION|TBF_EXCEPTION_ERRCODE(,%rcx,TBF_INTERRUPT),%ecx UNLIKELY_END(sysenter_gpf) @@ -507,7 +507,7 @@ int80_slow_path: * IDT entry with DPL=3D=3D0. */ movl $((0x80 << 3) | X86_XEC_IDT),UREGS_error_code(%rsp) - movl $TRAP_gp_fault,UREGS_entry_vector(%rsp) + movl $X86_EXC_GP, UREGS_entry_vector(%rsp) /* A GPF wouldn't have incremented the instruction pointer. */ subq $2,UREGS_rip(%rsp) /* @@ -693,7 +693,7 @@ ret_from_intr: .section .init.text, "ax", @progbits ENTRY(early_page_fault) ENDBR64 - movl $TRAP_page_fault, 4(%rsp) + movl $X86_EXC_PF, 4(%rsp) SAVE_ALL movq %rsp, %rdi call do_early_page_fault @@ -808,13 +808,13 @@ handle_exception_saved: jnz .Lcr4_pv32_done /* * The below effectively is - * if ( regs->entry_vector =3D=3D TRAP_page_fault && + * if ( regs->entry_vector =3D=3D X86_EXC_PF && * (regs->error_code & PFEC_page_present) && * !(regs->error_code & ~(PFEC_write_access|PFEC_insn_fetch))= ) * goto compat_test_all_events; */ mov $PFEC_page_present,%al - cmpb $TRAP_page_fault,UREGS_entry_vector(%rsp) + cmpb $X86_EXC_PF, UREGS_entry_vector(%rsp) jne .Lcr4_pv32_done xor UREGS_error_code(%rsp),%eax test $~(PFEC_write_access|PFEC_insn_fetch),%eax @@ -925,7 +925,7 @@ FATAL_exception_with_ints_disabled: =20 ENTRY(entry_DF) ENDBR64 - movl $TRAP_double_fault,4(%rsp) + movl $X86_EXC_DF, 4(%rsp) /* Set AC to reduce chance of further SMAP faults */ ALTERNATIVE "", stac, X86_FEATURE_XEN_SMAP SAVE_ALL @@ -1047,7 +1047,7 @@ handle_ist_exception: .L_ist_dispatch_done: mov %r15, STACK_CPUINFO_FIELD(xen_cr3)(%r14) mov %bl, STACK_CPUINFO_FIELD(use_pv_cr3)(%r14) - cmpb $TRAP_nmi,UREGS_entry_vector(%rsp) + cmpb $X86_EXC_NMI, UREGS_entry_vector(%rsp) jne ret_from_intr =20 /* We want to get straight to the IRET on the NMI exit path. */ @@ -1118,7 +1118,7 @@ autogen_stubs: /* Automatically generated stubs. */ =20 /* Reserved exceptions, heading towards do_unhandled_trap(). */ .elseif vec =3D=3D X86_EXC_CSO || vec =3D=3D X86_EXC_SPV || \ - vec =3D=3D X86_EXC_VE || (vec > X86_EXC_CP && vec < TRAP_= nr) + vec =3D=3D X86_EXC_VE || (vec > X86_EXC_CP && vec < X86_E= XC_NUM) =20 1: ENDBR64 diff --git a/xen/arch/x86/x86_emulate.c b/xen/arch/x86/x86_emulate.c index 8c7d18521807..9a502e04d68f 100644 --- a/xen/arch/x86/x86_emulate.c +++ b/xen/arch/x86/x86_emulate.c @@ -78,7 +78,7 @@ int cf_check x86emul_read_xcr( break; /* fall through */ default: - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); return X86EMUL_EXCEPTION; } =20 @@ -99,7 +99,7 @@ int cf_check x86emul_write_xcr( default: gp_fault: if ( ctxt ) - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); return X86EMUL_EXCEPTION; } =20 @@ -146,7 +146,7 @@ int cf_check x86emul_read_dr( ud_fault: default: if ( ctxt ) - x86_emul_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC, ctxt); + x86_emul_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC, ctxt); =20 return X86EMUL_EXCEPTION; } @@ -168,11 +168,11 @@ int cf_check x86emul_write_dr( return X86EMUL_OKAY; =20 case -ENODEV: - x86_emul_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC, ctxt); + x86_emul_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC, ctxt); return X86EMUL_EXCEPTION; =20 default: - x86_emul_hw_exception(TRAP_gp_fault, 0, ctxt); + x86_emul_hw_exception(X86_EXC_GP, 0, ctxt); return X86EMUL_EXCEPTION; } } diff --git a/xen/arch/x86/x86_emulate/x86_emulate.h b/xen/arch/x86/x86_emul= ate/x86_emulate.h index bb7af967ffee..9644a9847950 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -90,7 +90,7 @@ struct x86_event { uint8_t type; /* X86_EVENTTYPE_* */ uint8_t insn_len; /* Instruction length */ int32_t error_code; /* X86_EVENT_NO_EC if n/a */ - unsigned long cr2; /* Only for TRAP_page_fault h/w exception = */ + unsigned long cr2; /* Only for X86_EXC_PF h/w exception */ }; =20 /* @@ -835,7 +835,7 @@ static inline void x86_emul_pagefault( { ASSERT(!ctxt->event_pending); =20 - ctxt->event.vector =3D 14; /* TRAP_page_fault */ + ctxt->event.vector =3D X86_EXC_PF; ctxt->event.type =3D X86_EVENTTYPE_HW_EXCEPTION; ctxt->event.error_code =3D error_code; ctxt->event.cr2 =3D cr2; --=20 2.30.2