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Wed, 15 Feb 2023 07:39:06 -0800 (PST) Sender: Sergey Dyasli From: Sergey Dyasli X-Google-Original-From: Sergey Dyasli To: xen-devel@lists.xenproject.org Cc: Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Sergey Dyasli Subject: [PATCH v4 1/2] x86/ucode/AMD: apply the patch early on every logical thread Date: Wed, 15 Feb 2023 15:38:45 +0000 Message-Id: <20230215153846.18582-2-sergey.dyasli@citrix.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230215153846.18582-1-sergey.dyasli@citrix.com> References: <20230215153846.18582-1-sergey.dyasli@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1676475580677100001 Content-Type: text/plain; charset="utf-8" The original issue has been reported on AMD Bulldozer-based CPUs where ucode loading loses the LWP feature bit in order to gain the IBPB bit. LWP disabling is per-SMT/CMT core modification and needs to happen on each sibling thread despite the shared microcode engine. Otherwise, logical CPUs will end up with different cpuid capabilities. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D216211 Guests running under Xen happen to be not affected because of levelling logic for the feature masking/override MSRs which causes the LWP bit to fall out and hides the issue. The latest recommendation from AMD, after discussing this bug, is to load ucode on every logical CPU. In Linux kernel this issue has been addressed by e7ad18d1169c ("x86/microcode/AMD: Apply the patch early on every logical thread"). Follow the same approach in Xen. Introduce SAME_UCODE match result and use it for early AMD ucode loading. Take this opportunity and move opt_ucode_allow_same out of compare_revisions() to the relevant callers and also modify the warning message based on it. Intel's side of things is modified for consistency but provides no functional change. Signed-off-by: Sergey Dyasli Reviewed-by: Jan Beulich --- v3 --> v4: - Coding style fixes - Removed goto - Removed the paragraph about late loading in the commit message v2 --> v3: - Moved opt_ucode_allow_same out of compare_revisions() and updated the commit message - Adjusted the warning message v1 --> v2: - Expanded the commit message with the levelling section - Adjusted comment for OLD_UCODE --- xen/arch/x86/cpu/microcode/amd.c | 11 ++++++++--- xen/arch/x86/cpu/microcode/core.c | 26 +++++++++++++++++--------- xen/arch/x86/cpu/microcode/intel.c | 10 +++++++--- xen/arch/x86/cpu/microcode/private.h | 3 ++- 4 files changed, 34 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/= amd.c index 4b097187a0..a9a5557835 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -176,8 +176,8 @@ static enum microcode_match_result compare_revisions( if ( new_rev > old_rev ) return NEW_UCODE; =20 - if ( opt_ucode_allow_same && new_rev =3D=3D old_rev ) - return NEW_UCODE; + if ( new_rev =3D=3D old_rev ) + return SAME_UCODE; =20 return OLD_UCODE; } @@ -220,8 +220,13 @@ static int cf_check apply_microcode(const struct micro= code_patch *patch) unsigned int cpu =3D smp_processor_id(); struct cpu_signature *sig =3D &per_cpu(cpu_sig, cpu); uint32_t rev, old_rev =3D sig->rev; + enum microcode_match_result result =3D microcode_fits(patch); =20 - if ( microcode_fits(patch) !=3D NEW_UCODE ) + /* + * Allow application of the same revision to pick up SMT-specific chan= ges + * even if the revision of the other SMT thread is already up-to-date. + */ + if ( result !=3D NEW_UCODE && result !=3D SAME_UCODE ) return -EINVAL; =20 if ( check_final_patch_levels(sig) ) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index d14754e222..ba6e7b42c6 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -612,17 +612,25 @@ static long cf_check microcode_update_helper(void *da= ta) * that ucode revision. */ spin_lock(µcode_mutex); - if ( microcode_cache && - alternative_call(ucode_ops.compare_patch, - patch, microcode_cache) !=3D NEW_UCODE ) + if ( microcode_cache ) { - spin_unlock(µcode_mutex); - printk(XENLOG_WARNING "microcode: couldn't find any newer revision= " - "in the provided blob!\n"); - microcode_free_patch(patch); - ret =3D -ENOENT; + enum microcode_match_result result; =20 - goto put; + result =3D alternative_call(ucode_ops.compare_patch, patch, + microcode_cache); + + if ( result !=3D NEW_UCODE && + !(opt_ucode_allow_same && result =3D=3D SAME_UCODE) ) + { + spin_unlock(µcode_mutex); + printk(XENLOG_WARNING + "microcode: couldn't find any newer%s revision in the p= rovided blob!\n", + opt_ucode_allow_same ? " (or the same)" : ""); + microcode_free_patch(patch); + ret =3D -ENOENT; + + goto put; + } } spin_unlock(µcode_mutex); =20 diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcod= e/intel.c index f7fec4b4ed..8d4d6574aa 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -232,8 +232,8 @@ static enum microcode_match_result compare_revisions( if ( new_rev > old_rev ) return NEW_UCODE; =20 - if ( opt_ucode_allow_same && new_rev =3D=3D old_rev ) - return NEW_UCODE; + if ( new_rev =3D=3D old_rev ) + return SAME_UCODE; =20 /* * Treat pre-production as always applicable - anyone using pre-produc= tion @@ -290,8 +290,12 @@ static int cf_check apply_microcode(const struct micro= code_patch *patch) unsigned int cpu =3D smp_processor_id(); struct cpu_signature *sig =3D &this_cpu(cpu_sig); uint32_t rev, old_rev =3D sig->rev; + enum microcode_match_result result; + + result =3D microcode_update_match(patch); =20 - if ( microcode_update_match(patch) !=3D NEW_UCODE ) + if ( result !=3D NEW_UCODE && + !(opt_ucode_allow_same && result =3D=3D SAME_UCODE) ) return -EINVAL; =20 wbinvd(); diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microc= ode/private.h index 73b095d5bf..626aeb4d08 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -6,7 +6,8 @@ extern bool opt_ucode_allow_same; =20 enum microcode_match_result { - OLD_UCODE, /* signature matched, but revision id is older or equal */ + OLD_UCODE, /* signature matched, but revision id is older */ + SAME_UCODE, /* signature matched, but revision id is the same */ NEW_UCODE, /* signature matched, but revision id is newer */ MIS_UCODE, /* signature mismatched */ }; --=20 2.31.1 From nobody Fri May 10 02:57:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" Currently late ucode loading is performed only on the first core of CPU siblings. But according to the latest recommendation from AMD, late ucode loading should happen on every logical thread/core. To achieve that, consider every logical cpu as "primary" when running on AMD cpus, i.e. skip cpu_sibling_mask checks. Signed-off-by: Sergey Dyasli --- v4: - new patch --- xen/arch/x86/cpu/microcode/core.c | 35 ++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index ba6e7b42c6..f720030761 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -398,10 +398,16 @@ static int cf_check microcode_nmi_callback( (!ucode_in_nmi && cpu =3D=3D primary) ) return 0; =20 - if ( cpu =3D=3D primary ) + if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + /* load ucode on every logical thread/core */ ret =3D primary_thread_work(nmi_patch); else - ret =3D secondary_nmi_work(); + { + if ( cpu =3D=3D primary ) + ret =3D primary_thread_work(nmi_patch); + else + ret =3D secondary_nmi_work(); + } this_cpu(loading_err) =3D ret; =20 return 0; @@ -540,7 +546,6 @@ static int control_thread_fn(const struct microcode_pat= ch *patch) static int cf_check do_microcode_update(void *patch) { unsigned int cpu =3D smp_processor_id(); - int ret; =20 /* * The control thread set state to coordinate ucode loading. Primary @@ -548,13 +553,18 @@ static int cf_check do_microcode_update(void *patch) * the completion of the ucode loading process. */ if ( cpu =3D=3D cpumask_first(&cpu_online_map) ) - ret =3D control_thread_fn(patch); - else if ( cpu =3D=3D cpumask_first(this_cpu(cpu_sibling_mask)) ) - ret =3D primary_thread_fn(patch); - else - ret =3D secondary_thread_fn(); + return control_thread_fn(patch); =20 - return ret; + if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + /* load ucode on every logical thread/core */ + return primary_thread_fn(patch); + else + { + if ( cpu =3D=3D cpumask_first(this_cpu(cpu_sibling_mask)) ) + return primary_thread_fn(patch); + else + return secondary_thread_fn(); + } } =20 struct ucode_buf { @@ -642,8 +652,13 @@ static long cf_check microcode_update_helper(void *dat= a) /* Calculate the number of online CPU core */ nr_cores =3D 0; for_each_online_cpu(cpu) - if ( cpu =3D=3D cpumask_first(per_cpu(cpu_sibling_mask, cpu)) ) + { + if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + /* load ucode on every logical thread/core */ + nr_cores++; + else if ( cpu =3D=3D cpumask_first(per_cpu(cpu_sibling_mask, cpu))= ) nr_cores++; + } =20 printk(XENLOG_INFO "%u cores are to update their microcode\n", nr_core= s); =20 --=20 2.31.1