From nobody Tue Feb 10 00:59:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1675336135815973.3190575460999; Thu, 2 Feb 2023 03:08:55 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.488661.756851 (Exim 4.92) (envelope-from ) id 1pNXSD-0003Bb-Rs; Thu, 02 Feb 2023 11:08:33 +0000 Received: by outflank-mailman (output) from mailman id 488661.756851; Thu, 02 Feb 2023 11:08:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pNXSD-0003AH-Kt; Thu, 02 Feb 2023 11:08:33 +0000 Received: by outflank-mailman (input) for mailman id 488661; Thu, 02 Feb 2023 11:08:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pNXSC-0002sY-4x for xen-devel@lists.xenproject.org; Thu, 02 Feb 2023 11:08:32 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id ecc1a21b-a2e9-11ed-933c-83870f6b2ba8; Thu, 02 Feb 2023 12:08:30 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 740A41424; Thu, 2 Feb 2023 03:09:12 -0800 (PST) Received: from e109506.cambridge.arm.com (e109506.cambridge.arm.com [10.1.199.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CD8333F64C; Thu, 2 Feb 2023 03:08:28 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ecc1a21b-a2e9-11ed-933c-83870f6b2ba8 From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: bertrand.marquis@arm.com, wei.chen@arm.com, Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Wei Liu Subject: [PATCH 02/10] xen/arm: add sve_vl_bits field to domain Date: Thu, 2 Feb 2023 11:08:08 +0000 Message-Id: <20230202110816.1252419-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230202110816.1252419-1-luca.fancellu@arm.com> References: <20230202110816.1252419-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1675336137368100009 Content-Type: text/plain; charset="utf-8" Add sve_vl_bits field to arch_domain and xen_arch_domainconfig structure, to allow the domain to have an information about the SVE feature and the number of SVE register bits that are allowed for this domain. The field is used also to allow or forbid a domain to use SVE, because a value equal to zero means the guest is not allowed to use the feature. Check that the requested vector length is lower or equal to the platform supported vector length, otherwise fail on domain creation. Signed-off-by: Luca Fancellu --- Changes from RFC: - restore zcr_el2 in sve_restore_state, that will be introduced later in this serie, so remove zcr_el2 related code from this patch and move everything to the later patch (Julien) - add explicit padding into struct xen_arch_domainconfig (Julien) - Don't lower down the vector length, just fail to create the domain. (Julien) --- xen/arch/arm/arm64/sve.c | 9 ++++++++ xen/arch/arm/domain.c | 32 ++++++++++++++++++++++++++++ xen/arch/arm/include/asm/arm64/sve.h | 12 +++++++++++ xen/arch/arm/include/asm/domain.h | 5 +++++ xen/include/public/arch-arm.h | 3 +++ xen/include/public/domctl.h | 2 +- 6 files changed, 62 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c index 1c8024b44cd8..eee39caa9efa 100644 --- a/xen/arch/arm/arm64/sve.c +++ b/xen/arch/arm/arm64/sve.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -47,3 +48,11 @@ register_t vl_to_zcr(uint16_t vl) { return ((vl / SVE_VL_MULTIPLE_VAL) - 1U) & ZCR_ELx_LEN_MASK; } + +/* Get the system sanitized value for VL in bits */ +uint16_t get_sys_vl_len(void) +{ + /* ZCR_ELx len field is ((len+1) * 128) =3D vector bits length */ + return ((system_cpuinfo.zcr64.bits[0] & ZCR_ELx_LEN_MASK) + 1U) * + SVE_VL_MULTIPLE_VAL; +} diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index adb6ace2e24d..8d64e3c08edf 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -13,6 +13,7 @@ #include =20 #include +#include #include #include #include @@ -550,6 +551,8 @@ int arch_vcpu_create(struct vcpu *v) v->arch.vmpidr =3D MPIDR_SMP | vcpuid_to_vaffinity(v->vcpu_id); =20 v->arch.cptr_el2 =3D get_default_cptr_flags(); + if ( is_sve_domain(v->domain) ) + v->arch.cptr_el2 &=3D ~HCPTR_CP(8); =20 v->arch.hcr_el2 =3D get_default_hcr_flags(); =20 @@ -594,6 +597,7 @@ int arch_sanitise_domain_config(struct xen_domctl_creat= edomain *config) unsigned int max_vcpus; unsigned int flags_required =3D (XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_h= ap); unsigned int flags_optional =3D (XEN_DOMCTL_CDF_iommu | XEN_DOMCTL_CDF= _vpmu); + unsigned int sve_vl_bits =3D config->arch.sve_vl_bits; =20 if ( (config->flags & ~flags_optional) !=3D flags_required ) { @@ -602,6 +606,31 @@ int arch_sanitise_domain_config(struct xen_domctl_crea= tedomain *config) return -EINVAL; } =20 + /* Check feature flags */ + if ( sve_vl_bits > 0 ) { + unsigned int zcr_max_bits =3D get_sys_vl_len(); + + if ( !cpu_has_sve ) + { + dprintk(XENLOG_INFO, "SVE is unsupported on this machine.\n"); + return -EINVAL; + } + else if ( !is_vl_valid(sve_vl_bits) ) + { + dprintk(XENLOG_INFO, "Unsupported SVE vector length (%u)\n", + sve_vl_bits); + return -EINVAL; + } + else if ( sve_vl_bits > zcr_max_bits ) + { + dprintk(XENLOG_INFO, + "The requested SVE vector length (%u) must be lower or= \n" + "equal to the platform supported vector length (%u)\n", + sve_vl_bits, zcr_max_bits); + return -EINVAL; + } + } + /* The P2M table must always be shared between the CPU and the IOMMU */ if ( config->iommu_opts & XEN_DOMCTL_IOMMU_no_sharept ) { @@ -744,6 +773,9 @@ int arch_domain_create(struct domain *d, if ( (rc =3D domain_vpci_init(d)) !=3D 0 ) goto fail; =20 + /* Copy sve_vl_bits to the domain configuration */ + d->arch.sve_vl_bits =3D config->arch.sve_vl_bits; + return 0; =20 fail: diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/as= m/arm64/sve.h index bd56e2f24230..f4a660e402ca 100644 --- a/xen/arch/arm/include/asm/arm64/sve.h +++ b/xen/arch/arm/include/asm/arm64/sve.h @@ -13,10 +13,17 @@ /* Vector length must be multiple of 128 */ #define SVE_VL_MULTIPLE_VAL (128U) =20 +static inline bool is_vl_valid(uint16_t vl) +{ + /* SVE vector length is multiple of 128 and maximum 2048 */ + return ((vl % SVE_VL_MULTIPLE_VAL) =3D=3D 0) && (vl <=3D SVE_VL_MAX_BI= TS); +} + #ifdef CONFIG_ARM64_SVE =20 register_t compute_max_zcr(void); register_t vl_to_zcr(uint16_t vl); +uint16_t get_sys_vl_len(void); =20 #else /* !CONFIG_ARM64_SVE */ =20 @@ -30,6 +37,11 @@ static inline register_t vl_to_zcr(uint16_t vl) return 0; } =20 +static inline uint16_t get_sys_vl_len(void) +{ + return 0; +} + #endif =20 #endif /* _ARM_ARM64_SVE_H */ diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index 42eb5df320a7..1bd669e0a5c1 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -31,6 +31,8 @@ enum domain_type { =20 #define is_domain_direct_mapped(d) ((d)->cdf & CDF_directmap) =20 +#define is_sve_domain(d) ((d)->arch.sve_vl_bits > 0) + /* * Is the domain using the host memory layout? * @@ -114,6 +116,9 @@ struct arch_domain void *tee; #endif =20 + /* max SVE vector length in bits */ + uint16_t sve_vl_bits; + } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 1528ced5097a..3094aeb57990 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -304,6 +304,9 @@ struct xen_arch_domainconfig { uint16_t tee_type; /* IN */ uint32_t nr_spis; + /* IN */ + uint16_t sve_vl_bits; + uint16_t _pad1; /* * OUT * Based on the property clock-frequency in the DT timer node. diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 51be28c3de7c..616d7a1c070d 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -21,7 +21,7 @@ #include "hvm/save.h" #include "memory.h" =20 -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000015 +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000016 =20 /* * NB. xen_domctl.domain is an IN/OUT parameter for this operation. --=20 2.25.1