From nobody Fri Dec 19 20:14:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1673604731; cv=none; d=zohomail.com; s=zohoarc; b=mlW4kV23+IoLux9PvEcf568f2LcUJhi++Vk3UV4oB5ZmkGiz9fT2yirJesC+VH9nRm+8fKa5/zB7n6wbs9tqN8Q6BNIMr4FMcbILgPSWpzCOjVWUmwE5m+8E4zdcXJunMX4q/FnirLR97HWg981f2PPOjo+DA6aLJ/j54QTBU4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673604731; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ANX4uKeCMRVYaXkbuMkjBprVFaVY+sMMAHGSSjC0sGw=; b=QPO7vRDeu0J2KHyGJKT8Ze8BdTA3F1gwa+6N4YuGID43AacHZkon3Y4TtBVzbBze/Kxv7gvUULmEDh0226sZPHS0ydASPiw8SFq3WsJ58IEx+vnDCpWBeZCO+xBE0w8vDrGBugqepC4HqQ3lRhYCvjdk/07p0lTvAWK+VwLDLEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1673604731224905.1625778953739; Fri, 13 Jan 2023 02:12:11 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.477054.739644 (Exim 4.92) (envelope-from ) id 1pGH2N-0005pV-DI; Fri, 13 Jan 2023 10:11:51 +0000 Received: by outflank-mailman (output) from mailman id 477054.739644; Fri, 13 Jan 2023 10:11:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pGH2N-0005oq-5P; Fri, 13 Jan 2023 10:11:51 +0000 Received: by outflank-mailman (input) for mailman id 477054; Fri, 13 Jan 2023 10:11:49 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pGH2L-0005P0-NI for xen-devel@lists.xenproject.org; Fri, 13 Jan 2023 10:11:49 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1pGH2L-0006ep-Fe; Fri, 13 Jan 2023 10:11:49 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1pGH2L-0005Ty-7e; Fri, 13 Jan 2023 10:11:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=ANX4uKeCMRVYaXkbuMkjBprVFaVY+sMMAHGSSjC0sGw=; b=dPsTKjOE8q39aZlEKcGaRYj8pi tsaflRTAnwNBfhsfgnCX2Vms/yRRLbEN6g0iPhut/UddBFIdBPNx2nZTFLw+SbStTmzJGrmHK5oHF S9fk1Q8mV2suAWKmk8TEVVlcTvYHzS6M4Jqf8qgMhV+teUggvnBZ4xhESGtwutw/LO+4=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v4 08/14] xen/arm32: head: Introduce an helper to flush the TLBs Date: Fri, 13 Jan 2023 10:11:30 +0000 Message-Id: <20230113101136.479-9-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113101136.479-1-julien@xen.org> References: <20230113101136.479-1-julien@xen.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1673604731872100018 Content-Type: text/plain; charset="utf-8" From: Julien Grall The sequence for flushing the TLBs is 4 instruction long and often requires an explanation how it works. So create a helper and use it in the boot code (switch_ttbr() is left alone until we decide the semantic of the call). Note that in secondary_switched, we were also flushing the instruction cache and branch predictor. Neither of them was necessary because: * We are only supporting IVIPT cache on arm32, so the instruction cache flush is only necessary when executable code is modified. None of the boot code is doing that. * The instruction cache is not invalidated and misprediction is not a problem at boot. Signed-off-by: Julien Grall Reviewed-by: Henry Wang Reviewed-by: Michal Orzel Tested-by: Henry Wang ---- Changes in v4: - Expand the commit message to explain why switch_ttbr() is not updated. - Remove extra spaces in the comment - Fix typo in the commit message Changes in v3: * Fix typo * Update the documentation * Rename the argument from tmp1 to tmp --- xen/arch/arm/arm32/head.S | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 50ad6c948be2..67b910808b74 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -66,6 +66,20 @@ add \rb, \rb, r10 .endm =20 +/* + * Flush local TLBs + * + * @tmp: Scratch register + * + * See asm/arm32/flushtlb.h for the explanation of the sequence. + */ +.macro flush_xen_tlb_local tmp + dsb nshst + mcr CP32(\tmp, TLBIALLH) + dsb nsh + isb +.endm + /* * Common register usage in this file: * r0 - @@ -232,11 +246,7 @@ secondary_switched: mcrr CP64(r4, r5, HTTBR) dsb isb - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ - mcr CP32(r0, ICIALLU) /* Flush I-cache */ - mcr CP32(r0, BPIALL) /* Flush branch predictor */ - dsb /* Ensure completion of TLB+BP flush = */ - isb + flush_xen_tlb_local r0 =20 #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ @@ -529,8 +539,7 @@ enable_mmu: * The state of the TLBs is unknown before turning on the MMU. * Flush them to avoid stale one. */ - mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLBs */ - dsb nsh + flush_xen_tlb_local r0 =20 /* Write Xen's PT's paddr into the HTTBR */ load_paddr r0, boot_pgtable @@ -605,12 +614,7 @@ remove_identity_mapping: strd r2, r3, [r0, r1] =20 identity_mapping_removed: - /* See asm/arm32/flushtlb.h for the explanation of the sequence. */ - dsb nshst - mcr CP32(r0, TLBIALLH) - dsb nsh - isb - + flush_xen_tlb_local r0 mov pc, lr ENDPROC(remove_identity_mapping) =20 --=20 2.38.1