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bh=+ycBL9vnbS90AEBJIm+fOecH7kLgLt9EJFNxYphA770=; b=ZmYoHEZAKc98I3QhHr7QGiETU/YC9lf1LMP/D54ERVY8XzeKOb+3c5ao816pACymeyassgIr3v5+Fxd7QIPQcNzyVyN7HgpzbfKF0a0pwaS//sv7HDQD5L9dnLXhhr3S0KERjdsSSG/DgdPirlOafj1We1BiS85286RYoYudo+A= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v5 09/11] xen/Arm: GICv3: Define remaining GIC registers for AArch32 Date: Mon, 5 Dec 2022 13:26:35 +0000 Message-ID: <20221205132637.26775-10-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221205132637.26775-1-ayan.kumar.halder@amd.com> References: <20221205132637.26775-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT026:EE_|SA3PR12MB7949:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a364457-2ba1-40c9-0abd-08dad6c4de73 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 13:30:25.9893 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a364457-2ba1-40c9-0abd-08dad6c4de73 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7949 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1670247056618100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define missing assembly aliases for GIC registers on arm32, taking the ones defined already for arm64 as a base. Aliases are defined according to the GIC Architecture Specification ARM IHI 0069H. Defined the following registers:- 1. Interrupt Controller Interrupt Priority Mask Register 2. Interrupt Controller System Register Enable register 3. Interrupt Controller Deactivate Interrupt Register 4. Interrupt Controller End Of Interrupt Register 1 5. Interrupt Controller Interrupt Acknowledge Register 1 6. Interrupt Controller Binary Point Register 1 7. Interrupt Controller Control Register 8. Interrupt Controller Interrupt Group 1 Enable register 9. Interrupt Controller Maintenance Interrupt State Register 10. Interrupt Controller End of Interrupt Status Register 11. Interrupt Controller Empty List Register Status Register 12. Interrupt Controller Virtual Machine Control Register Signed-off-by: Ayan Kumar Halder Reviewed-by: Michal Orzel Acked-by: Julien Grall --- Changes from :- v1 - 1. Moved coproc regs definition to asm/cpregs.h v2 - 1. Defined register alias. 2. Style issues. 3. Defined ELSR, MISR, EISR to make it consistent with AArch64. v3 - 1. Rectified some of the register names. v4 - 1. Placed ICC_DIR after VBAR. 2. Added Rb. xen/arch/arm/include/asm/cpregs.h | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/c= pregs.h index 4476c9f11b..6b083de204 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -161,6 +161,7 @@ #define DACR p15,0,c3,c0,0 /* Domain Access Control Register = */ =20 /* CP15 CR4: */ +#define ICC_PMR p15,0,c4,c6,0 /* Interrupt Priority Mask Registe= r */ =20 /* CP15 CR5: Fault Status Registers */ #define DFSR p15,0,c5,c0,0 /* Data Fault Status Register */ @@ -257,6 +258,7 @@ #define ICC_ASGI1R p15,1,c12 /* Interrupt Controller Alias SGI = Group 1 Register */ #define ICC_SGI0R p15,2,c12 /* Interrupt Controller SGI Group = 0 */ #define VBAR p15,0,c12,c0,0 /* Vector Base Address Register */ +#define ICC_DIR p15,0,c12,c11,1 /* Interrupt Controller Deactivate= Interrupt Register */ #define HVBAR p15,4,c12,c0,0 /* Hyp. Vector Base Address Regist= er */ =20 /* @@ -279,6 +281,20 @@ #define ICH_AP1R2 __AP1Rx(2) #define ICH_AP1R3 __AP1Rx(3) =20 +#define ICC_IAR1 p15,0,c12,c12,0 /* Interrupt Controller Interrupt= Acknowledge Register 1 */ +#define ICC_EOIR1 p15,0,c12,c12,1 /* Interrupt Controller End Of In= terrupt Register 1 */ +#define ICC_BPR1 p15,0,c12,c12,3 /* Interrupt Controller Binary Po= int Register 1 */ +#define ICC_CTLR p15,0,c12,c12,4 /* Interrupt Controller Control R= egister */ +#define ICC_SRE p15,0,c12,c12,5 /* Interrupt Controller System Re= gister Enable register */ +#define ICC_IGRPEN1 p15,0,c12,c12,7 /* Interrupt Controller Interrupt= Group 1 Enable register */ +#define ICC_HSRE p15,4,c12,c9,5 /* Interrupt Controller Hyp Syste= m Register Enable register */ +#define ICH_HCR p15,4,c12,c11,0 /* Interrupt Controller Hyp Contr= ol Register */ +#define ICH_VTR p15,4,c12,c11,1 /* Interrupt Controller VGIC Type= Register */ +#define ICH_MISR p15,4,c12,c11,2 /* Interrupt Controller Maintenan= ce Interrupt State Register */ +#define ICH_EISR p15,4,c12,c11,3 /* Interrupt Controller End of In= terrupt Status Register */ +#define ICH_ELRSR p15,4,c12,c11,5 /* Interrupt Controller Empty Lis= t Register Status Register */ +#define ICH_VMCR p15,4,c12,c11,7 /* Interrupt Controller Virtual M= achine Control Register */ + /* CP15 CR12: Interrupt Controller List Registers, n =3D 0 - 15 */ #define __LR0(x) p15, 4, c12, c12, x #define __LR8(x) p15, 4, c12, c13, x @@ -379,6 +395,15 @@ #define HCR_EL2 HCR #define HPFAR_EL2 HPFAR #define HSTR_EL2 HSTR +#define ICC_BPR1_EL1 ICC_BPR1 +#define ICC_CTLR_EL1 ICC_CTLR +#define ICC_DIR_EL1 ICC_DIR +#define ICC_EOIR1_EL1 ICC_EOIR1 +#define ICC_IGRPEN1_EL1 ICC_IGRPEN1 +#define ICC_PMR_EL1 ICC_PMR +#define ICC_SGI1R_EL1 ICC_SGI1R +#define ICC_SRE_EL1 ICC_SRE +#define ICC_SRE_EL2 ICC_HSRE #define ICH_AP0R0_EL2 ICH_AP0R0 #define ICH_AP0R1_EL2 ICH_AP0R1 #define ICH_AP0R2_EL2 ICH_AP0R2 @@ -387,6 +412,10 @@ #define ICH_AP1R1_EL2 ICH_AP1R1 #define ICH_AP1R2_EL2 ICH_AP1R2 #define ICH_AP1R3_EL2 ICH_AP1R3 +#define ICH_EISR_EL2 ICH_EISR +#define ICH_ELRSR_EL2 ICH_ELRSR +#define ICH_HCR_EL2 ICH_HCR +#define ICC_IAR1_EL1 ICC_IAR1 #define ICH_LR0_EL2 ICH_LR0 #define ICH_LR1_EL2 ICH_LR1 #define ICH_LR2_EL2 ICH_LR2 @@ -419,6 +448,9 @@ #define ICH_LRC13_EL2 ICH_LRC13 #define ICH_LRC14_EL2 ICH_LRC14 #define ICH_LRC15_EL2 ICH_LRC15 +#define ICH_MISR_EL2 ICH_MISR +#define ICH_VMCR_EL2 ICH_VMCR +#define ICH_VTR_EL2 ICH_VTR #define ID_AFR0_EL1 ID_AFR0 #define ID_DFR0_EL1 ID_DFR0 #define ID_DFR1_EL1 ID_DFR1 --=20 2.17.1