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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , Ayan Kumar Halder Subject: [XEN v4] xen/page_alloc: Relax the BUILD_BUG_ON() in xenheap_max_mfn() Date: Mon, 5 Dec 2022 09:48:17 +0000 Message-ID: <20221205094817.21062-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT095:EE_|MN2PR12MB4517:EE_ X-MS-Office365-Filtering-Correlation-Id: 63d82896-cd03-4200-78bd-08dad6a5de13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QqHLvwbRbLHz43TEkSEmzgvpybW7xCkNlq1nh1bzKjKyZPMftlYXc4sauaj8PYbMNXkA0CBky1RskJAisM9TxduvWKN99Cwedq7+EbQlT/ZbvxnmrkNN7xb2yfo84DhGaCeCO+OalnVEu8t4C/Vyety+N8w8HxOMnFwYcvi7V5L7Uxh7p2KBUdw11Oi5xe8gt5wafk60JLh13LLUzfRGj2+oabz+ydSRjHKTKQTA6knGX4DomO08peqrR5eobk5oVRu2xd9ySSBiDiFn7tY0TLSC+jZGk40BZCmXSVxHJmBPbSCRoEx/v5tEaqG21YdEO2NzDTHC8qWmXh/U1zkgpEx52oEJ5s5GKUJBhG7JUvulHNgoAMzf+w+/i92ov8erIoyufZQv2Forjszb8E6eT6IzoVByUyl3eCdgzr1iVUEGAHgK8qaRov2OvTaNcdlmL6yqOSl+STMapJg8e3py9K2jUUADwK5KwgknITCoH+oeUNa0+VFcToyaO5homQKUq9D98x3+DXMDCQP8ya2GL5cqkcmwByZV94ACufzn0j2hIYl1pHGnORUUiHTTuZBb+RngiYoFYRO2c+7P512tHCSWmHxVK4F8ILj2TfdOHe4vbHAmD+43/A42S8Iw0qfLI09eJ/qub9U8deB6CNGdeS//79i3YDy+UtoekVOza+YFo5t2cJELU58Gkn7st7TWiIWdwrn7fc3HFxZr+d8idD8QsJbcK2Aj4J70SIFBBrQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(396003)(376002)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(1076003)(336012)(186003)(316002)(54906003)(6916009)(478600001)(103116003)(82740400003)(40480700001)(356005)(81166007)(86362001)(40460700003)(36756003)(83380400001)(26005)(47076005)(2616005)(426003)(82310400005)(6666004)(5660300002)(2906002)(41300700001)(36860700001)(4326008)(8676002)(70586007)(70206006)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2022 09:48:30.8550 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63d82896-cd03-4200-78bd-08dad6a5de13 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT095.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4517 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1670233754153100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the near future, we are considering to use a common xen/domain heap for Arm 32-bit V8-R. In this setup, both PADDR_BITS and BITS_PER_LONG will be 32. Therefore, the condition PADDR_BITS >=3D BITS_PER_LONG will become true. Looking at the commit that introduce the BUILD_BUG_ON (88e3ed61642b "x86/NUMA: make init_node_heap() respect Xen heap limit") and the current use, it seems this check was mainly to ensure that the shift of xenheap_bits is not going to be undefined (>> N for a N-bit type is undefined). So far, all the shifts are using "xenheap_bits - PAGE_SHIFT". Therefore, the existing code should work for 32-bit architecture as long as the result of the substraction is below 32. Therefore relax the BUILD_BUG_ON() to check that (PADDR_BITS - PAGE_SHIFT) is not equal of above BITS_PER_LONG. Note that we would need further precaution if we ended up to use 'xenheap_bits' alone in shifts. Signed-off-by: Ayan Kumar Halder Signed-off-by: Julien Grall Acked-by: Jan Beulich --- Currently this change will not have any impact on the existing architecture= s. The following table illustrates PADDR_BITS vs BITS_PER_LONG of different ar= chs ------------------------------------------------ | Arch | PADDR_BITS | BITS_PER_LONG | ------------------------------------------------ | Arm_64 | 48 | 64 | | Arm_32 | 40 | 32 | | RISCV_64 | 56 | 64 | | x86 | 52 | 64 | ------------------------------------------------- However, this will change when we introduce a platform (For eg Cortex-R52) = which supports 32 bit physical address and BITS_PER_LONG. This platform does not = follow the same code path as Arm_32. Thus, I have introduced this change as I don't see it causing a regression = on any of the supported platforms. Changes from v1:- 1. Changed the check from "(PADDR_BITS > BITS_PER_LONG)" to "((PADDR_BITS -= PAGE_SHIFT) >=3D BITS_PER_LONG)" 2. Updated the commit message to explain the reason for this. v2 :- 1. Updated the commit message. v3 :- 1. Updated the commit message. 2. Added Julien's SOB. xen/common/page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 62afb07bc6..c5b8c7444f 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -2245,7 +2245,7 @@ void __init xenheap_max_mfn(unsigned long mfn) { ASSERT(!first_node_initialised); ASSERT(!xenheap_bits); - BUILD_BUG_ON(PADDR_BITS >=3D BITS_PER_LONG); + BUILD_BUG_ON((PADDR_BITS - PAGE_SHIFT) >=3D BITS_PER_LONG); xenheap_bits =3D min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS); printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits); } --=20 2.17.1