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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3] Xen: Ensure "xenheap_bits - PAGE_SHIFT" can be used as a rhs operand of shift operator Date: Fri, 2 Dec 2022 12:35:59 +0000 Message-ID: <20221202123559.33143-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT043:EE_|BL1PR12MB5287:EE_ X-MS-Office365-Filtering-Correlation-Id: e9d395dc-39e6-4161-6de6-08dad461c962 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uJAM8npwqPkMcR0Jqc+fp9oWfVrgy/T4mFYkjqyWaxgoar5US8ZoqH9XbWuWW7twBxD88LZCZa3zF7rLOElNCrz00lJIF2FdIEUTkGWCG8OXSFVZfDEMhYEyh0l22CBEVLP0CfRtOFkE4tM+XfbRokFFLn1SmUhlV5M9zbRhGFv4yFzUJ1nqSkT70lq6NfiXbXYQZ1CuvlrDX2eE+uY72TAWGU0azQ66sIii1J/yf+mlPv6320eMdqHHryeH09xLTQhoKOCjSi8dAj9d5xLR094lGVsuyVVwUL7rVFwA5OyVByneeH+gJGsP8Xg3WqwPD19R3Sgj9J8te8aqZmiFaOrOuOf/mAOetNX/bK4O6+kaRLj54aKiNkEpUf+g71ADu/NohjDxKuzNKcNYzl4vSxzCYMowlI4UwlpkDa/d5FXTqE3Mn8CzxUwNNDr9t+uinkwAiBLnaCrBd5BkMW6J8MIK4IUVgOTgjPAukeQ3YNuEA361A+p1ybSKNf4DE5oOE3OVxIWqzWKJId500AT0D+/uo1jDA95OLZfP8wGg9rfGC5uJN+3ZcLZf9Ktmbgzlad3fx8PBtyalGlodMH5ScV9JFc9JpQJRDcLqUz7tujEnLf3g51Yyp98FbQXHeO0Eo8x28QY/vZPR2elKw+VTNzGIjz1UZGRg5h/FRliIFI9ejkKUssdu/XQ+09uwGCkfSgudbKj4dfib90YBHPvuyXJpEsnhz0PqoICz/3voaVI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(136003)(39860400002)(376002)(451199015)(36840700001)(40470700004)(46966006)(2906002)(356005)(6666004)(478600001)(81166007)(86362001)(103116003)(40480700001)(36756003)(82740400003)(1076003)(336012)(36860700001)(186003)(47076005)(2616005)(426003)(40460700003)(83380400001)(4326008)(41300700001)(5660300002)(26005)(82310400005)(8936002)(7416002)(70206006)(8676002)(54906003)(316002)(6916009)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 12:36:08.1465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9d395dc-39e6-4161-6de6-08dad461c962 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5287 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1669984621230100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We want to ensure that "xenheap_bits - PAGE_SHIFT" is strictly less than the number of bits to represent unsigned long as it is used a rhs operand to shift mfn. It is also important to note that the "xenheap_bits - PAGE_SHIFT" is never used to shift an address (rather than a frame number), and going forward then also shouldn't be (perhaps unless further precautions are taken). Signed-off-by: Ayan Kumar Halder --- Currently this change will not have any impact on the existing architecture= s. The following table illustrates PADDR_BITS vs BITS_PER_LONG of different ar= chs ------------------------------------------------ | Arch | PADDR_BITS | BITS_PER_LONG | ------------------------------------------------ | Arm_64 | 48 | 64 | | Arm_32 | 40 | 32 | | RISCV_64 | Don't know | 64 | | x86 | 52 | 64 | ------------------------------------------------- However, this will change when we introduce a platform (For eg Cortex-R52) = which supports 32 bit physical address and BITS_PER_LONG. This platform does not = follow the same code path as Arm_32. Thus, I have introduced this change as I don't see it causing a regression = on any of the supported platforms. Changes from v1:- 1. Changed the check from "(PADDR_BITS > BITS_PER_LONG)" to "((PADDR_BITS -= PAGE_SHIFT) >=3D BITS_PER_LONG)" 2. Updated the commit message to explain the reason for this. v2 :- 1. Updated the commit message. xen/common/page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 62afb07bc6..c5b8c7444f 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -2245,7 +2245,7 @@ void __init xenheap_max_mfn(unsigned long mfn) { ASSERT(!first_node_initialised); ASSERT(!xenheap_bits); - BUILD_BUG_ON(PADDR_BITS >=3D BITS_PER_LONG); + BUILD_BUG_ON((PADDR_BITS - PAGE_SHIFT) >=3D BITS_PER_LONG); xenheap_bits =3D min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS); printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits); } --=20 2.17.1