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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2022 18:11:51.5707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad91d816-865d-4166-746b-08dad3c7856a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6564 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1669918380788100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Machine frame number (mfn) is used to represent the hardware page address. This is an unsigned long variable. We need to check if it can hold the comp= lete range of hardware page addresses. To ensure this we check that the count of= bits represented by 'unsigned long' added to the bit index of page size, should = be less than the count of bits required to represent the maximum physical addr= ess. Signed-off-by: Ayan Kumar Halder --- Currently this change will not have any impact on the existing architecture= s. The following table illustrates PADDR_BITS vs BITS_PER_LONG of different ar= chs ------------------------------------------------ | Arch | PADDR_BITS | BITS_PER_LONG | ------------------------------------------------ | Arm_64 | 48 | 64 | | Arm_32 | 40 | 32 | | RISCV_64 | Don't know | 64 | | x86 | 52 | 64 | ------------------------------------------------- However, this will change when we introduce a platform (For eg Cortex-R52) = which supports 32 bit physical address and BITS_PER_LONG. This platform does not = follow the same code path as Arm_32. Thus, I have introduced this change as I don't see it causing a regression = on any of the supported platforms. Changes from v1:- 1. Changed the check from "(PADDR_BITS > BITS_PER_LONG)" to "((PADDR_BITS -= PAGE_SHIFT) >=3D BITS_PER_LONG)" 2. Updated the commit message to explain the reason for this. xen/common/page_alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 62afb07bc6..c5b8c7444f 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -2245,7 +2245,7 @@ void __init xenheap_max_mfn(unsigned long mfn) { ASSERT(!first_node_initialised); ASSERT(!xenheap_bits); - BUILD_BUG_ON(PADDR_BITS >=3D BITS_PER_LONG); + BUILD_BUG_ON((PADDR_BITS - PAGE_SHIFT) >=3D BITS_PER_LONG); xenheap_bits =3D min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS); printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits); } --=20 2.17.1