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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v6 01/11] xen/arm: remove xen_phys_start and xenheap_phys_end from config.h Date: Fri, 4 Nov 2022 18:07:31 +0800 Message-ID: <20221104100741.2176307-2-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT061:EE_|GV2PR08MB8121:EE_|VI1EUR03FT044:EE_|AM9PR08MB6228:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f472e3f-3336-4640-d16b-08dabe4c831b x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:25.1839 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f472e3f-3336-4640-d16b-08dabe4c831b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT044.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6228 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556552830100001 Content-Type: text/plain; charset="utf-8" These two variables are stale variables, they only have declarations in config.h, they don't have any definition and no any code is using these two variables. So in this patch, we remove them from config.h. Signed-off-by: Wei Chen Acked-by: Julien Grall --- xen/arch/arm/include/asm/config.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/c= onfig.h index 0fefed1b8a..25a625ff08 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -172,8 +172,6 @@ #define STACK_SIZE (PAGE_SIZE << STACK_ORDER) =20 #ifndef __ASSEMBLY__ -extern unsigned long xen_phys_start; -extern unsigned long xenheap_phys_end; extern unsigned long frametable_virt_end; #endif =20 --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667556552; cv=pass; d=zohomail.com; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:24.5669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49cba82c-d5a0-4d74-0d69-08dabe4c82c0 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9441 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556554683100007 Content-Type: text/plain; charset="utf-8" domain_build use ioremap_wc to map a new non-cacheable virtual address for initrd. After Xen copy initrd from this address to guest, this new allocated virtual address has not been unmapped. So in this patch, we add an iounmap to the end of domain_build, after Xen loaded initrd to guest memory. Signed-off-by: Wei Chen --- xen/arch/arm/domain_build.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 4fb5c20b13..bd30d3798c 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -3418,6 +3418,8 @@ static void __init initrd_load(struct kernel_info *ki= nfo) initrd, len); if ( res !=3D 0 ) panic("Unable to copy the initrd in the hwdom memory\n"); + + iounmap(initrd); } =20 /* --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667556551; cv=pass; d=zohomail.com; s=zohoarc; b=b6DKyY4UfEqU9NOAY+PMLCCBDHmvrWGF1cRHkDjjikJZQ48PQXM7aG7LORYs/f4FeaRYA/uFjG0TWyfiYkohfCVziXhA8GSaEI+T9ZQV/R/jKJ34lnVjAUzD+IlnR2txQvHnrg+CB6ho2S3boIhC1VTsmbxulfrrTrBSzfzmzFw= ARC-Message-Signature: i=3; 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helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v6 03/11] xen/arm: disable EFI boot services for MPU systems Date: Fri, 4 Nov 2022 18:07:33 +0800 Message-ID: <20221104100741.2176307-4-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT061:EE_|AS8PR08MB6437:EE_|DBAEUR03FT032:EE_|AS2PR08MB9716:EE_ X-MS-Office365-Filtering-Correlation-Id: 169d4642-7c36-446c-35ac-08dabe4c8551 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 34qvEV9wGeLGeLvvUPLKo1q+sKqe9UlPIeI1vG2DPmIMyXA4JJqS72wQfZjkFdBZsCinr39sze20ILUMfJAP9Rumec4bdiHGCAz4uMI0U9+uRPpX30HdPo0B+4R3UclS4O7/WnzNjxg3xaxJHGazKri6SRWGqaLJ9ko5SB9Y5o/71OAU1pvfRTiO0iSVrcc6H0rT9ruwiKlqRzaT+OCLvcwOqDCrvXeH/6iE5A8zxyQMOZ+oVlviHj6xUuS++MbezRbhM3xkpnJ54f8bZpgT+xEBYvxwMUghZd5aEPt64+hW+yFcj1rVToQrPtsQtPBiojORHAsBZRjDidSgqdefHQaGzs4SYukBI6K5cpdRQFeKGF13TwmLKmC/KYOH7Zt3V2/S8lvCeaIfaZUl3OPI4I/gWIi2+7UgCNlkE3orohuls7b8k1kr3vqPUS4llpD0XSHVKHbKW3ByfgiP9vlg2O5Kq0N+RF1Pg6Fwg3SuF9p1Heqx6IhbgngYZzagSRPcW1kYn0/1OmkmxkCtD6nKhFzg5CdFLgNCk2pwwpo7xf7KMWj/JBWClrFHP9OlvkpvkDVpG/V/mDU/5geYbb/IAy5CEKfV4NJEGGXNzzb4UCehxSNUEGeqAHkAwHnpU30dbNR6mi6uZqH0+8x13XngEmZOC1ppvc7Zc6tTJ59bGLbNCWhyXuHPPIX29rk4ZKra3WuGBBxxY91Lj2eJmz9esbGoS0SrcRn2RxPGTZvEhXWY/KlPEuo9iM3Ag+fbhDWy/kMb4nv294WkHCr7CuHM15hSS9gnIy86FItCAUO+/1pkgfWXAjasWaE2Z9Dt6Obp X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199015)(40470700004)(36840700001)(46966006)(356005)(40480700001)(81166007)(36756003)(40460700003)(8676002)(86362001)(82310400005)(41300700001)(26005)(70206006)(4326008)(70586007)(2616005)(186003)(8936002)(5660300002)(44832011)(336012)(478600001)(1076003)(7696005)(54906003)(6666004)(6916009)(36860700001)(316002)(82740400003)(2906002)(426003)(47076005)(83380400001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:28.9674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 169d4642-7c36-446c-35ac-08dabe4c8551 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9716 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556552841100002 Content-Type: text/plain; charset="utf-8" Current EFI boot services support of Arm64 could not work well for Armv8-R64 system that only has MPU in EL2. That is because EFI boot services may need some relocation support or partial PIE/PIC support. But these will not be supported in the initial stage of porting Xen to MPU systems. So in this patch, we disable EFI boot services support for Arm MPU systems. Signed-off-by: Wei Chen --- xen/arch/arm/Kconfig | 2 +- xen/arch/arm/arm64/head.S | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 1fe5faf847..ad592367bd 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -7,7 +7,7 @@ config ARM_64 def_bool y depends on !ARM_32 select 64BIT - select ARM_EFI + select ARM_EFI if !HAS_MPU select HAS_FAST_MULTIPLY =20 config ARM diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index ad014716db..ccedf20dc7 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -172,8 +172,10 @@ efi_head: .byte 0x52 .byte 0x4d .byte 0x64 - .long pe_header - efi_head /* Offset to the PE header. */ - +#ifndef CONFIG_ARM_EFI + .long 0 /* 0 means no PE header. */ +#else + .long pe_header - efi_head /* Offset to the PE header. */ /* * Add the PE/COFF header to the file. The address of this header * is at offset 0x3c in the file, and is part of Linux "Image" @@ -279,6 +281,8 @@ section_table: .short 0 /* NumberOfLineNumbers (0 for executable= s) */ .long 0xe0500020 /* Characteristics (section flags) */ .align 5 +#endif /* CONFIG_ARM_EFI */ + real_start: /* BSS should be zeroed when booting without EFI */ mov x26, #0 /* x26 :=3D skip_zero_bss */ --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667556555; cv=pass; d=zohomail.com; s=zohoarc; b=m1aBroYWJDXIIkWRMhFnW2xSdkosjgqqToQgiu4YyxTomKx6NgL94lhCmAeY/VabiCJLsiuld6qFXKnBK0WwO0Xfibm5e/k+3W0PMfPFZU8Nmn/1k0C/8H1gogzV72sFngVcuyEYCWlIs0kLAYmq9GVCba1VDl51CCeHzQXVF+c= ARC-Message-Signature: i=3; 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helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v6 04/11] xen/arm: adjust Xen TLB helpers for Armv8-R64 PMSA Date: Fri, 4 Nov 2022 18:07:34 +0800 Message-ID: <20221104100741.2176307-5-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT052:EE_|AM0PR08MB5522:EE_|AM7EUR03FT029:EE_|VI1PR08MB5375:EE_ X-MS-Office365-Filtering-Correlation-Id: fa237cae-570c-42c6-d5bb-08dabe4c8714 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 52V1vIbZmYLVBrv5egf7M+GbZZrGJrnIV33m03ena2tSfgVqqqHYcf43koFBeaBHBk6ch10RzRo40eUDYjVvCHYmbGLDzaZgVAz4WX4MNyIf+Yfg2whTa2OrMoII5JlMoqaoqiwR/LI0T+PD/NM2H3+qwL6Y9V1eqRRL7rC4Zr7Vzyxb3alxZt7D3OP7PLTJS6ZtUTuQSiOijs1kKVNCbZgZ7Ksqf9wjj5mmuFzs8ILG2ucumc1PuipHKHIX+ib2e9fQHOaH9Ot3lMJ5cuYK0j29wx89cnUcM11rbqlHEI+9eJevI7sGqFzmQdOGizSGBReoPVDeIFfoyGgZH2s0TZeH/PpBLu5DbooQDHX8KjnOlEJJNFhDG3LmETbc9M6nBPR+kizCmMbGqooQqFZ1EQVSIbzXvcRuUdcf/DkgpBqfdTX77h6uOz1dc4bVqOtQ9EyfUhcW5RLYbx2wSdIXYWEGKYWXuhCqY+n0cHJCSEfHuFGQAepzsRLmWxxauGDpeStJWXolxzgEvYYVEBYa3VL/XrxalaiX1LEqtUusHHgAgj1WlncXZaaXuy9c4ALx5KGg7q47qQrS82Y6A61vOj6FHkd5XV9/vfE0rn7dplkLNf7nbtD7azIYJqxU2/MJHbvWxklq5uShJmqHAtlgO+aUNQDMmdSW2BXjHbon+qcfCaHcMvNH1ywn0lWLMh7lXfQU6K8+7GvSdYLWiIZGktJCaZID1+ZRnlYkv5aTzDv76PExl0RG9hP9zQNmN9D+b8yl8P9t59CPOHh9qYDg48dk1oV2MkZSRV9aBPgG7Sp1+wITUYc0Yrm5y0gnL9aAoUMrXxBg8mTfsY09bdSGEg== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(346002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(4326008)(8676002)(26005)(70206006)(70586007)(6916009)(316002)(54906003)(36756003)(6666004)(8936002)(41300700001)(966005)(478600001)(86362001)(7696005)(47076005)(44832011)(5660300002)(1076003)(356005)(81166007)(186003)(82740400003)(82310400005)(83380400001)(426003)(40480700001)(40460700003)(336012)(36860700001)(2616005)(2906002)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:31.7084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa237cae-570c-42c6-d5bb-08dabe4c8714 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT029.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB5375 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556556735100011 Content-Type: text/plain; charset="utf-8" From Arm ARM Supplement of Armv8-R AArch64 (DDI 0600A) [1], section D1.6.2 TLB maintenance instructions. We know that Armv8-R AArch64 permits an implementation to cache stage 1 VMSAv8-64 and stage 2 PMSAv8-64 attributes as a common entry for the Secure EL1&0 translation regime. But for Xen itself, it's running with stage 1 PMSAv8-64 on Armv8-R AArch64. The EL2 MPU updates for stage1 PMSAv8-64 will not be cached in TLB entries. So we don't need any TLB invalidation for Xen itself in EL2. So in this patch, we use empty macros to stub Xen TLB helpers for MPU system (PMSA), but still keep the Guest TLB helpers. Because when a guest running in EL1 with VMSAv8-64 (MMU), guest TLB invalidation is still needed. But we need some policy to distinguish MPU and MMU guest, this will be done in guest support of Armv8-R64 later. [1] https://developer.arm.com/documentation/ddi0600/ac Signed-off-by: Wei Chen --- xen/arch/arm/include/asm/arm64/flushtlb.h | 25 +++++++++++++++++++++++ xen/arch/arm/include/asm/flushtlb.h | 22 ++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/inclu= de/asm/arm64/flushtlb.h index 7c54315187..fe445f6831 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -51,6 +51,8 @@ TLB_HELPER(flush_all_guests_tlb_local, alle1); /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ TLB_HELPER(flush_all_guests_tlb, alle1is); =20 +#ifndef CONFIG_HAS_MPU + /* Flush all hypervisor mappings from the TLB of the local processor. */ TLB_HELPER(flush_xen_tlb_local, alle2); =20 @@ -66,6 +68,29 @@ static inline void __flush_xen_tlb_one(vaddr_t va) asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); } =20 +#else + +/* + * When Xen is running with stage 1 PMSAv8-64 on MPU systems. The EL2 MPU + * updates for stage1 PMSAv8-64 will not be cached in TLB entries. So we + * don't need any TLB invalidation for Xen itself in EL2. See Arm ARM + * Supplement of Armv8-R AArch64 (DDI 0600A), section D1.6.2 TLB maintenan= ce + * instructions for more details. + */ +static inline void flush_xen_tlb_local(void) +{ +} + +static inline void __flush_xen_tlb_one_local(vaddr_t va) +{ +} + +static inline void __flush_xen_tlb_one(vaddr_t va) +{ +} + +#endif /* CONFIG_HAS_MPU */ + #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/arch/arm/include/asm/flushtlb.h b/xen/arch/arm/include/asm= /flushtlb.h index 125a141975..4b8bf65281 100644 --- a/xen/arch/arm/include/asm/flushtlb.h +++ b/xen/arch/arm/include/asm/flushtlb.h @@ -28,6 +28,7 @@ static inline void page_set_tlbflush_timestamp(struct pag= e_info *page) /* Flush specified CPUs' TLBs */ void arch_flush_tlb_mask(const cpumask_t *mask); =20 +#ifndef CONFIG_HAS_MPU /* * Flush a range of VA's hypervisor mappings from the TLB of the local * processor. @@ -66,6 +67,27 @@ static inline void flush_xen_tlb_range_va(vaddr_t va, isb(); } =20 +#else + +/* + * When Xen is running with stage 1 PMSAv8-64 on MPU systems. The EL2 MPU + * updates for stage1 PMSAv8-64 will not be cached in TLB entries. So we + * don't need any TLB invalidation for Xen itself in EL2. See Arm ARM + * Supplement of Armv8-R AArch64 (DDI 0600A), section D1.6.2 TLB maintenan= ce + * instructions for more details. + */ +static inline void flush_xen_tlb_range_va_local(vaddr_t va, + unsigned long size) +{ +} + +static inline void flush_xen_tlb_range_va(vaddr_t va, + unsigned long size) +{ +} + +#endif /* CONFIG_HAS_MPU */ + #endif /* __ASM_ARM_FLUSHTLB_H__ */ /* * Local variables: --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667556554; cv=pass; d=zohomail.com; s=zohoarc; b=IZtZq3QzT3oGsmz2x6c55PGpLND7YjxwZJW5fJX7nhMJnqlQhUEGVLGTZzAOMg7kN+0UkFKnjlXCm/WvO82ld5ryEUDNrTFFjDdlvGKRVHguIQZ84sZzjA+uXHgl9CibxNM3jvJ8/7xDbMV4tce8JngbPJxz02GgMnQA3vICvhY= ARC-Message-Signature: i=3; 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helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , "Jiamei . Xie" Subject: [PATCH v6 05/11] xen/arm: define Xen start address for FVP BaseR platform Date: Fri, 4 Nov 2022 18:07:35 +0800 Message-ID: <20221104100741.2176307-6-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT052:EE_|AM8PR08MB6625:EE_|AM7EUR03FT016:EE_|AM9PR08MB6290:EE_ X-MS-Office365-Filtering-Correlation-Id: e964fb75-088f-4d55-d02d-08dabe4c88a4 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: bLT+mUdP00z4e1w4SDyK1mGpcABic/E8OlPFhZTAoLxpxhSlAUqiXmHz88uYzrStFZsu17+ulICo32L5neteH4s5Rajnk9Y1zaBU4GXBgom3YN6R6tlkqqfGXQptu8nTqpUkbIeA79QG/bFA1jaqI9YBP4n5vMcDIfIYrjCaLTgutMBDZDFxqkZCtSM0ZhrhGQlffO+iLI4RwB4jRRDcROJ0fJQkqAIvib9qln1DxwBT40tY2VB+10aHMunXipKcu4rxyHqK6V1dP59TzX08cjjkcwB2JyUzBtgmqem1cAArb7Q5f+a4MaELzvpXMW3KsS6pIg+8t+FKCcbVuK+tzrN/R6l5sXB5xKNvBR6l0EW8vtNjztLBxCWfhsiChJvCuudAeqOasdR/naOpctDuFfF51xrVmo//HuYpBqpQ1blk6mTclWw9RWBxq+8owUF9Ve2fduGf6lbAESLIZ8x+9oekRejM2CbLV0VYPB7c584LMy+P9oufidxzOgCq5SKq31UcR2+FI8BMqE+GM5CWoS7zz7oRgEjEsjt1dpo18d47vA4vJ4spvMHcF8GO38oGWtFJUBMT55wcNwH/MMXusbzwpQAc/ilIKrAOJ8Z8t3cVL/Nk5SOtbDb+qcdaGBceXNemD8Fi1T/EX7/2KeUYUEKhxA6sAgME3vZX/ti6SBAGps0LjlVC2KpoTU/irFnhc2RoA/Bh/lwEkje0uOoD6bRUU6fcjNzXPIsSHcirlRAxq3a/DHS8+K6YW/CKOxKaL+vev/bMRPPqQqKpFEX/gWKNpAbBZeEKhPJ2lMlD5iQ46PrianQ2u416yhZH6db/ X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199015)(36840700001)(40470700004)(46966006)(426003)(336012)(36860700001)(86362001)(36756003)(356005)(81166007)(82740400003)(83380400001)(47076005)(1076003)(7696005)(26005)(6666004)(478600001)(6916009)(54906003)(70586007)(4326008)(70206006)(41300700001)(8676002)(316002)(44832011)(2906002)(5660300002)(8936002)(186003)(82310400005)(2616005)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB6625 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 7a229894-52fa-4d08-452f-08dabe4c8334 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gYZ0FhS1PzsfWPBS4Gbgve6nNG/O5e48GX+zgeiVC2JBp3TpeM8DAr5qmxgot+uJF3XUlVp1gMbUFergOgtbE6jTY2tbRRR2mUKLXl5tYeevyCKYoj2SS2kRIxoMUDHH7pUaH0AcP9R6+hWxPuM4qCpc2+eGjLb2ihXhGc6GElZjXG7LShtUJsPW3xErSI2asLlfTBvwpmT1vTYS/gOOWkrC1HrCdqKBmjtDJXyoXJXSQGK/CfeXSQjpx8EHLqnRXFK7T1kFVTXJzdPmuKXs/Q5fed8+Jxz2R5S3+P3OuM69y1wCVBpLDJGTezi0tiG0bFFx+IrlwdWD+p5b5RkgeDDX7+sMJgqnldj9R/V3Wi95wmioIjZB3RE7FTeqrcO94H9/Sc1qbXBJfLpUSp0oz4VW+OLtsPs6Ql5r6AqPt0XYX0nki6kXtyrm71OV6DphDm31oJn1dU2s2muk/Ul1D0DiFyXjqdzsT1JPM7JKiwHJk4LCbz6flAlSeP6a4zjAbvCUIyddwjgSs8c2Eswm3P1IvMr0CXcNY6iVvJhMT+BlyHurvCFz4j/JgZDtJ+EjCbd/iuaKGwPpns0+f9KM/Og7JywUegg2UyYri5uQ9wScA7ybGcvLHGEDjunfg6LVIeSBaOyjy5xqPzeljmttfFxUS+D2qXiABZvLNInN7t6Pnli2L8fAV/G/5YmpyzKt3zrB/xCtNgDMQ602i73GvGWlBOrzwHplKHfBdEKVXq9iMGKjM0oQC5BpUV0Af9BHIBnactqxUykhLeP1fC5wUQ== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(39860400002)(346002)(451199015)(36840700001)(40470700004)(46966006)(81166007)(82740400003)(478600001)(36860700001)(82310400005)(44832011)(336012)(70586007)(1076003)(5660300002)(70206006)(186003)(40460700003)(4326008)(8676002)(2616005)(54906003)(83380400001)(6916009)(6666004)(7696005)(47076005)(426003)(86362001)(2906002)(36756003)(26005)(8936002)(41300700001)(316002)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:34.5016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e964fb75-088f-4d55-d02d-08dabe4c88a4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6290 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556554719100008 Content-Type: text/plain; charset="utf-8" On Armv8-A, Xen has a fixed virtual start address (link address too) for all Armv8-A platforms. In an MMU based system, Xen can map its loaded address to this virtual start address. So, on Armv8-A platforms, the Xen start address does not need to be configurable. But on Armv8-R platforms, there is no MMU to map loaded address to a fixed virtual address and different platforms will have very different address space layout. So Xen cannot use a fixed physical address on MPU based system and need to have it configurable. So in this patch, we reuse the existing arm/platforms to store Armv8-R platforms' parameters. And `XEN_START_ADDRESS` is one kind of FVP BaseR platform's parameters. So we define default `XEN_START_ADDRESS` for FVP BaseR in its platform file. We also introduce one Kconfig option for users to override the default Xen start address of selected platform, if they think the default address doesn't suit their scenarios. For this Kconfig option, we use an unaligned address "0xffffffff" as the default value to indicate that users haven't used a customized Xen start address. And as we introduced Armv8-R platforms to Xen, that means the existed Arm64 platforms should not be listed in Armv8-R platform list, so we add !ARM_V8R dependency for these platforms. Signed-off-by: Wei Chen Signed-off-by: Jiamei.Xie --- xen/arch/arm/Kconfig | 11 +++++++++++ xen/arch/arm/include/asm/platforms/fvp_baser.h | 14 ++++++++++++++ xen/arch/arm/platforms/Kconfig | 16 +++++++++++++--- 3 files changed, 38 insertions(+), 3 deletions(-) create mode 100644 xen/arch/arm/include/asm/platforms/fvp_baser.h diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index ad592367bd..ac276307d6 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -138,6 +138,17 @@ config TEE This option enables generic TEE mediators support. It allows guests to access real TEE via one of TEE mediators implemented in XEN. =20 +config XEN_START_ADDRESS + hex "Xen start address: keep default to use platform defined address" + default 0xFFFFFFFF + depends on HAS_MPU + help + This option allows to set the customized address at which Xen will be + linked on MPU systems. This address must be aligned to a page size. + Use 0xFFFFFFFF as the default value to indicate that user hasn't + customized this address, and Xen use use the default value that has + been defined in platform files. + source "arch/arm/tee/Kconfig" =20 config STATIC_SHM diff --git a/xen/arch/arm/include/asm/platforms/fvp_baser.h b/xen/arch/arm/= include/asm/platforms/fvp_baser.h new file mode 100644 index 0000000000..9450a411a9 --- /dev/null +++ b/xen/arch/arm/include/asm/platforms/fvp_baser.h @@ -0,0 +1,14 @@ +#ifndef __ASM_ARM_PLATFORMS_FVP_BASER_H__ +#define __ASM_ARM_PLATFORMS_FVP_BASER_H__ + +/* + * 0xFFFFFFFF indicates users haven't customized XEN_START_ADDRESS, + * we will use platform defined default address. + */ +#if CONFIG_XEN_START_ADDRESS =3D=3D 0xFFFFFFFF +#define XEN_START_ADDRESS 0x200000 +#else +#define XEN_START_ADDRESS CONFIG_XEN_START_ADDRESS +#endif + +#endif /* __ASM_ARM_PLATFORMS_FVP_BASER_H__ */ diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig index c93a6b2756..0904793a0b 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -1,6 +1,7 @@ choice prompt "Platform Support" default ALL_PLAT + default FVP_BASER if ARM_V8R ---help--- Choose which hardware platform to enable in Xen. =20 @@ -8,13 +9,14 @@ choice =20 config ALL_PLAT bool "All Platforms" + depends on !ARM_V8R ---help--- Enable support for all available hardware platforms. It doesn't automatically select any of the related drivers. =20 config QEMU bool "QEMU aarch virt machine support" - depends on ARM_64 + depends on ARM_64 && !ARM_V8R select GICV3 select HAS_PL011 ---help--- @@ -23,7 +25,7 @@ config QEMU =20 config RCAR3 bool "Renesas RCar3 support" - depends on ARM_64 + depends on ARM_64 && !ARM_V8R select HAS_SCIF select IPMMU_VMSA ---help--- @@ -31,14 +33,22 @@ config RCAR3 =20 config MPSOC bool "Xilinx Ultrascale+ MPSoC support" - depends on ARM_64 + depends on ARM_64 && !ARM_V8R select HAS_CADENCE_UART select ARM_SMMU ---help--- Enable all the required drivers for Xilinx Ultrascale+ MPSoC =20 +config FVP_BASER + bool "Fixed Virtual Platform BaseR support" + depends on ARM_V8R + help + Enable platform specific configurations for Fixed Virtual + Platform BaseR + config NO_PLAT bool "No Platforms" + depends on !ARM_V8R ---help--- Do not enable specific support for any platform. =20 --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:40.3412 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04129640-a6d0-4e2e-420a-08dabe4c8c22 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT036.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR08MB5334 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556564805100001 Content-Type: text/plain; charset="utf-8" Xen defines some global configuration macros for Arm in config.h. We still want to use it for Armv8-R systems, but there are some address related macros that are defined for MMU systems. These macros will not be used by MPU systems, Adding ifdefery with CONFIG_HAS_MPU to gate these macros will result in a messy and hard to read/maintain code. So we keep some common definitions still in config.h, but move virtual address related definitions to a new file - config_mmu.h. And use a new file config_mpu.h to store definitions for MPU systems. To avoid spreading #ifdef everywhere, we keep the same definition names for MPU systems, like XEN_VIRT_START and HYPERVISOR_VIRT_START, but the definition contents are MPU specific. Signed-off-by: Wei Chen --- xen/arch/arm/include/asm/config.h | 97 +-------------------- xen/arch/arm/include/asm/config_mmu.h | 119 ++++++++++++++++++++++++++ xen/arch/arm/include/asm/config_mpu.h | 27 ++++++ 3 files changed, 150 insertions(+), 93 deletions(-) create mode 100644 xen/arch/arm/include/asm/config_mmu.h create mode 100644 xen/arch/arm/include/asm/config_mpu.h diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/c= onfig.h index 25a625ff08..189e932605 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -71,99 +71,10 @@ #include #include =20 -/* - * Common ARM32 and ARM64 layout: - * 0 - 2M Unmapped - * 2M - 4M Xen text, data, bss - * 4M - 6M Fixmap: special-purpose 4K mapping slots - * 6M - 10M Early boot mapping of FDT - * 10M - 12M Livepatch vmap (if compiled in) - * - * ARM32 layout: - * 0 - 12M - * - * 32M - 128M Frametable: 24 bytes per page for 16GB of RAM - * 256M - 1G VMAP: ioremap and early_ioremap use this virtual address - * space - * - * 1G - 2G Xenheap: always-mapped memory - * 2G - 4G Domheap: on-demand-mapped - * - * ARM64 layout: - * 0x0000000000000000 - 0x0000007fffffffff (512GB, L0 slot [0]) - * 0 - 12M - * - * 1G - 2G VMAP: ioremap and early_ioremap - * - * 32G - 64G Frametable: 24 bytes per page for 5.3TB of RAM - * - * 0x0000008000000000 - 0x00007fffffffffff (127.5TB, L0 slots [1..255]) - * Unused - * - * 0x0000800000000000 - 0x000084ffffffffff (5TB, L0 slots [256..265]) - * 1:1 mapping of RAM - * - * 0x0000850000000000 - 0x0000ffffffffffff (123TB, L0 slots [266..511]) - * Unused - */ - -#define XEN_VIRT_START _AT(vaddr_t,0x00200000) -#define FIXMAP_ADDR(n) (_AT(vaddr_t,0x00400000) + (n) * PAGE_SIZE) - -#define BOOT_FDT_VIRT_START _AT(vaddr_t,0x00600000) -#define BOOT_FDT_VIRT_SIZE _AT(vaddr_t, MB(4)) - -#ifdef CONFIG_LIVEPATCH -#define LIVEPATCH_VMAP_START _AT(vaddr_t,0x00a00000) -#define LIVEPATCH_VMAP_SIZE _AT(vaddr_t, MB(2)) -#endif - -#define HYPERVISOR_VIRT_START XEN_VIRT_START - -#ifdef CONFIG_ARM_32 - -#define CONFIG_SEPARATE_XENHEAP 1 - -#define FRAMETABLE_VIRT_START _AT(vaddr_t,0x02000000) -#define FRAMETABLE_SIZE MB(128-32) -#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) -#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - = 1) - -#define VMAP_VIRT_START _AT(vaddr_t,0x10000000) -#define VMAP_VIRT_SIZE _AT(vaddr_t, GB(1) - MB(256)) - -#define XENHEAP_VIRT_START _AT(vaddr_t,0x40000000) -#define XENHEAP_VIRT_SIZE _AT(vaddr_t, GB(1)) - -#define DOMHEAP_VIRT_START _AT(vaddr_t,0x80000000) -#define DOMHEAP_VIRT_SIZE _AT(vaddr_t, GB(2)) - -#define DOMHEAP_ENTRIES 1024 /* 1024 2MB mapping slots */ - -/* Number of domheap pagetable pages required at the second level (2MB map= pings) */ -#define DOMHEAP_SECOND_PAGES (DOMHEAP_VIRT_SIZE >> FIRST_SHIFT) - -#else /* ARM_64 */ - -#define SLOT0_ENTRY_BITS 39 -#define SLOT0(slot) (_AT(vaddr_t,slot) << SLOT0_ENTRY_BITS) -#define SLOT0_ENTRY_SIZE SLOT0(1) - -#define VMAP_VIRT_START GB(1) -#define VMAP_VIRT_SIZE GB(1) - -#define FRAMETABLE_VIRT_START GB(32) -#define FRAMETABLE_SIZE GB(32) -#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) - -#define DIRECTMAP_VIRT_START SLOT0(256) -#define DIRECTMAP_SIZE (SLOT0_ENTRY_SIZE * (265-256)) -#define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE - 1) - -#define XENHEAP_VIRT_START directmap_virt_start - -#define HYPERVISOR_VIRT_END DIRECTMAP_VIRT_END - +#ifdef CONFIG_HAS_MPU +#include +#else +#include #endif =20 #define NR_hypercalls 64 diff --git a/xen/arch/arm/include/asm/config_mmu.h b/xen/arch/arm/include/a= sm/config_mmu.h new file mode 100644 index 0000000000..444223f4a1 --- /dev/null +++ b/xen/arch/arm/include/asm/config_mmu.h @@ -0,0 +1,119 @@ +/*************************************************************************= ***** + * config_mmu.h + * + * A Linux-style configuration list, only can be included by config.h + */ + +#ifndef __ARM_CONFIG_MMU_H__ +#define __ARM_CONFIG_MMU_H__ + +/* + * Common ARM32 and ARM64 layout: + * 0 - 2M Unmapped + * 2M - 4M Xen text, data, bss + * 4M - 6M Fixmap: special-purpose 4K mapping slots + * 6M - 10M Early boot mapping of FDT + * 10M - 12M Livepatch vmap (if compiled in) + * + * ARM32 layout: + * 0 - 12M + * + * 32M - 128M Frametable: 24 bytes per page for 16GB of RAM + * 256M - 1G VMAP: ioremap and early_ioremap use this virtual address + * space + * + * 1G - 2G Xenheap: always-mapped memory + * 2G - 4G Domheap: on-demand-mapped + * + * ARM64 layout: + * 0x0000000000000000 - 0x0000007fffffffff (512GB, L0 slot [0]) + * 0 - 12M + * + * 1G - 2G VMAP: ioremap and early_ioremap + * + * 32G - 64G Frametable: 24 bytes per page for 5.3TB of RAM + * + * 0x0000008000000000 - 0x00007fffffffffff (127.5TB, L0 slots [1..255]) + * Unused + * + * 0x0000800000000000 - 0x000084ffffffffff (5TB, L0 slots [256..265]) + * 1:1 mapping of RAM + * + * 0x0000850000000000 - 0x0000ffffffffffff (123TB, L0 slots [266..511]) + * Unused + */ + +#define XEN_VIRT_START _AT(vaddr_t,0x00200000) +#define FIXMAP_ADDR(n) (_AT(vaddr_t,0x00400000) + (n) * PAGE_SIZE) + +#define BOOT_FDT_VIRT_START _AT(vaddr_t,0x00600000) +#define BOOT_FDT_VIRT_SIZE _AT(vaddr_t, MB(4)) + +#ifdef CONFIG_LIVEPATCH +#define LIVEPATCH_VMAP_START _AT(vaddr_t,0x00a00000) +#define LIVEPATCH_VMAP_SIZE _AT(vaddr_t, MB(2)) +#endif + +#define HYPERVISOR_VIRT_START XEN_VIRT_START + +#ifdef CONFIG_ARM_32 + +#define CONFIG_SEPARATE_XENHEAP 1 + +#define FRAMETABLE_VIRT_START _AT(vaddr_t,0x02000000) +#define FRAMETABLE_SIZE MB(128-32) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - = 1) + +#define VMAP_VIRT_START _AT(vaddr_t,0x10000000) +#define VMAP_VIRT_SIZE _AT(vaddr_t, GB(1) - MB(256)) + +#define XENHEAP_VIRT_START _AT(vaddr_t,0x40000000) +#define XENHEAP_VIRT_SIZE _AT(vaddr_t, GB(1)) + +#define DOMHEAP_VIRT_START _AT(vaddr_t,0x80000000) +#define DOMHEAP_VIRT_SIZE _AT(vaddr_t, GB(2)) + +#define DOMHEAP_ENTRIES 1024 /* 1024 2MB mapping slots */ + +/* Number of domheap pagetable pages required at the second level (2MB map= pings) */ +#define DOMHEAP_SECOND_PAGES (DOMHEAP_VIRT_SIZE >> FIRST_SHIFT) + +#else /* ARM_64 */ + +#define SLOT0_ENTRY_BITS 39 +#define SLOT0(slot) (_AT(vaddr_t,slot) << SLOT0_ENTRY_BITS) +#define SLOT0_ENTRY_SIZE SLOT0(1) + +#define VMAP_VIRT_START GB(1) +#define VMAP_VIRT_SIZE GB(1) + +#define FRAMETABLE_VIRT_START GB(32) +#define FRAMETABLE_SIZE GB(32) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) + +#define DIRECTMAP_VIRT_START SLOT0(256) +#define DIRECTMAP_SIZE (SLOT0_ENTRY_SIZE * (265-256)) +#define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE - 1) + +#define XENHEAP_VIRT_START directmap_virt_start + +#define HYPERVISOR_VIRT_END DIRECTMAP_VIRT_END + +#endif + +/* Fixmap slots */ +#define FIXMAP_CONSOLE 0 /* The primary UART */ +#define FIXMAP_MISC 1 /* Ephemeral mappings of hardware */ +#define FIXMAP_ACPI_BEGIN 2 /* Start mappings of ACPI tables */ +#define FIXMAP_ACPI_END (FIXMAP_ACPI_BEGIN + NUM_FIXMAP_ACPI_PAGES - 1)= /* End mappings of ACPI tables */ + +#endif /* __ARM_CONFIG_MMU_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/config_mpu.h b/xen/arch/arm/include/a= sm/config_mpu.h new file mode 100644 index 0000000000..530abb8302 --- /dev/null +++ b/xen/arch/arm/include/asm/config_mpu.h @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * config_mpu.h: A Linux-style configuration list for Arm MPU systems, + * only can be included by config.h + */ + +#ifndef __ARM_CONFIG_MPU_H__ +#define __ARM_CONFIG_MPU_H__ + +#ifdef CONFIG_FVP_BASER +#include +#endif + +/* + * All MPU platforms need to provide a XEN_START_ADDRESS for linker. This + * address indicates where Xen image will be loaded and run from. This + * address must be aligned to a PAGE_SIZE. + */ +#if (XEN_START_ADDRESS % PAGE_SIZE) !=3D 0 +#error "XEN_START_ADDRESS must be aligned to PAGE_SIZE" +#endif + +#define XEN_VIRT_START _AT(paddr_t, XEN_START_ADDRESS) + +#define HYPERVISOR_VIRT_START XEN_VIRT_START + +#endif /* __ARM_CONFIG_MPU_H__ */ --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667556570; cv=pass; d=zohomail.com; s=zohoarc; b=EiVXE7nZ/GfMAvPLoXbi9l4DdejYBasWKK2UhczqRs24YbLMiZVygKfqDjj9VbInq3KIOe4+9YG4O1eMQBNdymfQ1dN61CuX7hu0upMDDTAACyGq0HhHzxrV3LcLMxsSMaW0z+elt6V1ja4CyDZeaeRDo58y8cC6jRUvF3LAUdE= ARC-Message-Signature: i=3; a=rsa-sha256; c=relaxed/relaxed; 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helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v6 07/11] xen/arm: implement FIXMAP_ADDR for MPU systems Date: Fri, 4 Nov 2022 18:07:37 +0800 Message-ID: <20221104100741.2176307-8-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT052:EE_|PA4PR08MB7434:EE_|AM7EUR03FT042:EE_|GV1PR08MB8179:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b1f7ead-8183-49c6-8e95-08dabe4c8c09 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: SDsgSV5MLhJSMBhVKO/b/g+CH6oIhhIn729JH6MXL6Vphlts7Pqyqe3Gj3hVCaGA2y49170DA0TpEuzdsCkM7YiV8Z4HyFYHQ7QLwuM6qkOA9W/92a7fnM0YMOeku3yYgMOrnlfrQa/EnI3z/1Sc0Kf+LUWLZnySUqkMQCnrNbnOboN30lWeNGKhgUC/D1tzFRHCemzibCdYCdlDP1wQ+iXoBu6YoYBskQD3kjLQfGRsJsA/xXQLLwStZuYwYesc3HO/D9GpkrQUWtcD8veOuGQdCkqP5m32AZNdvXCT0ygaKbE6N718SIxm50d3aH0S2CZaqlXYak8kSKF71n0NNfhe40XWDxHn4jHcQwTGeLDyyVcoQrraK0PxjmmS5Of61v4V/oWwFq7ndd7xH5qqEthq2PuyiKlEuvqVIeqzrS13Zzs6ues0CyjfyS+oPHSlze5dWWDRofqOfd5w1e0NOZch9q9DORBQO2FqjvoNlbTyKL1ouA+Jb488iMxKsT49O31cdTw5ECNSOb8Ot/qejXea/d4ZUwirrKehoXi5AhIMYTh0GC97VPHaIulD7V5O/nn0nAnfO6I6LOWwk4pdjSyrlMyHNNIXubTDhLHuiAqkOlIWPGiSV2ftxON44dTDwbQKESufuS2qJgp5Nuyo/7iTKPg2WHnCp6rrVQOuAnqYYHxivg4nZPj3yBiAly/EmQAq+sW0bDqdlDn7hqW2uhOw9SIU6pBj4bqlQo1P96KACdJE+JwruQ6rn67UWgwWHe9+gJABXm048uOjERa5gwNwZIxAPPziBvYmw8aT2V4BQgXJnAALVJeHq1pGhN0+ X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199015)(40470700004)(36840700001)(46966006)(47076005)(478600001)(426003)(316002)(336012)(44832011)(6666004)(70586007)(1076003)(70206006)(8676002)(40460700003)(2616005)(186003)(5660300002)(4326008)(36860700001)(2906002)(82310400005)(54906003)(6916009)(83380400001)(82740400003)(356005)(36756003)(41300700001)(81166007)(8936002)(7696005)(86362001)(40480700001)(26005)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:40.2106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b1f7ead-8183-49c6-8e95-08dabe4c8c09 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB8179 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556570869100001 Content-Type: text/plain; charset="utf-8" FIXMAP is a special virtual address section for Xen to map some physical ram or device memory temporarily in initialization for MMU systems. FIXMAP_ADDR will return a virtual address by index for special purpose phys-to-virt mapping usage. For example, FIXMAP_ADDR(FIXMAP_CONSOLE) for early console mapping and FIXMAP_ADDR(FIXMAP_MISC) for copy_from_paddr. But in MPU systems, we can't map physical address to any virtual address. So we want the code that is using FIXMAP_ADDR to return the input physical address in MPU systems. So in MPU version, FIXMAP_ADDR will trim physical address to PAGE alignment. This will return an offset which is similar to MMU version FIXMAP_ADDR. But it's a physical offset got from input physical address, plus to an offset inside page (which is also got from physical address mask with PAGE_MASK). The caller can return the input physical address directly. As pmap depends on FIXAMP, so we disable pmap for Arm with MPU enabled systems. Signed-off-by: Wei Chen --- xen/arch/arm/Kconfig | 2 +- xen/arch/arm/include/asm/config_mpu.h | 2 ++ xen/arch/arm/include/asm/fixmap.h | 25 +++++++++++++++++++++++++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index ac276307d6..1458ffa777 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -16,7 +16,7 @@ config ARM select HAS_DEVICE_TREE select HAS_PASSTHROUGH select HAS_PDX - select HAS_PMAP + select HAS_PMAP if !HAS_MPU select IOMMU_FORCE_PT_SHARE =20 config ARCH_DEFCONFIG diff --git a/xen/arch/arm/include/asm/config_mpu.h b/xen/arch/arm/include/a= sm/config_mpu.h index 530abb8302..eee60dcffc 100644 --- a/xen/arch/arm/include/asm/config_mpu.h +++ b/xen/arch/arm/include/asm/config_mpu.h @@ -24,4 +24,6 @@ =20 #define HYPERVISOR_VIRT_START XEN_VIRT_START =20 +#define FIXMAP_ADDR(n) (_AT(paddr_t, n) & (PAGE_MASK)) + #endif /* __ARM_CONFIG_MPU_H__ */ diff --git a/xen/arch/arm/include/asm/fixmap.h b/xen/arch/arm/include/asm/f= ixmap.h index d0c9a52c8c..1e338759e9 100644 --- a/xen/arch/arm/include/asm/fixmap.h +++ b/xen/arch/arm/include/asm/fixmap.h @@ -7,6 +7,8 @@ #include #include =20 +#ifndef CONFIG_HAS_MPU + /* Fixmap slots */ #define FIXMAP_CONSOLE 0 /* The primary UART */ #define FIXMAP_MISC 1 /* Ephemeral mappings of hardware */ @@ -45,4 +47,27 @@ static inline unsigned int virt_to_fix(vaddr_t vaddr) =20 #endif /* __ASSEMBLY__ */ =20 +#else + +/* + * FIXMAP_ADDR will trim physical address to PAGE alignment. + * This will return an offset which is similar to MMU version + * FIXMAP_ADDR. + * For example: + * EARLY_UART_VIRTUAL_ADDRESS is defined by: + * (FIXMAP_ADDR(FIXMAP_CONSOLE) + \ + * (CONFIG_EARLY_UART_BASE_ADDRESS & ~PAGE_MASK)) + * With MPU version FIXMAP_CONSOLE and FIXMAP_ADDR definitions, + * EARLY_UART_VIRTUAL_ADDRESS can be restore to + * CONFIG_EARLY_UART_BASE_ADDRESS. + * In this case, we don't need to use #ifdef MPU in the code + * where are using FIXMAP_ADDR to make them to use physical + * address explicitily. + */ +#ifdef CONFIG_EARLY_UART_BASE_ADDRESS +#define FIXMAP_CONSOLE CONFIG_EARLY_UART_BASE_ADDRESS +#endif + +#endif /* CONFIG_HAS_MPU */ + #endif /* __ASM_FIXMAP_H */ --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Wei Chen , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Henry Wang Subject: [PATCH v6 08/11] xen/arm64: move MMU related code from head.S to head_mmu.S Date: Fri, 4 Nov 2022 18:07:38 +0800 Message-ID: <20221104100741.2176307-9-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT019:EE_|PAXPR08MB6365:EE_|DBAEUR03FT053:EE_|VI1PR08MB10148:EE_ X-MS-Office365-Filtering-Correlation-Id: 8822de9f-8cb4-4ee3-4804-08dabe4c8df9 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:43.5062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8822de9f-8cb4-4ee3-4804-08dabe4c8df9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT053.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB10148 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556576941100001 Content-Type: text/plain; charset="utf-8" There are lots of MMU specific code in head.S. This code will not be used in MPU systems. If we use #ifdef to gate them, the code will become messy and hard to maintain. So we move MMU related code to head_mmu.S, and keep common code still in head.S. As we need to access "fail" and "puts" functions out of assembly file, so we have to export them in this patch. And the assembly macros: adr_l and load_paddr will be used by MMU and MPU later, so we move them to macros.h. Signed-off-by: Henry Wang Signed-off-by: Wei Chen --- xen/arch/arm/arm64/Makefile | 3 + xen/arch/arm/arm64/head.S | 407 +----------------------- xen/arch/arm/arm64/head_mmu.S | 364 +++++++++++++++++++++ xen/arch/arm/include/asm/arm64/macros.h | 52 ++- 4 files changed, 432 insertions(+), 394 deletions(-) create mode 100644 xen/arch/arm/arm64/head_mmu.S diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 6d507da0d4..22da2f54b5 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -8,6 +8,9 @@ obj-y +=3D domctl.o obj-y +=3D domain.o obj-y +=3D entry.o obj-y +=3D head.o +ifneq ($(CONFIG_HAS_MPU),y) +obj-y +=3D head_mmu.o +endif obj-y +=3D insn.o obj-$(CONFIG_LIVEPATCH) +=3D livepatch.o obj-y +=3D smc.o diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index ccedf20dc7..d9a8da9120 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -25,17 +25,6 @@ #include #include =20 -#define PT_PT 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ -#define PT_MEM 0xf7d /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D0 P=3D1 */ -#define PT_MEM_L3 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ -#define PT_DEV 0xe71 /* nG=3D1 AF=3D1 SH=3D10 AP=3D01 NS=3D1 ATTR=3D100= T=3D0 P=3D1 */ -#define PT_DEV_L3 0xe73 /* nG=3D1 AF=3D1 SH=3D10 AP=3D01 NS=3D1 ATTR=3D100= T=3D1 P=3D1 */ - -/* Convenience defines to get slot used by Xen mapping. */ -#define XEN_ZEROETH_SLOT zeroeth_table_offset(XEN_VIRT_START) -#define XEN_FIRST_SLOT first_table_offset(XEN_VIRT_START) -#define XEN_SECOND_SLOT second_table_offset(XEN_VIRT_START) - #define __HEAD_FLAG_PAGE_SIZE ((PAGE_SHIFT - 10) / 2) =20 #define __HEAD_FLAG_PHYS_BASE 1 @@ -82,73 +71,22 @@ * x30 - lr */ =20 -#ifdef CONFIG_EARLY_PRINTK -/* - * Macro to print a string to the UART, if there is one. - * - * Clobbers x0 - x3 - */ -#define PRINT(_s) \ - mov x3, lr ; \ - adr x0, 98f ; \ - bl puts ; \ - mov lr, x3 ; \ - RODATA_STR(98, _s) +.section .text.header, "ax", %progbits +/*.aarch64*/ =20 /* - * Macro to print the value of register \xb + * Kernel startup entry point. + * --------------------------- * - * Clobbers x0 - x4 - */ -.macro print_reg xb - mov x0, \xb - mov x4, lr - bl putn - mov lr, x4 -.endm - -#else /* CONFIG_EARLY_PRINTK */ -#define PRINT(s) - -.macro print_reg xb -.endm - -#endif /* !CONFIG_EARLY_PRINTK */ - -/* - * Pseudo-op for PC relative adr , where is - * within the range +/- 4GB of the PC. + * The requirements are: + * MMU =3D off, D-cache =3D off, I-cache =3D on or off, + * x0 =3D physical address to the FDT blob. * - * @dst: destination register (64 bit wide) - * @sym: name of the symbol + * This must be the very first address in the loaded image. + * It should be linked at XEN_VIRT_START, and loaded at any + * 4K-aligned address. All of text+data+bss must fit in 2MB, + * or the initial pagetable code below will need adjustment. */ -.macro adr_l, dst, sym - adrp \dst, \sym - add \dst, \dst, :lo12:\sym -.endm - -/* Load the physical address of a symbol into xb */ -.macro load_paddr xb, sym - ldr \xb, =3D\sym - add \xb, \xb, x20 -.endm - - .section .text.header, "ax", %progbits - /*.aarch64*/ - - /* - * Kernel startup entry point. - * --------------------------- - * - * The requirements are: - * MMU =3D off, D-cache =3D off, I-cache =3D on or off, - * x0 =3D physical address to the FDT blob. - * - * This must be the very first address in the loaded image. - * It should be linked at XEN_VIRT_START, and loaded at any - * 4K-aligned address. All of text+data+bss must fit in 2MB, - * or the initial pagetable code below will need adjustment. - */ =20 GLOBAL(start) /* @@ -497,296 +435,6 @@ cpu_init: ret ENDPROC(cpu_init) =20 -/* - * Macro to find the slot number at a given page-table level - * - * slot: slot computed - * virt: virtual address - * lvl: page-table level - */ -.macro get_table_slot, slot, virt, lvl - ubfx \slot, \virt, #XEN_PT_LEVEL_SHIFT(\lvl), #XEN_PT_LPAE_SHIFT -.endm - -/* - * Macro to create a page table entry in \ptbl to \tbl - * - * ptbl: table symbol where the entry will be created - * tbl: table symbol to point to - * virt: virtual address - * lvl: page-table level - * tmp1: scratch register - * tmp2: scratch register - * tmp3: scratch register - * - * Preserves \virt - * Clobbers \tmp1, \tmp2, \tmp3 - * - * Also use x20 for the phys offset. - * - * Note that all parameters using registers should be distinct. - */ -.macro create_table_entry, ptbl, tbl, virt, lvl, tmp1, tmp2, tmp3 - get_table_slot \tmp1, \virt, \lvl /* \tmp1 :=3D slot in \tlb */ - - load_paddr \tmp2, \tbl - mov \tmp3, #PT_PT /* \tmp3 :=3D right for linear= PT */ - orr \tmp3, \tmp3, \tmp2 /* + \tlb paddr */ - - adr_l \tmp2, \ptbl - - str \tmp3, [\tmp2, \tmp1, lsl #3] -.endm - -/* - * Macro to create a mapping entry in \tbl to \phys. Only mapping in 3rd - * level table (i.e page granularity) is supported. - * - * ptbl: table symbol where the entry will be created - * virt: virtual address - * phys: physical address (should be page aligned) - * tmp1: scratch register - * tmp2: scratch register - * tmp3: scratch register - * type: mapping type. If not specified it will be normal memory (PT_ME= M_L3) - * - * Preserves \virt, \phys - * Clobbers \tmp1, \tmp2, \tmp3 - * - * Note that all parameters using registers should be distinct. - */ -.macro create_mapping_entry, ptbl, virt, phys, tmp1, tmp2, tmp3, type=3DPT= _MEM_L3 - and \tmp3, \phys, #THIRD_MASK /* \tmp3 :=3D PAGE_ALIGNED(phy= s) */ - - get_table_slot \tmp1, \virt, 3 /* \tmp1 :=3D slot in \tlb */ - - mov \tmp2, #\type /* \tmp2 :=3D right for sectio= n PT */ - orr \tmp2, \tmp2, \tmp3 /* + PAGE_ALIGNED(phy= s) */ - - adr_l \tmp3, \ptbl - - str \tmp2, [\tmp3, \tmp1, lsl #3] -.endm - -/* - * Rebuild the boot pagetable's first-level entries. The structure - * is described in mm.c. - * - * After the CPU enables paging it will add the fixmap mapping - * to these page tables, however this may clash with the 1:1 - * mapping. So each CPU must rebuild the page tables here with - * the 1:1 in place. - * - * Inputs: - * x19: paddr(start) - * x20: phys offset - * - * Clobbers x0 - x4 - */ -create_page_tables: - /* Prepare the page-tables for mapping Xen */ - ldr x0, =3DXEN_VIRT_START - create_table_entry boot_pgtable, boot_first, x0, 0, x1, x2, x3 - create_table_entry boot_first, boot_second, x0, 1, x1, x2, x3 - create_table_entry boot_second, boot_third, x0, 2, x1, x2, x3 - - /* Map Xen */ - adr_l x4, boot_third - - lsr x2, x19, #THIRD_SHIFT /* Base address for 4K mapping */ - lsl x2, x2, #THIRD_SHIFT - mov x3, #PT_MEM_L3 /* x2 :=3D Section map */ - orr x2, x2, x3 - - /* ... map of vaddr(start) in boot_third */ - mov x1, xzr -1: str x2, [x4, x1] /* Map vaddr(start) */ - add x2, x2, #PAGE_SIZE /* Next page */ - add x1, x1, #8 /* Next slot */ - cmp x1, #(XEN_PT_LPAE_ENTRIES<<3) /* 512 entries per page */ - b.lt 1b - - /* - * If Xen is loaded at exactly XEN_VIRT_START then we don't - * need an additional 1:1 mapping, the virtual mapping will - * suffice. - */ - cmp x19, #XEN_VIRT_START - bne 1f - ret -1: - /* - * Setup the 1:1 mapping so we can turn the MMU on. Note that - * only the first page of Xen will be part of the 1:1 mapping. - */ - - /* - * Find the zeroeth slot used. If the slot is not - * XEN_ZEROETH_SLOT, then the 1:1 mapping will use its own set of - * page-tables from the first level. - */ - get_table_slot x0, x19, 0 /* x0 :=3D zeroeth slot */ - cmp x0, #XEN_ZEROETH_SLOT - beq 1f - create_table_entry boot_pgtable, boot_first_id, x19, 0, x0, x1, x2 - b link_from_first_id - -1: - /* - * Find the first slot used. If the slot is not XEN_FIRST_SLOT, - * then the 1:1 mapping will use its own set of page-tables from - * the second level. - */ - get_table_slot x0, x19, 1 /* x0 :=3D first slot */ - cmp x0, #XEN_FIRST_SLOT - beq 1f - create_table_entry boot_first, boot_second_id, x19, 1, x0, x1, x2 - b link_from_second_id - -1: - /* - * Find the second slot used. If the slot is XEN_SECOND_SLOT, then= the - * 1:1 mapping will use its own set of page-tables from the - * third level. For slot XEN_SECOND_SLOT, Xen is not yet able to h= andle - * it. - */ - get_table_slot x0, x19, 2 /* x0 :=3D second slot */ - cmp x0, #XEN_SECOND_SLOT - beq virtphys_clash - create_table_entry boot_second, boot_third_id, x19, 2, x0, x1, x2 - b link_from_third_id - -link_from_first_id: - create_table_entry boot_first_id, boot_second_id, x19, 1, x0, x1, = x2 -link_from_second_id: - create_table_entry boot_second_id, boot_third_id, x19, 2, x0, x1, = x2 -link_from_third_id: - create_mapping_entry boot_third_id, x19, x19, x0, x1, x2 - ret - -virtphys_clash: - /* Identity map clashes with boot_third, which we cannot handle ye= t */ - PRINT("- Unable to build boot page tables - virt and phys addresse= s clash. -\r\n") - b fail -ENDPROC(create_page_tables) - -/* - * Turn on the Data Cache and the MMU. The function will return on the 1:1 - * mapping. In other word, the caller is responsible to switch to the runt= ime - * mapping. - * - * Clobbers x0 - x3 - */ -enable_mmu: - PRINT("- Turning on paging -\r\n") - - /* - * The state of the TLBs is unknown before turning on the MMU. - * Flush them to avoid stale one. - */ - tlbi alle2 /* Flush hypervisor TLBs */ - dsb nsh - - /* Write Xen's PT's paddr into TTBR0_EL2 */ - load_paddr x0, boot_pgtable - msr TTBR0_EL2, x0 - isb - - mrs x0, SCTLR_EL2 - orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MMU */ - orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ - dsb sy /* Flush PTE writes and finish reads = */ - msr SCTLR_EL2, x0 /* now paging is enabled */ - isb /* Now, flush the icache */ - ret -ENDPROC(enable_mmu) - -/* - * Remove the 1:1 map from the page-tables. It is not easy to keep track - * where the 1:1 map was mapped, so we will look for the top-level entry - * exclusive to the 1:1 map and remove it. - * - * Inputs: - * x19: paddr(start) - * - * Clobbers x0 - x1 - */ -remove_identity_mapping: - /* - * Find the zeroeth slot used. Remove the entry from zeroeth - * table if the slot is not XEN_ZEROETH_SLOT. - */ - get_table_slot x1, x19, 0 /* x1 :=3D zeroeth slot */ - cmp x1, #XEN_ZEROETH_SLOT - beq 1f - /* It is not in slot XEN_ZEROETH_SLOT, remove the entry. */ - ldr x0, =3Dboot_pgtable /* x0 :=3D root table */ - str xzr, [x0, x1, lsl #3] - b identity_mapping_removed - -1: - /* - * Find the first slot used. Remove the entry for the first - * table if the slot is not XEN_FIRST_SLOT. - */ - get_table_slot x1, x19, 1 /* x1 :=3D first slot */ - cmp x1, #XEN_FIRST_SLOT - beq 1f - /* It is not in slot XEN_FIRST_SLOT, remove the entry. */ - ldr x0, =3Dboot_first /* x0 :=3D first table */ - str xzr, [x0, x1, lsl #3] - b identity_mapping_removed - -1: - /* - * Find the second slot used. Remove the entry for the first - * table if the slot is not XEN_SECOND_SLOT. - */ - get_table_slot x1, x19, 2 /* x1 :=3D second slot */ - cmp x1, #XEN_SECOND_SLOT - beq identity_mapping_removed - /* It is not in slot 1, remove the entry */ - ldr x0, =3Dboot_second /* x0 :=3D second table */ - str xzr, [x0, x1, lsl #3] - -identity_mapping_removed: - /* See asm/arm64/flushtlb.h for the explanation of the sequence. */ - dsb nshst - tlbi alle2 - dsb nsh - isb - - ret -ENDPROC(remove_identity_mapping) - -/* - * Map the UART in the fixmap (when earlyprintk is used) and hook the - * fixmap table in the page tables. - * - * The fixmap cannot be mapped in create_page_tables because it may - * clash with the 1:1 mapping. - * - * Inputs: - * x20: Physical offset - * x23: Early UART base physical address - * - * Clobbers x0 - x3 - */ -setup_fixmap: -#ifdef CONFIG_EARLY_PRINTK - /* Add UART to the fixmap table */ - ldr x0, =3DEARLY_UART_VIRTUAL_ADDRESS - create_mapping_entry xen_fixmap, x0, x23, x1, x2, x3, type=3DPT_DE= V_L3 -#endif - /* Map fixmap into boot_second */ - ldr x0, =3DFIXMAP_ADDR(0) - create_table_entry boot_second, xen_fixmap, x0, 2, x1, x2, x3 - /* Ensure any page table updates made above have occurred. */ - dsb nshst - - ret -ENDPROC(setup_fixmap) - /* * Setup the initial stack and jump to the C world * @@ -810,41 +458,14 @@ launch: ENDPROC(launch) =20 /* Fail-stop */ -fail: PRINT("- Boot failed -\r\n") +ENTRY(fail) + PRINT("- Boot failed -\r\n") 1: wfe b 1b ENDPROC(fail) =20 GLOBAL(_end_boot) =20 -/* - * Switch TTBR - * - * x0 ttbr - * - * TODO: This code does not comply with break-before-make. - */ -ENTRY(switch_ttbr) - dsb sy /* Ensure the flushes happen before - * continuing */ - isb /* Ensure synchronization with previo= us - * changes to text */ - tlbi alle2 /* Flush hypervisor TLB */ - ic iallu /* Flush I-cache */ - dsb sy /* Ensure completion of TLB flush */ - isb - - msr TTBR0_EL2, x0 - - isb /* Ensure synchronization with previo= us - * changes to text */ - tlbi alle2 /* Flush hypervisor TLB */ - ic iallu /* Flush I-cache */ - dsb sy /* Ensure completion of TLB flush */ - isb - - ret -ENDPROC(switch_ttbr) =20 #ifdef CONFIG_EARLY_PRINTK /* @@ -868,7 +489,7 @@ ENDPROC(init_uart) * x0: Nul-terminated string to print. * x23: Early UART base address * Clobbers x0-x1 */ -puts: +ENTRY(puts) early_uart_ready x23, 1 ldrb w1, [x0], #1 /* Load next char */ cbz w1, 1f /* Exit on nul */ diff --git a/xen/arch/arm/arm64/head_mmu.S b/xen/arch/arm/arm64/head_mmu.S new file mode 100644 index 0000000000..1a3df81a38 --- /dev/null +++ b/xen/arch/arm/arm64/head_mmu.S @@ -0,0 +1,364 @@ +/* + * xen/arch/arm/head_mmu.S + * + * Start-of-day code for an ARMv8-A. + * + * Ian Campbell + * Copyright (c) 2012 Citrix Systems. + * + * Based on ARMv7-A head.S by + * Tim Deegan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#define PT_PT 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ +#define PT_MEM 0xf7d /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D0 P=3D1 */ +#define PT_MEM_L3 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ +#define PT_DEV 0xe71 /* nG=3D1 AF=3D1 SH=3D10 AP=3D01 NS=3D1 ATTR=3D100= T=3D0 P=3D1 */ +#define PT_DEV_L3 0xe73 /* nG=3D1 AF=3D1 SH=3D10 AP=3D01 NS=3D1 ATTR=3D100= T=3D1 P=3D1 */ + +/* Convenience defines to get slot used by Xen mapping. */ +#define XEN_ZEROETH_SLOT zeroeth_table_offset(XEN_VIRT_START) +#define XEN_FIRST_SLOT first_table_offset(XEN_VIRT_START) +#define XEN_SECOND_SLOT second_table_offset(XEN_VIRT_START) + +/* + * Macro to find the slot number at a given page-table level + * + * slot: slot computed + * virt: virtual address + * lvl: page-table level + */ +.macro get_table_slot, slot, virt, lvl + ubfx \slot, \virt, #XEN_PT_LEVEL_SHIFT(\lvl), #XEN_PT_LPAE_SHIFT +.endm + +/* + * Macro to create a page table entry in \ptbl to \tbl + * + * ptbl: table symbol where the entry will be created + * tbl: table symbol to point to + * virt: virtual address + * lvl: page-table level + * tmp1: scratch register + * tmp2: scratch register + * tmp3: scratch register + * + * Preserves \virt + * Clobbers \tmp1, \tmp2, \tmp3 + * + * Also use x20 for the phys offset. + * + * Note that all parameters using registers should be distinct. + */ +.macro create_table_entry, ptbl, tbl, virt, lvl, tmp1, tmp2, tmp3 + get_table_slot \tmp1, \virt, \lvl /* \tmp1 :=3D slot in \tlb */ + + load_paddr \tmp2, \tbl + mov \tmp3, #PT_PT /* \tmp3 :=3D right for linear= PT */ + orr \tmp3, \tmp3, \tmp2 /* + \tlb paddr */ + + adr_l \tmp2, \ptbl + + str \tmp3, [\tmp2, \tmp1, lsl #3] +.endm + +/* + * Macro to create a mapping entry in \tbl to \phys. Only mapping in 3rd + * level table (i.e page granularity) is supported. + * + * ptbl: table symbol where the entry will be created + * virt: virtual address + * phys: physical address (should be page aligned) + * tmp1: scratch register + * tmp2: scratch register + * tmp3: scratch register + * type: mapping type. If not specified it will be normal memory (PT_ME= M_L3) + * + * Preserves \virt, \phys + * Clobbers \tmp1, \tmp2, \tmp3 + * + * Note that all parameters using registers should be distinct. + */ +.macro create_mapping_entry, ptbl, virt, phys, tmp1, tmp2, tmp3, type=3DPT= _MEM_L3 + and \tmp3, \phys, #THIRD_MASK /* \tmp3 :=3D PAGE_ALIGNED(phy= s) */ + + get_table_slot \tmp1, \virt, 3 /* \tmp1 :=3D slot in \tlb */ + + mov \tmp2, #\type /* \tmp2 :=3D right for sectio= n PT */ + orr \tmp2, \tmp2, \tmp3 /* + PAGE_ALIGNED(phy= s) */ + + adr_l \tmp3, \ptbl + + str \tmp2, [\tmp3, \tmp1, lsl #3] +.endm + +.section .text.header, "ax", %progbits +/*.aarch64*/ + +/* + * Rebuild the boot pagetable's first-level entries. The structure + * is described in mm.c. + * + * After the CPU enables paging it will add the fixmap mapping + * to these page tables, however this may clash with the 1:1 + * mapping. So each CPU must rebuild the page tables here with + * the 1:1 in place. + * + * Inputs: + * x19: paddr(start) + * x20: phys offset + * + * Clobbers x0 - x4 + */ +ENTRY(create_page_tables) + /* Prepare the page-tables for mapping Xen */ + ldr x0, =3DXEN_VIRT_START + create_table_entry boot_pgtable, boot_first, x0, 0, x1, x2, x3 + create_table_entry boot_first, boot_second, x0, 1, x1, x2, x3 + create_table_entry boot_second, boot_third, x0, 2, x1, x2, x3 + + /* Map Xen */ + adr_l x4, boot_third + + lsr x2, x19, #THIRD_SHIFT /* Base address for 4K mapping */ + lsl x2, x2, #THIRD_SHIFT + mov x3, #PT_MEM_L3 /* x2 :=3D Section map */ + orr x2, x2, x3 + + /* ... map of vaddr(start) in boot_third */ + mov x1, xzr +1: str x2, [x4, x1] /* Map vaddr(start) */ + add x2, x2, #PAGE_SIZE /* Next page */ + add x1, x1, #8 /* Next slot */ + cmp x1, #(XEN_PT_LPAE_ENTRIES<<3) /* 512 entries per page */ + b.lt 1b + + /* + * If Xen is loaded at exactly XEN_VIRT_START then we don't + * need an additional 1:1 mapping, the virtual mapping will + * suffice. + */ + cmp x19, #XEN_VIRT_START + bne 1f + ret +1: + /* + * Setup the 1:1 mapping so we can turn the MMU on. Note that + * only the first page of Xen will be part of the 1:1 mapping. + */ + + /* + * Find the zeroeth slot used. If the slot is not + * XEN_ZEROETH_SLOT, then the 1:1 mapping will use its own set of + * page-tables from the first level. + */ + get_table_slot x0, x19, 0 /* x0 :=3D zeroeth slot */ + cmp x0, #XEN_ZEROETH_SLOT + beq 1f + create_table_entry boot_pgtable, boot_first_id, x19, 0, x0, x1, x2 + b link_from_first_id + +1: + /* + * Find the first slot used. If the slot is not XEN_FIRST_SLOT, + * then the 1:1 mapping will use its own set of page-tables from + * the second level. + */ + get_table_slot x0, x19, 1 /* x0 :=3D first slot */ + cmp x0, #XEN_FIRST_SLOT + beq 1f + create_table_entry boot_first, boot_second_id, x19, 1, x0, x1, x2 + b link_from_second_id + +1: + /* + * Find the second slot used. If the slot is XEN_SECOND_SLOT, then= the + * 1:1 mapping will use its own set of page-tables from the + * third level. For slot XEN_SECOND_SLOT, Xen is not yet able to h= andle + * it. + */ + get_table_slot x0, x19, 2 /* x0 :=3D second slot */ + cmp x0, #XEN_SECOND_SLOT + beq virtphys_clash + create_table_entry boot_second, boot_third_id, x19, 2, x0, x1, x2 + b link_from_third_id + +link_from_first_id: + create_table_entry boot_first_id, boot_second_id, x19, 1, x0, x1, = x2 +link_from_second_id: + create_table_entry boot_second_id, boot_third_id, x19, 2, x0, x1, = x2 +link_from_third_id: + create_mapping_entry boot_third_id, x19, x19, x0, x1, x2 + ret + +virtphys_clash: + /* Identity map clashes with boot_third, which we cannot handle ye= t */ + PRINT("- Unable to build boot page tables - virt and phys addresse= s clash. -\r\n") + b fail +ENDPROC(create_page_tables) + +/* + * Turn on the Data Cache and the MMU. The function will return on the 1:1 + * mapping. In other word, the caller is responsible to switch to the runt= ime + * mapping. + * + * Clobbers x0 - x3 + */ +ENTRY(enable_mmu) + PRINT("- Turning on paging -\r\n") + + /* + * The state of the TLBs is unknown before turning on the MMU. + * Flush them to avoid stale one. + */ + tlbi alle2 /* Flush hypervisor TLBs */ + dsb nsh + + /* Write Xen's PT's paddr into TTBR0_EL2 */ + load_paddr x0, boot_pgtable + msr TTBR0_EL2, x0 + isb + + mrs x0, SCTLR_EL2 + orr x0, x0, #SCTLR_Axx_ELx_M /* Enable MMU */ + orr x0, x0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + dsb sy /* Flush PTE writes and finish reads = */ + msr SCTLR_EL2, x0 /* now paging is enabled */ + isb /* Now, flush the icache */ + ret +ENDPROC(enable_mmu) + +/* + * Remove the 1:1 map from the page-tables. It is not easy to keep track + * where the 1:1 map was mapped, so we will look for the top-level entry + * exclusive to the 1:1 map and remove it. + * + * Inputs: + * x19: paddr(start) + * + * Clobbers x0 - x1 + */ +ENTRY(remove_identity_mapping) + /* + * Find the zeroeth slot used. Remove the entry from zeroeth + * table if the slot is not XEN_ZEROETH_SLOT. + */ + get_table_slot x1, x19, 0 /* x1 :=3D zeroeth slot */ + cmp x1, #XEN_ZEROETH_SLOT + beq 1f + /* It is not in slot XEN_ZEROETH_SLOT, remove the entry. */ + ldr x0, =3Dboot_pgtable /* x0 :=3D root table */ + str xzr, [x0, x1, lsl #3] + b identity_mapping_removed + +1: + /* + * Find the first slot used. Remove the entry for the first + * table if the slot is not XEN_FIRST_SLOT. + */ + get_table_slot x1, x19, 1 /* x1 :=3D first slot */ + cmp x1, #XEN_FIRST_SLOT + beq 1f + /* It is not in slot XEN_FIRST_SLOT, remove the entry. */ + ldr x0, =3Dboot_first /* x0 :=3D first table */ + str xzr, [x0, x1, lsl #3] + b identity_mapping_removed + +1: + /* + * Find the second slot used. Remove the entry for the first + * table if the slot is not XEN_SECOND_SLOT. + */ + get_table_slot x1, x19, 2 /* x1 :=3D second slot */ + cmp x1, #XEN_SECOND_SLOT + beq identity_mapping_removed + /* It is not in slot 1, remove the entry */ + ldr x0, =3Dboot_second /* x0 :=3D second table */ + str xzr, [x0, x1, lsl #3] + +identity_mapping_removed: + /* See asm/arm64/flushtlb.h for the explanation of the sequence. */ + dsb nshst + tlbi alle2 + dsb nsh + isb + + ret +ENDPROC(remove_identity_mapping) + +/* + * Map the UART in the fixmap (when earlyprintk is used) and hook the + * fixmap table in the page tables. + * + * The fixmap cannot be mapped in create_page_tables because it may + * clash with the 1:1 mapping. + * + * Inputs: + * x20: Physical offset + * x23: Early UART base physical address + * + * Clobbers x0 - x3 + */ +ENTRY(setup_fixmap) +#ifdef CONFIG_EARLY_PRINTK + /* Add UART to the fixmap table */ + ldr x0, =3DEARLY_UART_VIRTUAL_ADDRESS + create_mapping_entry xen_fixmap, x0, x23, x1, x2, x3, type=3DPT_DE= V_L3 +#endif + /* Map fixmap into boot_second */ + ldr x0, =3DFIXMAP_ADDR(0) + create_table_entry boot_second, xen_fixmap, x0, 2, x1, x2, x3 + /* Ensure any page table updates made above have occurred. */ + dsb nshst + + ret +ENDPROC(setup_fixmap) + +/* + * Switch TTBR + * + * x0 ttbr + * + * TODO: This code does not comply with break-before-make. + */ +ENTRY(switch_ttbr) + dsb sy /* Ensure the flushes happen before + * continuing */ + isb /* Ensure synchronization with previo= us + * changes to text */ + tlbi alle2 /* Flush hypervisor TLB */ + ic iallu /* Flush I-cache */ + dsb sy /* Ensure completion of TLB flush */ + isb + + msr TTBR0_EL2, x0 + + isb /* Ensure synchronization with previo= us + * changes to text */ + tlbi alle2 /* Flush hypervisor TLB */ + ic iallu /* Flush I-cache */ + dsb sy /* Ensure completion of TLB flush */ + isb + + ret +ENDPROC(switch_ttbr) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/macros.h b/xen/arch/arm/include= /asm/arm64/macros.h index 140e223b4c..462dc70335 100644 --- a/xen/arch/arm/include/asm/arm64/macros.h +++ b/xen/arch/arm/include/asm/arm64/macros.h @@ -32,10 +32,60 @@ hint #22 .endm =20 + /* + * Pseudo-op for PC relative adr , where is + * within the range +/- 4GB of the PC. + * + * @dst: destination register (64 bit wide) + * @sym: name of the symbol + */ + .macro adr_l, dst, sym + adrp \dst, \sym + add \dst, \dst, :lo12:\sym + .endm + + /* Load the physical address of a symbol into xb */ + .macro load_paddr xb, sym + ldr \xb, =3D\sym + add \xb, \xb, x20 + .endm + /* * Register aliases. */ lr .req x30 /* link register */ =20 -#endif /* __ASM_ARM_ARM64_MACROS_H */ +#ifdef CONFIG_EARLY_PRINTK +/* + * Macro to print a string to the UART, if there is one. + * + * Clobbers x0 - x3 + */ +#define PRINT(_s) \ + mov x3, lr ; \ + adr x0, 98f ; \ + bl puts ; \ + mov lr, x3 ; \ + RODATA_STR(98, _s) =20 + /* + * Macro to print the value of register \xb + * + * Clobbers x0 - x4 + */ + .macro print_reg xb + mov x0, \xb + mov x4, lr + bl putn + mov lr, x4 + .endm + +#else /* CONFIG_EARLY_PRINTK */ +#define PRINT(s) + +.macro print_reg xb +.endm + +#endif /* !CONFIG_EARLY_PRINTK */ + +#endif /* __ASM_ARM_ARM64_MACROS_H */ --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667557237; cv=pass; d=zohomail.com; s=zohoarc; b=ClqAD92IsgdjG8lEbQkhQvP4XlCi7JjYE/xrfNdktQjk2ku31BO04MnHK2IMu/+6L03aXTrD5eetU79RCT9Q7VNWXNHHeiHY5g+zcvznkVhNlTKsCuMZouDNo9qursZ+rIWBWVmyaQFGMnr7DnLb8TItmqwHOkqhOy+Q34McPZQ= ARC-Message-Signature: i=3; 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helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Wei Chen Subject: [PATCH v6 09/11] xen/arm64: create boot-time MPU protection regions Date: Fri, 4 Nov 2022 18:07:39 +0800 Message-ID: <20221104100741.2176307-10-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT019:EE_|GV1PR08MB8378:EE_|DBAEUR03FT017:EE_|DU0PR08MB7461:EE_ X-MS-Office365-Filtering-Correlation-Id: 1288136f-ad87-4942-95f1-08dabe4c8f31 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: YDz5fIJeSyTX9LXNBuPq6LGLd9xImAfIM7xMZdhKWCL77jFphZz9xhj00s4mq/2l2Qd3JnOnAMc1/tDWYn8I3TgeKtvoiBnOtLGP6xUi+zmzAR7XZiWA/4KHZheGF/N99Hb7yVnD6JiJiEXmVXVr0ZUMN2XBrBwqtb+i0IaBHZicffOBE9kpn4Fzer9evDSElbui0W6UEQlBS7yzqnbSG88vIXU4SgFqK4t5RBjq4cCoqLFcym924uUbzss/ggDQT2A+oE5U6iIN13XxJOB5WfC98qKz1KVNU/BN2OLoK95i5moVB7AgSVgCOshUshyQYLB9eDDwEKhyGkWcf3DYEo6nXRdIvUkluCh/oXhd/VfryVUU20C5hBQYMZHhttA8GH/aRSpOLFAGJgDqRIwerUHnpzITgUviKGOz8M2JM6TBJU/Tw+dgEP1CFu0mnYUcuzjJBtLs0tkqfUB2P7QroPKacwC5lePgOQ3T68GHAXXbi9LytMDamNGTo82xvIz0jlnToous0CHGRjmzQFlFKYPY+ynOPBIhDd1KImWbDqmcp7u4ve5xsRMsau7KSh2a8JfbsqjXWT5dMOxkvm3zXMTXiAPcgVSb8ItxOs7z6pqmeI4uwJJ5Y0fNNOktsbgpbNYF4oGyioT5nvFK4IzbKWAE0NJiZ5Q0EBIxlMRTdv2oXxzJz8uyJZQbtxyE+KFHk220TcN/M+XvrClzw7TgwYVLh49NSuscOwuTXCIlrAk67tAPzK+EXJQw/nZ4MzYvV3gdQTh7fJ0Aj7ZK2+nABn3i85SXph11S8mkZDv6bwrW6x8adaFRikRp81t+wekT X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(39860400002)(376002)(396003)(451199015)(46966006)(40470700004)(36840700001)(36756003)(81166007)(86362001)(356005)(82740400003)(44832011)(1076003)(70586007)(6916009)(40480700001)(5660300002)(336012)(426003)(47076005)(2616005)(36860700001)(478600001)(7696005)(40460700003)(186003)(83380400001)(26005)(8936002)(8676002)(54906003)(70206006)(2906002)(316002)(82310400005)(4326008)(41300700001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:45.5529 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1288136f-ad87-4942-95f1-08dabe4c8f31 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7461 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667557239705100001 Content-Type: text/plain; charset="utf-8" From: Penny Zheng Like boot-time page table in MMU system, we need a boot-time MPU protection region configuration in MPU system so Xen can fetch code and data from normal memory. This operation need to access Armv8-R MPU system registers, but these system registers are not supported in GCC version < 11. So we have to encode these Armv8-R MPU system registers in header file explicitly. As MMU system and MPU system have different functions to create the boot MMU/MPU data, this will introduce extra #ifdef in code flow, so we introduce a neutral name prepare_early_mappings to replace create_page_tables for MMU and MPU. Signed-off-by: Wei Chen Signed-off-by: Penny Zheng --- xen/arch/arm/arm64/Makefile | 2 + xen/arch/arm/arm64/head.S | 13 ++-- xen/arch/arm/arm64/head_mmu.S | 4 +- xen/arch/arm/arm64/head_mpu.S | 70 +++++++++++++++++++ xen/arch/arm/include/asm/arm64/mpu.h | 13 ++++ xen/arch/arm/include/asm/arm64/sysregs.h | 89 ++++++++++++++++++++++++ 6 files changed, 185 insertions(+), 6 deletions(-) create mode 100644 xen/arch/arm/arm64/head_mpu.S create mode 100644 xen/arch/arm/include/asm/arm64/mpu.h diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 22da2f54b5..438c9737ad 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -10,6 +10,8 @@ obj-y +=3D entry.o obj-y +=3D head.o ifneq ($(CONFIG_HAS_MPU),y) obj-y +=3D head_mmu.o +else +obj-y +=3D head_mpu.o endif obj-y +=3D insn.o obj-$(CONFIG_LIVEPATCH) +=3D livepatch.o diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index d9a8da9120..6c1a5f74a1 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -79,12 +79,12 @@ * --------------------------- * * The requirements are: - * MMU =3D off, D-cache =3D off, I-cache =3D on or off, + * MMU/MPU =3D off, D-cache =3D off, I-cache =3D on or off, * x0 =3D physical address to the FDT blob. * * This must be the very first address in the loaded image. * It should be linked at XEN_VIRT_START, and loaded at any - * 4K-aligned address. All of text+data+bss must fit in 2MB, + * 4K-aligned address. All of text+data+bss must fit in 2MB, * or the initial pagetable code below will need adjustment. */ =20 @@ -249,7 +249,12 @@ real_start_efi: =20 bl check_cpu_mode bl cpu_init - bl create_page_tables + + /* + * Create boot memory management data, pagetable for MMU systems + * and protection regions for MPU systems. + */ + bl prepare_early_mappings bl enable_mmu =20 /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ @@ -307,7 +312,7 @@ GLOBAL(init_secondary) #endif bl check_cpu_mode bl cpu_init - bl create_page_tables + bl prepare_early_mappings bl enable_mmu =20 /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ diff --git a/xen/arch/arm/arm64/head_mmu.S b/xen/arch/arm/arm64/head_mmu.S index 1a3df81a38..fc64819a98 100644 --- a/xen/arch/arm/arm64/head_mmu.S +++ b/xen/arch/arm/arm64/head_mmu.S @@ -123,7 +123,7 @@ * * Clobbers x0 - x4 */ -ENTRY(create_page_tables) +ENTRY(prepare_early_mappings) /* Prepare the page-tables for mapping Xen */ ldr x0, =3DXEN_VIRT_START create_table_entry boot_pgtable, boot_first, x0, 0, x1, x2, x3 @@ -208,7 +208,7 @@ virtphys_clash: /* Identity map clashes with boot_third, which we cannot handle ye= t */ PRINT("- Unable to build boot page tables - virt and phys addresse= s clash. -\r\n") b fail -ENDPROC(create_page_tables) +ENDPROC(prepare_early_mappings) =20 /* * Turn on the Data Cache and the MMU. The function will return on the 1:1 diff --git a/xen/arch/arm/arm64/head_mpu.S b/xen/arch/arm/arm64/head_mpu.S new file mode 100644 index 0000000000..f60611b556 --- /dev/null +++ b/xen/arch/arm/arm64/head_mpu.S @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include +#include + +/* + * From the requirements of head.S we know that Xen image should + * be linked at XEN_START_ADDRESS, and all of text + data + bss + * must fit in 2MB. On MPU systems, XEN_START_ADDRESS is also the + * address that Xen image should be loaded at. So for initial MPU + * regions setup, we use 2MB for Xen data memory to setup boot + * region, or the create boot regions code below will need adjustment. + */ +#define XEN_START_MEM_SIZE 0x200000 + +/* + * In boot stage, we will use 1 MPU region: + * Region#0: Normal memory for Xen text + data + bss (2MB) + */ +#define BOOT_NORMAL_REGION_IDX 0x0 + +/* MPU normal memory attributes. */ +#define PRBAR_NORMAL_MEM 0x30 /* SH=3D11 AP=3D00 XN=3D00 */ +#define PRLAR_NORMAL_MEM 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ + +.macro write_pr, sel, prbar, prlar + msr PRSELR_EL2, \sel + dsb sy + msr PRBAR_EL2, \prbar + msr PRLAR_EL2, \prlar + dsb sy + isb +.endm + +.section .text.header, "ax", %progbits + +/* + * Static start-of-day EL2 MPU memory layout. + * + * It has a very simple structure, including: + * - 2MB normal memory mappings of xen at XEN_START_ADDRESS, which + * is the address where Xen was loaded by the bootloader. + */ +ENTRY(prepare_early_mappings) + /* Map Xen start memory to a normal memory region. */ + mov x0, #BOOT_NORMAL_REGION_IDX + ldr x1, =3DXEN_START_ADDRESS + and x1, x1, #MPU_REGION_MASK + mov x3, #PRBAR_NORMAL_MEM + orr x1, x1, x3 + + ldr x2, =3DXEN_START_ADDRESS + mov x3, #(XEN_START_MEM_SIZE - 1) + add x2, x2, x3 + and x2, x2, #MPU_REGION_MASK + mov x3, #PRLAR_NORMAL_MEM + orr x2, x2, x3 + + /* + * Write to MPU protection region: + * x0 for pr_sel, x1 for prbar x2 for prlar + */ + write_pr x0, x1, x2 + + ret +ENDPROC(prepare_early_mappings) diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h new file mode 100644 index 0000000000..d209eef6db --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mpu.h: Arm Memory Protection Unit definitions. + */ + +#ifndef __ARM64_MPU_H__ +#define __ARM64_MPU_H__ + +#define MPU_REGION_SHIFT 6 +#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT) +#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1)) + +#endif /* __ARM64_MPU_H__ */ diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 54670084c3..a596042d6c 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -458,6 +458,95 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +/* System registers for AArch64 with PMSA */ +#ifdef CONFIG_HAS_MPU + +/* EL1 MPU Protection Region Base Address Register encode */ +#define PRBAR_EL1 S3_0_C6_C8_0 +#define PRBAR1_EL1 S3_0_C6_C8_4 +#define PRBAR2_EL1 S3_0_C6_C9_0 +#define PRBAR3_EL1 S3_0_C6_C9_4 +#define PRBAR4_EL1 S3_0_C6_C10_0 +#define PRBAR5_EL1 S3_0_C6_C10_4 +#define PRBAR6_EL1 S3_0_C6_C11_0 +#define PRBAR7_EL1 S3_0_C6_C11_4 +#define PRBAR8_EL1 S3_0_C6_C12_0 +#define PRBAR9_EL1 S3_0_C6_C12_4 +#define PRBAR10_EL1 S3_0_C6_C13_0 +#define PRBAR11_EL1 S3_0_C6_C13_4 +#define PRBAR12_EL1 S3_0_C6_C14_0 +#define PRBAR13_EL1 S3_0_C6_C14_4 +#define PRBAR14_EL1 S3_0_C6_C15_0 +#define PRBAR15_EL1 S3_0_C6_C15_4 + +/* EL1 MPU Protection Region Limit Address Register encode */ +#define PRLAR_EL1 S3_0_C6_C8_1 +#define PRLAR1_EL1 S3_0_C6_C8_5 +#define PRLAR2_EL1 S3_0_C6_C9_1 +#define PRLAR3_EL1 S3_0_C6_C9_5 +#define PRLAR4_EL1 S3_0_C6_C10_1 +#define PRLAR5_EL1 S3_0_C6_C10_5 +#define PRLAR6_EL1 S3_0_C6_C11_1 +#define PRLAR7_EL1 S3_0_C6_C11_5 +#define PRLAR8_EL1 S3_0_C6_C12_1 +#define PRLAR9_EL1 S3_0_C6_C12_5 +#define PRLAR10_EL1 S3_0_C6_C13_1 +#define PRLAR11_EL1 S3_0_C6_C13_5 +#define PRLAR12_EL1 S3_0_C6_C14_1 +#define PRLAR13_EL1 S3_0_C6_C14_5 +#define PRLAR14_EL1 S3_0_C6_C15_1 +#define PRLAR15_EL1 S3_0_C6_C15_5 + +/* EL2 MPU Protection Region Base Address Register encode */ +#define PRBAR_EL2 S3_4_C6_C8_0 +#define PRBAR1_EL2 S3_4_C6_C8_4 +#define PRBAR2_EL2 S3_4_C6_C9_0 +#define PRBAR3_EL2 S3_4_C6_C9_4 +#define PRBAR4_EL2 S3_4_C6_C10_0 +#define PRBAR5_EL2 S3_4_C6_C10_4 +#define PRBAR6_EL2 S3_4_C6_C11_0 +#define PRBAR7_EL2 S3_4_C6_C11_4 +#define PRBAR8_EL2 S3_4_C6_C12_0 +#define PRBAR9_EL2 S3_4_C6_C12_4 +#define PRBAR10_EL2 S3_4_C6_C13_0 +#define PRBAR11_EL2 S3_4_C6_C13_4 +#define PRBAR12_EL2 S3_4_C6_C14_0 +#define PRBAR13_EL2 S3_4_C6_C14_4 +#define PRBAR14_EL2 S3_4_C6_C15_0 +#define PRBAR15_EL2 S3_4_C6_C15_4 + +/* EL2 MPU Protection Region Limit Address Register encode */ +#define PRLAR_EL2 S3_4_C6_C8_1 +#define PRLAR1_EL2 S3_4_C6_C8_5 +#define PRLAR2_EL2 S3_4_C6_C9_1 +#define PRLAR3_EL2 S3_4_C6_C9_5 +#define PRLAR4_EL2 S3_4_C6_C10_1 +#define PRLAR5_EL2 S3_4_C6_C10_5 +#define PRLAR6_EL2 S3_4_C6_C11_1 +#define PRLAR7_EL2 S3_4_C6_C11_5 +#define PRLAR8_EL2 S3_4_C6_C12_1 +#define PRLAR9_EL2 S3_4_C6_C12_5 +#define PRLAR10_EL2 S3_4_C6_C13_1 +#define PRLAR11_EL2 S3_4_C6_C13_5 +#define PRLAR12_EL2 S3_4_C6_C14_1 +#define PRLAR13_EL2 S3_4_C6_C14_5 +#define PRLAR14_EL2 S3_4_C6_C15_1 +#define PRLAR15_EL2 S3_4_C6_C15_5 + +/* MPU Protection Region Enable Register encode */ +#define PRENR_EL1 S3_0_C6_C1_1 +#define PRENR_EL2 S3_4_C6_C1_1 + +/* MPU Protection Region Selection Register encode */ +#define PRSELR_EL1 S3_0_C6_C2_1 +#define PRSELR_EL2 S3_4_C6_C2_1 + +/* MPU Type registers encode */ +#define MPUIR_EL1 S3_0_C0_C0_4 +#define MPUIR_EL2 S3_4_C0_C0_4 + +#endif + /* Access to system registers */ =20 #define WRITE_SYSREG64(v, name) do { \ --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=3; a=rsa-sha256; t=1667557213; cv=pass; d=zohomail.com; s=zohoarc; b=ZkgNyQtihCYPjr+obP9H8jBjsZ++lPrU2WJ+p0oEz+t3EV2z3UA3qrplg4BgrYjOFJeln7zBmgM1pYNWH5HPs+jV+CZZEvmNtzd74U1Cq20J2/MCD60NWeV0gZiil/W4OqUH1JU3eMZo48pFylkQxscOABgxfisrMUKSPbzqsOc= ARC-Message-Signature: i=3; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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b=HoDHy0eJM5az/HUbzTHmEojHtdlO8zcdpirgv/BHfhSjHP6y7SPmXdUChRrlAEbRprOWxWhvgX8QOmilKhxft1tSKVcN/QPDUcVj8cATCNO3tG+aYfYrgiJjsmEK1s+YJoUeN6dbsWhAqw+9LaJ2dR5y7nm1uw8KXo5Ytdw7Odc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Wei Chen Subject: [PATCH v6 10/11] xen/arm64: introduce helpers for MPU enable/disable Date: Fri, 4 Nov 2022 18:07:40 +0800 Message-ID: <20221104100741.2176307-11-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> 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CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(346002)(136003)(376002)(451199015)(36840700001)(46966006)(40470700004)(186003)(336012)(7696005)(2616005)(1076003)(83380400001)(6666004)(426003)(36860700001)(26005)(47076005)(82740400003)(54906003)(44832011)(2906002)(40480700001)(40460700003)(316002)(8676002)(5660300002)(478600001)(8936002)(82310400005)(41300700001)(4326008)(70586007)(70206006)(6916009)(36756003)(81166007)(86362001);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:50.8408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ff2786d-cd62-4a0d-739a-08dabe4c9258 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT040.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB5921 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667557215607100001 Content-Type: text/plain; charset="utf-8" From: Penny Zheng We need some helpers for Xen to enable/disable MPU in boot-time and runtime. For MPU enable helper, we know that it's an essential requirement of MPU system. But for MPU disable, we need to use it for some special situations. For example, in the progress of tranferring from boot-time to runtime, we need to update the MPU protection regions configuration, but we can't modify an MPU protection region if there is some data accessed by Xen. But in boot-time all of Xen text, data and BSS are in one MPU protection region, if Xen want to update this protection region, above restriction will be triggered. So in this situation, we need to disable the whole MPU to update the protection regions. In these helper, enable/disable MPU will also enable/disable the D-cache. There are two reasons for it: 1. Make the function semantic be consistent with enable_mmu. For MMU systems, enable_mmu will turn MMU and D-Cache at the same time. 2. When MPU is disabled, the MPU background attributes will be used. On some platforms, the background will treat all memory as device memory. The access to device memory will bypass the cache, even if the C bit is enabled in SCTLR. To avoid this implicit behavior, we disable cache with MPU explicitly to tell user that when MPU is disabled, the memory access is uncacheable. In this patch, we also introduce a neutral name enable_mm for Xen to enable MMU/MPU. This can help us to keep one code flow in head.S Signed-off-by: Wei Chen Signed-off-by: Penny Zheng --- xen/arch/arm/arm64/head.S | 5 +++-- xen/arch/arm/arm64/head_mmu.S | 4 ++-- xen/arch/arm/arm64/head_mpu.S | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 6c1a5f74a1..228f01db69 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -255,7 +255,8 @@ real_start_efi: * and protection regions for MPU systems. */ bl prepare_early_mappings - bl enable_mmu + /* Turn on MMU or MPU */ + bl enable_mm =20 /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ ldr x0, =3Dprimary_switched @@ -313,7 +314,7 @@ GLOBAL(init_secondary) bl check_cpu_mode bl cpu_init bl prepare_early_mappings - bl enable_mmu + bl enable_mm =20 /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ ldr x0, =3Dsecondary_switched diff --git a/xen/arch/arm/arm64/head_mmu.S b/xen/arch/arm/arm64/head_mmu.S index fc64819a98..b542755bd2 100644 --- a/xen/arch/arm/arm64/head_mmu.S +++ b/xen/arch/arm/arm64/head_mmu.S @@ -217,7 +217,7 @@ ENDPROC(prepare_early_mappings) * * Clobbers x0 - x3 */ -ENTRY(enable_mmu) +ENTRY(enable_mm) PRINT("- Turning on paging -\r\n") =20 /* @@ -239,7 +239,7 @@ ENTRY(enable_mmu) msr SCTLR_EL2, x0 /* now paging is enabled */ isb /* Now, flush the icache */ ret -ENDPROC(enable_mmu) +ENDPROC(enable_mm) =20 /* * Remove the 1:1 map from the page-tables. It is not easy to keep track diff --git a/xen/arch/arm/arm64/head_mpu.S b/xen/arch/arm/arm64/head_mpu.S index f60611b556..5a1b03e293 100644 --- a/xen/arch/arm/arm64/head_mpu.S +++ b/xen/arch/arm/arm64/head_mpu.S @@ -68,3 +68,38 @@ ENTRY(prepare_early_mappings) =20 ret ENDPROC(prepare_early_mappings) + +/* + * Enable EL2 MPU and data cache. Because we will disable cache + * with MPU at the same time, in accordance with that, we have + * to enable cache with MPU at the same time in this function. + * When MPU is disabled, the MPU background attributes will + * be used. On some platform, the background will treat all + * memory as IO memory. The access to IO memory will bypass + * the cache, even you have enabled the C bit in SCTLR. + * To avoid this implicit behavior, we disable cache with MPU + * explicitly to tell user that when MPU is disabled, the memory + * access is uncacheable. + */ +ENTRY(enable_mm) + mrs x0, SCTLR_EL2 + mov x1, #(SCTLR_Axx_ELx_M | SCTLR_Axx_ELx_C) + /* Enable EL2 MPU and D-cache */ + orr x0, x0, x1 + dsb sy + msr SCTLR_EL2, x0 + isb + ret +ENDPROC(enable_mm) + +/* Disable MPU system, including data cache. */ +ENTRY(disable_mm) + mrs x0, SCTLR_EL2 + mov x1, #~(SCTLR_Axx_ELx_M | SCTLR_Axx_ELx_C) + /* Disable EL2 MPU and D-cache */ + and x0, x0, x1 + dsb sy + msr SCTLR_EL2, x0 + isb + ret +ENDPROC(disable_mm) --=20 2.25.1 From nobody Sun May 5 15:57:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=2 dmarc=pass fromdomain=arm.com); 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C From: Wei Chen To: CC: , Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Wei Chen Subject: [PATCH v6 11/11] xen/arm64: add setup_fixmap and remove_identity_mapping for MPU Date: Fri, 4 Nov 2022 18:07:41 +0800 Message-ID: <20221104100741.2176307-12-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221104100741.2176307-1-wei.chen@arm.com> References: <20221104100741.2176307-1-wei.chen@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT025:EE_|VE1PR08MB5823:EE_|DBAEUR03FT007:EE_|AM7PR08MB5400:EE_ X-MS-Office365-Filtering-Correlation-Id: ab9ddcbc-d674-4385-ff3c-08dabe4c92c6 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 10:08:51.5653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab9ddcbc-d674-4385-ff3c-08dabe4c92c6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT007.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR08MB5400 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1667556941225100001 Content-Type: text/plain; charset="utf-8" From: Penny Zheng setup_fixmap and remove_identity_mapping are two functions that are used in Xen boot-time code flow. We implement these two functions for MPU system, in this case, the code flow in head.S doesn't need to use #ifdef to gate MPU/MMU code. In MMU system, setup_fixmap is used for Xen to map some essentail data or devices in boot-time. For MPU system, we still have this requirement, we map the early UART to MPU protection region when earlyprintk is enabled. This also means PRINT can't be used after turning on MPU but before setup_fixmap. This restriction is the same as MMU system. For remove_identity_mapping, we just need an empty function to make head.S code flow happy. Signed-off-by: Wei Chen Signed-off-by: Penny Zheng --- xen/arch/arm/arm64/head_mpu.S | 49 +++++++++++++++++++ .../arm/include/asm/platforms/fvp_baser.h | 4 ++ 2 files changed, 53 insertions(+) diff --git a/xen/arch/arm/arm64/head_mpu.S b/xen/arch/arm/arm64/head_mpu.S index 5a1b03e293..336c0a630f 100644 --- a/xen/arch/arm/arm64/head_mpu.S +++ b/xen/arch/arm/arm64/head_mpu.S @@ -20,13 +20,20 @@ /* * In boot stage, we will use 1 MPU region: * Region#0: Normal memory for Xen text + data + bss (2MB) + * Region#1: Device memory for EARLY UART, size is defined + * by platform's EARLY_UART_SIZE */ #define BOOT_NORMAL_REGION_IDX 0x0 +#define BOOT_DEVICE_REGION_IDX 0x1 =20 /* MPU normal memory attributes. */ #define PRBAR_NORMAL_MEM 0x30 /* SH=3D11 AP=3D00 XN=3D00 */ #define PRLAR_NORMAL_MEM 0x0f /* NS=3D0 ATTR=3D111 EN=3D1 */ =20 +/* MPU device memory attributes. */ +#define PRBAR_DEVICE_MEM 0x20 /* SH=3D10 AP=3D00 XN=3D00 */ +#define PRLAR_DEVICE_MEM 0x09 /* NS=3D0 ATTR=3D100 EN=3D1 */ + .macro write_pr, sel, prbar, prlar msr PRSELR_EL2, \sel dsb sy @@ -69,6 +76,48 @@ ENTRY(prepare_early_mappings) ret ENDPROC(prepare_early_mappings) =20 +/* + * In MMU system, setup_fixmap is used for Xen to map some essential data + * or devices in boot-time. In order to be consistent with MMU system, we + * inherit the function name for MPU system. + * setup_fixmap of MPU system will: + * - Map the early UART to MPU protection region when earlyprintk is + * enabled (The PRINT can't be used after turning on MPU but before + * setup_fixmap). + * + * Clobbers x0 - x3 + */ +ENTRY(setup_fixmap) +#ifdef CONFIG_EARLY_PRINTK + /* Map early uart to MPU device region for early printk. */ + mov x0, #BOOT_DEVICE_REGION_IDX + ldr x1, =3DCONFIG_EARLY_UART_BASE_ADDRESS + and x1, x1, #MPU_REGION_MASK + mov x3, #PRBAR_DEVICE_MEM + orr x1, x1, x3 + + ldr x2, =3DCONFIG_EARLY_UART_BASE_ADDRESS + ldr x3, =3D(CONFIG_EARLY_UART_BASE_ADDRESS + EARLY_UART_SIZE - 1) + add x2, x2, x3 + and x2, x2, #MPU_REGION_MASK + mov x3, #PRLAR_DEVICE_MEM + orr x2, x2, x3 + + /* + * Write to MPU protection region: + * x0 for pr_sel, x1 for prbar x2 for prlar + */ + write_pr x0, x1, x2 +#endif + + ret +ENDPROC(setup_fixmap) + +/* Stub of remove_identity_mapping for MPU systems */ +ENTRY(remove_identity_mapping) + ret +ENDPROC(remove_identity_mapping) + /* * Enable EL2 MPU and data cache. Because we will disable cache * with MPU at the same time, in accordance with that, we have diff --git a/xen/arch/arm/include/asm/platforms/fvp_baser.h b/xen/arch/arm/= include/asm/platforms/fvp_baser.h index 9450a411a9..acde3541a1 100644 --- a/xen/arch/arm/include/asm/platforms/fvp_baser.h +++ b/xen/arch/arm/include/asm/platforms/fvp_baser.h @@ -11,4 +11,8 @@ #define XEN_START_ADDRESS CONFIG_XEN_START_ADDRESS #endif =20 +#ifdef CONFIG_EARLY_PRINTK +#define EARLY_UART_SIZE 0x1000 +#endif + #endif /* __ASM_ARM_PLATFORMS_FVP_BASER_H__ */ --=20 2.25.1