From nobody Tue Feb 10 04:13:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13809C433F5 for ; Wed, 5 Oct 2022 11:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229721AbiJELDS (ORCPT ); Wed, 5 Oct 2022 07:03:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229531AbiJELDN (ORCPT ); Wed, 5 Oct 2022 07:03:13 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17F456CF4F for ; Wed, 5 Oct 2022 04:03:12 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id B584C1F8A3; Wed, 5 Oct 2022 11:03:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1664967790; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZjfiyOlyqF25zTBDZULVk0UdTR16lW+0ZSJokbWtjEI=; b=mybiJLJXqY902Vp/rd3sqvMwiEKnCTgtRLXgK5oq+rrLSTp2pFMmn6YH/hWAdU//eFxwAp cdVcSzknEyIofxPePN/tqIyJAEP6E22WM5xXlKVfwA0Q8zmPaXg0b3Wv1hPWQl8M5Methq bflyIfbkTWugKokBYTizibEOrCLw1Jo= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 6FD9713345; Wed, 5 Oct 2022 11:03:10 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id tT8WGm5kPWPmQgAAMHmgww (envelope-from ); Wed, 05 Oct 2022 11:03:10 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v3 1/4] xen/pv: add fault recovery control to pmu msr accesses Date: Wed, 5 Oct 2022 13:02:59 +0200 Message-Id: <20221005110302.13455-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221005110302.13455-1-jgross@suse.com> References: <20221005110302.13455-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Today pmu_msr_read() and pmu_msr_write() fall back to the safe variants of read/write MSR in case the MSR access isn't emulated via Xen. Allow the caller to select that faults should not be recovered from by passing NULL for the error pointer. Restructure the code to make it more readable. Signed-off-by: Juergen Gross Reviewed-by: Jan Beulich --- V2: - do some restructuring (Jan Beulich, Boris Ostrovsky) V3: - commit message rephrasing (Jan Beulich) - more restructuring (Boris Ostrovsky) --- arch/x86/xen/pmu.c | 66 ++++++++++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 21ecbe754cb2..0f98cb1077e3 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -131,6 +131,9 @@ static inline uint32_t get_fam15h_addr(u32 addr) =20 static inline bool is_amd_pmu_msr(unsigned int msr) { + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) + return false; + if ((msr >=3D MSR_F15H_PERF_CTL && msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) || (msr >=3D MSR_K7_EVNTSEL0 && @@ -144,6 +147,9 @@ static int is_intel_pmu_msr(u32 msr_index, int *type, i= nt *index) { u32 msr_index_pmc; =20 + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) + return false; + switch (msr_index) { case MSR_CORE_PERF_FIXED_CTR_CTRL: case MSR_IA32_DS_AREA: @@ -290,48 +296,52 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64= *val, bool is_read) return false; } =20 +static bool pmu_msr_chk_emulated(unsigned int msr, uint64_t *val, bool is_= read, + bool *emul) +{ + int type, index; + + if (is_amd_pmu_msr(msr)) + *emul =3D xen_amd_pmu_emulate(msr, val, is_read); + else if (is_intel_pmu_msr(msr, &type, &index)) + *emul =3D xen_intel_pmu_emulate(msr, val, type, index, is_read); + else + return false; + + return true; +} + bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err) { - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { - if (is_amd_pmu_msr(msr)) { - if (!xen_amd_pmu_emulate(msr, val, 1)) - *val =3D native_read_msr_safe(msr, err); - return true; - } - } else { - int type, index; + bool emulated; =20 - if (is_intel_pmu_msr(msr, &type, &index)) { - if (!xen_intel_pmu_emulate(msr, val, type, index, 1)) - *val =3D native_read_msr_safe(msr, err); - return true; - } + if (!pmu_msr_chk_emulated(msr, val, true, &emulated)) + return false; + + if (!emulated) { + *val =3D err ? native_read_msr_safe(msr, err) + : native_read_msr(msr); } =20 - return false; + return true; } =20 bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err) { uint64_t val =3D ((uint64_t)high << 32) | low; + bool emulated; =20 - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { - if (is_amd_pmu_msr(msr)) { - if (!xen_amd_pmu_emulate(msr, &val, 0)) - *err =3D native_write_msr_safe(msr, low, high); - return true; - } - } else { - int type, index; + if (!pmu_msr_chk_emulated(msr, &val, false, &emulated)) + return false; =20 - if (is_intel_pmu_msr(msr, &type, &index)) { - if (!xen_intel_pmu_emulate(msr, &val, type, index, 0)) - *err =3D native_write_msr_safe(msr, low, high); - return true; - } + if (!emulated) { + if (err) + *err =3D native_write_msr_safe(msr, low, high); + else + native_write_msr(msr, low, high); } =20 - return false; + return true; } =20 static unsigned long long xen_amd_read_pmc(int counter) --=20 2.35.3