From nobody Sat May 18 18:02:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7DDDC433F5 for ; Tue, 4 Oct 2022 08:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230268AbiJDIo1 (ORCPT ); Tue, 4 Oct 2022 04:44:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230251AbiJDIoW (ORCPT ); Tue, 4 Oct 2022 04:44:22 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 669953DF34 for ; Tue, 4 Oct 2022 01:44:21 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id AD48F1F909; Tue, 4 Oct 2022 08:44:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1664873059; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NnOBG7dPJJxOFbSXECzEyNs/pZFtg7J3uSYUDX0hJuc=; b=DVk72WoqFGUhkClh0eikyDJjWI1vrwOAqEGWlI6G7eiI8jfg0qNJyRN+eacKsCWbQbv6G4 bkzMEiTdxHzdA++LqakKAWU8Nd8qVtje9HF5nf/uMJtJLiPN4I5rWRQd2WZzoVeG+xr7WS +hmgaRSunDvSY21mr96NQwNnMLa17S0= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 66731139D2; Tue, 4 Oct 2022 08:44:19 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 3f3BF2PyO2OpVwAAMHmgww (envelope-from ); Tue, 04 Oct 2022 08:44:19 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v2 1/3] xen/pv: allow pmu msr accesses to cause GP Date: Tue, 4 Oct 2022 10:43:33 +0200 Message-Id: <20221004084335.2838-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221004084335.2838-1-jgross@suse.com> References: <20221004084335.2838-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Today pmu_msr_read() and pmu_msr_write() fall back to the safe variants of read/write MSR in case the MSR access isn't emulated via Xen. Allow the caller to select the potentially faulting variant by passing NULL for the error pointer. Restructure the code to make it more readable. Signed-off-by: Juergen Gross --- V2: - do some restructuring (Jan Beulich, Boris Ostrovsky) --- arch/x86/xen/pmu.c | 61 +++++++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 21ecbe754cb2..501b6f872d96 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -131,6 +131,9 @@ static inline uint32_t get_fam15h_addr(u32 addr) =20 static inline bool is_amd_pmu_msr(unsigned int msr) { + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) + return false; + if ((msr >=3D MSR_F15H_PERF_CTL && msr < MSR_F15H_PERF_CTR + (amd_num_counters * 2)) || (msr >=3D MSR_K7_EVNTSEL0 && @@ -144,6 +147,9 @@ static int is_intel_pmu_msr(u32 msr_index, int *type, i= nt *index) { u32 msr_index_pmc; =20 + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) + return false; + switch (msr_index) { case MSR_CORE_PERF_FIXED_CTR_CTRL: case MSR_IA32_DS_AREA: @@ -292,46 +298,45 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64= *val, bool is_read) =20 bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err) { - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { - if (is_amd_pmu_msr(msr)) { - if (!xen_amd_pmu_emulate(msr, val, 1)) - *val =3D native_read_msr_safe(msr, err); - return true; - } - } else { - int type, index; + int type, index; + bool emulated; =20 - if (is_intel_pmu_msr(msr, &type, &index)) { - if (!xen_intel_pmu_emulate(msr, val, type, index, 1)) - *val =3D native_read_msr_safe(msr, err); - return true; - } + if (is_amd_pmu_msr(msr)) + emulated =3D xen_amd_pmu_emulate(msr, val, 1); + else if (is_intel_pmu_msr(msr, &type, &index)) + emulated =3D xen_intel_pmu_emulate(msr, val, type, index, 1); + else + return false; + + if (!emulated) { + *val =3D err ? native_read_msr_safe(msr, err) + : native_read_msr(msr); } =20 - return false; + return true; } =20 bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err) { uint64_t val =3D ((uint64_t)high << 32) | low; + int type, index; + bool emulated; =20 - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { - if (is_amd_pmu_msr(msr)) { - if (!xen_amd_pmu_emulate(msr, &val, 0)) - *err =3D native_write_msr_safe(msr, low, high); - return true; - } - } else { - int type, index; + if (is_amd_pmu_msr(msr)) + emulated =3D xen_amd_pmu_emulate(msr, &val, 0); + else if (is_intel_pmu_msr(msr, &type, &index)) + emulated =3D xen_intel_pmu_emulate(msr, &val, type, index, 0); + else + return false; =20 - if (is_intel_pmu_msr(msr, &type, &index)) { - if (!xen_intel_pmu_emulate(msr, &val, type, index, 0)) - *err =3D native_write_msr_safe(msr, low, high); - return true; - } + if (!emulated) { + if (err) + *err =3D native_write_msr_safe(msr, low, high); + else + native_write_msr(msr, low, high); } =20 - return false; + return true; } =20 static unsigned long long xen_amd_read_pmc(int counter) --=20 2.35.3 From nobody Sat May 18 18:02:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1664873065; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rg7G2sE/xwQjZFXkh5AfLZ6BOzaSFVCwXC3avs7dOhM=; b=A+NxQexafoTYnVQ/mf4TVXN0GkLKIg2mP5sKyx1Gz2V3ktHdatz1HlJqgWcQIRhl5hOeoT 3Q0+qKFhx2Ufd9teMM1JVfivPQD8aszyNe/LecnT3KZRw2nHdoey3kERS7LrsUGl99ZLcS S5gceBOro6LRxBH1JdWTsKpWGfKCeuU= From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v2 2/3] xen/pv: refactor msr access functions to support safe and unsafe accesses Date: Tue, 4 Oct 2022 10:43:34 +0200 Message-Id: <20221004084335.2838-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221004084335.2838-1-jgross@suse.com> References: <20221004084335.2838-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1664873085828100003 Content-Type: text/plain; charset="utf-8" Refactor and rename xen_read_msr_safe() and xen_write_msr_safe() to support both cases of MSR accesses, safe ones and potentially GP-fault generating ones. This will prepare to no longer swallow GPs silently in xen_read_msr() and xen_write_msr(). Signed-off-by: Juergen Gross Reviewed-by: Jan Beulich --- V2: - init val in xen_do_read_msr() to 0 (Jan Beulich) --- arch/x86/xen/enlighten_pv.c | 75 +++++++++++++++++++++++++++---------- 1 file changed, 56 insertions(+), 19 deletions(-) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 9b1a58dda935..d5b0844a1b7c 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -917,14 +917,18 @@ static void xen_write_cr4(unsigned long cr4) native_write_cr4(cr4); } =20 -static u64 xen_read_msr_safe(unsigned int msr, int *err) +static u64 xen_do_read_msr(unsigned int msr, int *err) { - u64 val; + u64 val =3D 0; /* Avoid uninitialized value for safe variant. */ =20 if (pmu_msr_read(msr, &val, err)) return val; =20 - val =3D native_read_msr_safe(msr, err); + if (err) + val =3D native_read_msr_safe(msr, err); + else + val =3D native_read_msr(msr); + switch (msr) { case MSR_IA32_APICBASE: val &=3D ~X2APIC_ENABLE; @@ -933,23 +937,39 @@ static u64 xen_read_msr_safe(unsigned int msr, int *e= rr) return val; } =20 -static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned hig= h) +static void set_seg(unsigned int which, unsigned int low, unsigned int hig= h, + int *err) { - int ret; - unsigned int which; - u64 base; + u64 base =3D ((u64)high << 32) | low; + + if (HYPERVISOR_set_segment_base(which, base) =3D=3D 0) + return; =20 - ret =3D 0; + if (err) + *err =3D -EIO; + else + WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); +} =20 +/* + * Support write_msr_safe() and write_msr() semantics. + * With err =3D=3D NULL write_msr() semantics are selected. + * Supplying an err pointer requires err to be pre-initialized with 0. + */ +static void xen_do_write_msr(unsigned int msr, unsigned int low, + unsigned int high, int *err) +{ switch (msr) { - case MSR_FS_BASE: which =3D SEGBASE_FS; goto set; - case MSR_KERNEL_GS_BASE: which =3D SEGBASE_GS_USER; goto set; - case MSR_GS_BASE: which =3D SEGBASE_GS_KERNEL; goto set; - - set: - base =3D ((u64)high << 32) | low; - if (HYPERVISOR_set_segment_base(which, base) !=3D 0) - ret =3D -EIO; + case MSR_FS_BASE: + set_seg(SEGBASE_FS, low, high, err); + break; + + case MSR_KERNEL_GS_BASE: + set_seg(SEGBASE_GS_USER, low, high, err); + break; + + case MSR_GS_BASE: + set_seg(SEGBASE_GS_KERNEL, low, high, err); break; =20 case MSR_STAR: @@ -965,11 +985,28 @@ static int xen_write_msr_safe(unsigned int msr, unsig= ned low, unsigned high) break; =20 default: - if (!pmu_msr_write(msr, low, high, &ret)) - ret =3D native_write_msr_safe(msr, low, high); + if (!pmu_msr_write(msr, low, high, err)) { + if (err) + *err =3D native_write_msr_safe(msr, low, high); + else + native_write_msr(msr, low, high); + } } +} + +static u64 xen_read_msr_safe(unsigned int msr, int *err) +{ + return xen_do_read_msr(msr, err); +} + +static int xen_write_msr_safe(unsigned int msr, unsigned int low, + unsigned int high) +{ + int err =3D 0; + + xen_do_write_msr(msr, low, high, &err); =20 - return ret; + return err; } =20 static u64 xen_read_msr(unsigned int msr) --=20 2.35.3 From nobody Sat May 18 18:02:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tue, 04 Oct 2022 08:44:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c37e190f-43c0-11ed-9377-c1cf23e5d27e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1664873071; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=j+lb+y1NjPOXtKvMZH/DFSB4E2HI7Wk27OuXyDj7Pes=; b=V5kYOfYG/kj7NXn15dK5dXFgizcJc0Xl1WjROjliBeu1yo+TIE6Sr3gVqM+UWRTYj9Tfil ASTZ7BUd2XV0WR39svbS+pg2w8Egm8ZAxheUGff0g9ixjcUtg+oeLNAbxtIhGaTZ+qv1Ug qKGMIb1hvqpeMW5WsqqTFd+LstFgDrE= From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-doc@vger.kernel.org Cc: Juergen Gross , Jonathan Corbet , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v2 3/3] xen/pv: support selecting safe/unsafe msr accesses Date: Tue, 4 Oct 2022 10:43:35 +0200 Message-Id: <20221004084335.2838-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221004084335.2838-1-jgross@suse.com> References: <20221004084335.2838-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1664873095690100001 Content-Type: text/plain; charset="utf-8" Instead of always doing the safe variants for reading and writing MSRs in Xen PV guests, make the behavior controllable via Kconfig option and a boot parameter. The default will be the current behavior, which is to always use the safe variant. Signed-off-by: Juergen Gross --- .../admin-guide/kernel-parameters.txt | 6 +++++ arch/x86/xen/Kconfig | 9 +++++++ arch/x86/xen/enlighten_pv.c | 24 +++++++++++-------- 3 files changed, 29 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 426fa892d311..1bda9cf18fae 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6836,6 +6836,12 @@ Crash from Xen panic notifier, without executing late panic() code such as dumping handler. =20 + xen_msr_safe=3D [X86,XEN] + Format: + Select whether to always use non-faulting (safe) MSR + access functions when running as Xen PV guest. The + default value is controlled by CONFIG_XEN_PV_MSR_SAFE. + xen_nopvspin [X86,XEN] Disables the qspinlock slowpath using Xen PV optimizations. This parameter is obsoleted by "nopvspin" parameter, which diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig index 85246dd9faa1..9b1ec5d8c99c 100644 --- a/arch/x86/xen/Kconfig +++ b/arch/x86/xen/Kconfig @@ -92,3 +92,12 @@ config XEN_DOM0 select X86_X2APIC if XEN_PVH && X86_64 help Support running as a Xen Dom0 guest. + +config XEN_PV_MSR_SAFE + bool "Always use safe MSR accesses in PV guests" + default y + depends on XEN_PV + help + Use safe (not faulting) MSR access functions even if the MSR access + should not fault anyway. + The default can be changed by using the "xen_msr_safe" boot parameter. diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index d5b0844a1b7c..daae454191f2 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -108,6 +108,16 @@ struct tls_descs { */ static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); =20 +static __read_mostly bool xen_msr_safe =3D IS_ENABLED(CONFIG_XEN_PV_MSR_SA= FE); + +static int __init parse_xen_msr_safe(char *str) +{ + if (str) + return strtobool(str, &xen_msr_safe); + return -EINVAL; +} +early_param("xen_msr_safe", parse_xen_msr_safe); + static void __init xen_pv_init_platform(void) { /* PV guests can't operate virtio devices without grants. */ @@ -1011,22 +1021,16 @@ static int xen_write_msr_safe(unsigned int msr, uns= igned int low, =20 static u64 xen_read_msr(unsigned int msr) { - /* - * This will silently swallow a #GP from RDMSR. It may be worth - * changing that. - */ int err; =20 - return xen_read_msr_safe(msr, &err); + return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); } =20 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) { - /* - * This will silently swallow a #GP from WRMSR. It may be worth - * changing that. - */ - xen_write_msr_safe(msr, low, high); + int err; + + xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); } =20 /* This is called once we have the cpu_possible_mask */ --=20 2.35.3