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Peter Anvin" Subject: [PATCH 1/3] xen/pv: allow pmu msr accesses to cause GP Date: Mon, 26 Sep 2022 16:18:47 +0200 Message-Id: <20220926141849.21805-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220926141849.21805-1-jgross@suse.com> References: <20220926141849.21805-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1664201971246100004 Content-Type: text/plain; charset="utf-8" Today pmu_msr_read() and pmu_msr_write() fall back to the safe variants of read/write MSR in case the MSR access isn't emulated via Xen. Allow the caller to select the potentially faulting variant by passing NULL for the error pointer. Remove one level of indentation by restructuring the code a little bit. Signed-off-by: Juergen Gross --- arch/x86/xen/pmu.c | 44 ++++++++++++++++++++++++++------------------ 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 21ecbe754cb2..34b4144f6041 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -293,22 +293,24 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64= *val, bool is_read) bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err) { if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { - if (is_amd_pmu_msr(msr)) { - if (!xen_amd_pmu_emulate(msr, val, 1)) - *val =3D native_read_msr_safe(msr, err); - return true; + if (!is_amd_pmu_msr(msr)) + return false; + if (!xen_amd_pmu_emulate(msr, val, 1)) { + *val =3D err ? native_read_msr_safe(msr, err) + : native_read_msr(msr); } + return true; } else { int type, index; =20 - if (is_intel_pmu_msr(msr, &type, &index)) { - if (!xen_intel_pmu_emulate(msr, val, type, index, 1)) - *val =3D native_read_msr_safe(msr, err); - return true; + if (!is_intel_pmu_msr(msr, &type, &index)) + return false; + if (!xen_intel_pmu_emulate(msr, val, type, index, 1)) { + *val =3D err ? native_read_msr_safe(msr, err) + : native_read_msr(msr); } + return true; } - - return false; } =20 bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t high, int *err) @@ -316,22 +318,28 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, ui= nt32_t high, int *err) uint64_t val =3D ((uint64_t)high << 32) | low; =20 if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) { - if (is_amd_pmu_msr(msr)) { - if (!xen_amd_pmu_emulate(msr, &val, 0)) + if (!is_amd_pmu_msr(msr)) + return false; + if (!xen_amd_pmu_emulate(msr, &val, 0)) { + if (err) *err =3D native_write_msr_safe(msr, low, high); - return true; + else + native_write_msr(msr, low, high); } + return true; } else { int type, index; =20 - if (is_intel_pmu_msr(msr, &type, &index)) { - if (!xen_intel_pmu_emulate(msr, &val, type, index, 0)) + if (!is_intel_pmu_msr(msr, &type, &index)) + return false; + if (!xen_intel_pmu_emulate(msr, &val, type, index, 0)) { + if (err) *err =3D native_write_msr_safe(msr, low, high); - return true; + else + native_write_msr(msr, low, high); } + return true; } - - return false; } =20 static unsigned long long xen_amd_read_pmc(int counter) --=20 2.35.3 From nobody Mon Feb 9 12:11:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1664201966; cv=none; d=zohomail.com; s=zohoarc; b=UbSKtq53jzbUHJ/df6Je+NHXK+XmzAW4V49O/Zbxh6+DseRfhIEbXaDUhMeg4T5wQ9uxtQqqgpXRzjXlEdiYEczr2sajv08tK4/VjG+OMfo14IbVNc5wzfdUSfZO6oskrmkA2xO0+1foWHQhVIuA310bnTLZVgEcbKEmdAeCJMA= ARC-Message-Signature: i=1; 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h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q2WIgyc8oeY+zl5KU1xJK3+56bjqBOzQeuZ/l6BD6ls=; b=qY8RvPXiIpmNppBtHhVvR/lcYb5+KrHTOtwch6dvTPWN8X/VLj6Cw/YIS2IJ+d1ByhjLv6 J/em/IezcFP+FLxo0JYsBoM3a1BAcvDVDlg27PUngju+UZucwdMDwAW0kSQx57aTdV54Yt FjdIzmNYyktbjc3IVUg5Yiuu9DvK60Y= From: Juergen Gross To: xen-devel@lists.xenproject.org, x86@kernel.org, linux-kernel@vger.kernel.org Cc: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH 2/3] xen/pv: refactor msr access functions to support safe and unsafe accesses Date: Mon, 26 Sep 2022 16:18:48 +0200 Message-Id: <20220926141849.21805-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220926141849.21805-1-jgross@suse.com> References: <20220926141849.21805-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1664201969315100001 Content-Type: text/plain; charset="utf-8" Refactor and rename xen_read_msr_safe() and xen_write_msr_safe() to support both cases of MSR accesses, safe ones and potentially GP-fault generating ones. This will prepare to no longer swallow GPs silently in xen_read_msr() and xen_write_msr(). Signed-off-by: Juergen Gross --- arch/x86/xen/enlighten_pv.c | 73 ++++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 18 deletions(-) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 0ed2e487a693..4e68e047df94 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -916,14 +916,18 @@ static void xen_write_cr4(unsigned long cr4) native_write_cr4(cr4); } =20 -static u64 xen_read_msr_safe(unsigned int msr, int *err) +static u64 xen_do_read_msr(unsigned int msr, int *err) { u64 val; =20 if (pmu_msr_read(msr, &val, err)) return val; =20 - val =3D native_read_msr_safe(msr, err); + if (err) + val =3D native_read_msr_safe(msr, err); + else + val =3D native_read_msr(msr); + switch (msr) { case MSR_IA32_APICBASE: val &=3D ~X2APIC_ENABLE; @@ -932,23 +936,39 @@ static u64 xen_read_msr_safe(unsigned int msr, int *e= rr) return val; } =20 -static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned hig= h) +static void set_seg(unsigned int which, unsigned int low, unsigned int hig= h, + int *err) { - int ret; - unsigned int which; - u64 base; + u64 base =3D ((u64)high << 32) | low; + + if (HYPERVISOR_set_segment_base(which, base) =3D=3D 0) + return; =20 - ret =3D 0; + if (err) + *err =3D -EIO; + else + WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); +} =20 +/* + * Support write_msr_safe() and write_msr() semantics. + * With err =3D=3D NULL write_msr() semantics are selected. + * Supplying an err pointer requires err to be pre-initialized with 0. + */ +static void xen_do_write_msr(unsigned int msr, unsigned int low, + unsigned int high, int *err) +{ switch (msr) { - case MSR_FS_BASE: which =3D SEGBASE_FS; goto set; - case MSR_KERNEL_GS_BASE: which =3D SEGBASE_GS_USER; goto set; - case MSR_GS_BASE: which =3D SEGBASE_GS_KERNEL; goto set; - - set: - base =3D ((u64)high << 32) | low; - if (HYPERVISOR_set_segment_base(which, base) !=3D 0) - ret =3D -EIO; + case MSR_FS_BASE: + set_seg(SEGBASE_FS, low, high, err); + break; + + case MSR_KERNEL_GS_BASE: + set_seg(SEGBASE_GS_USER, low, high, err); + break; + + case MSR_GS_BASE: + set_seg(SEGBASE_GS_KERNEL, low, high, err); break; =20 case MSR_STAR: @@ -964,11 +984,28 @@ static int xen_write_msr_safe(unsigned int msr, unsig= ned low, unsigned high) break; =20 default: - if (!pmu_msr_write(msr, low, high, &ret)) - ret =3D native_write_msr_safe(msr, low, high); + if (!pmu_msr_write(msr, low, high, err)) { + if (err) + *err =3D native_write_msr_safe(msr, low, high); + else + native_write_msr(msr, low, high); + } } +} + +static u64 xen_read_msr_safe(unsigned int msr, int *err) +{ + return xen_do_read_msr(msr, err); +} + +static int xen_write_msr_safe(unsigned int msr, unsigned int low, + unsigned int high) +{ + int err =3D 0; + + xen_do_write_msr(msr, low, high, &err); =20 - return ret; + return err; } =20 static u64 xen_read_msr(unsigned int msr) --=20 2.35.3 From nobody Mon Feb 9 12:11:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Mon, 26 Sep 2022 14:19:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 30a5c8d3-3da6-11ed-9374-c1cf23e5d27e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1664201950; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=acJkGEJzQvXK3ntpRB7CEDesvJKyVtqSHHdOsYKLzIg=; b=i1dwUiOyCBw7IR7aEH1PBRg4a9gQzwDV01bgDjlihYYT+NCz760Ilh718xzjV+CMcd+1gU Ysl9/VyM6OsgmljS7s7h0UDr+PBJX3FQhki4eIpF0+Av66TnrmdN/ZlEiCcnlBWkWVVSNE WoPIKXRUUFnLgAouJlYWO//iNsY5ADU= From: Juergen Gross To: xen-devel@lists.xenproject.org, x86@kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Juergen Gross , Jonathan Corbet , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH 3/3] xen/pv: support selecting safe/unsafe msr accesses Date: Mon, 26 Sep 2022 16:18:49 +0200 Message-Id: <20220926141849.21805-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220926141849.21805-1-jgross@suse.com> References: <20220926141849.21805-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1664201973192100007 Content-Type: text/plain; charset="utf-8" Instead of always doing the safe variants for reading and writing MSRs in Xen PV guests, make the behavior controllable via Kconfig option and a boot parameter. The default will be the current behavior, which is to always use the safe variant. Signed-off-by: Juergen Gross --- .../admin-guide/kernel-parameters.txt | 6 +++++ arch/x86/xen/Kconfig | 9 +++++++ arch/x86/xen/enlighten_pv.c | 24 +++++++++++-------- 3 files changed, 29 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 426fa892d311..1bda9cf18fae 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6836,6 +6836,12 @@ Crash from Xen panic notifier, without executing late panic() code such as dumping handler. =20 + xen_msr_safe=3D [X86,XEN] + Format: + Select whether to always use non-faulting (safe) MSR + access functions when running as Xen PV guest. The + default value is controlled by CONFIG_XEN_PV_MSR_SAFE. + xen_nopvspin [X86,XEN] Disables the qspinlock slowpath using Xen PV optimizations. This parameter is obsoleted by "nopvspin" parameter, which diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig index 85246dd9faa1..9b1ec5d8c99c 100644 --- a/arch/x86/xen/Kconfig +++ b/arch/x86/xen/Kconfig @@ -92,3 +92,12 @@ config XEN_DOM0 select X86_X2APIC if XEN_PVH && X86_64 help Support running as a Xen Dom0 guest. + +config XEN_PV_MSR_SAFE + bool "Always use safe MSR accesses in PV guests" + default y + depends on XEN_PV + help + Use safe (not faulting) MSR access functions even if the MSR access + should not fault anyway. + The default can be changed by using the "xen_msr_safe" boot parameter. diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 4e68e047df94..6b0e5d4c485a 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -108,6 +108,16 @@ struct tls_descs { */ static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); =20 +static __read_mostly bool xen_msr_safe =3D IS_ENABLED(CONFIG_XEN_PV_MSR_SA= FE); + +static int __init parse_xen_msr_safe(char *str) +{ + if (str) + return strtobool(str, &xen_msr_safe); + return -EINVAL; +} +early_param("xen_msr_safe", parse_xen_msr_safe); + static void __init xen_pv_init_platform(void) { /* PV guests can't operate virtio devices without grants. */ @@ -1010,22 +1020,16 @@ static int xen_write_msr_safe(unsigned int msr, uns= igned int low, =20 static u64 xen_read_msr(unsigned int msr) { - /* - * This will silently swallow a #GP from RDMSR. It may be worth - * changing that. - */ int err; =20 - return xen_read_msr_safe(msr, &err); + return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); } =20 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) { - /* - * This will silently swallow a #GP from WRMSR. It may be worth - * changing that. - */ - xen_write_msr_safe(msr, low, high); + int err; + + xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); } =20 /* This is called once we have the cpu_possible_mask */ --=20 2.35.3