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[79.136.84.253]) by smtp.gmail.com with ESMTPSA id f3-20020a05651c02c300b0025fdf1af42asm4815394ljo.78.2022.09.19.02.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Sep 2022 02:12:44 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 39a953fc-37fb-11ed-9647-05401a9f4f97 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=NUUOOqYydiRztk2+PXHvZdFqULJvxVlGXUcw0oHBVH8=; b=pOsW907B4i0eugdEEMl5LxmCXFPIdoH958yELCS0//NTftT/UReY0PZxEZ7NzXMPOY vN0wvrNrSHVqywfibzPJ87+zN/Ws1YI1+guEKJyM7zWNJP5t6WQuCk5zbt28j5c7cR5V 4/B71UkVlvaky0/DrgRqMhlcquWI0/lDSSWPsjYfP2pXELO4g1V+xIgM9GDRmB6pjpLJ gn4cUbq5gxM20JfY76j20uIo96soNq3fSLwSb1zKgblyGvM0RBNd89JH433IKWdXcwaM 7IWzwmQQkoD7jtXorQwLmvvrH4MTRroTsM0TvXSpiIT5Vy2lbegtdabxScRB+BypjdPH hxuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=NUUOOqYydiRztk2+PXHvZdFqULJvxVlGXUcw0oHBVH8=; b=CatYY8vJCxWUtfMaE2UiNkqZM9ev35f5iSiCLQHnR/tMqZjQoYOafL/LNmvLZniDH3 TuNYaDIkAFu5xYXVIlBI8DXhm+ujCmwQF1g4IfrgKZFw+mQzxAD7w8/hp65HncrcTFcK QQHhHR7Of2uAUhAFnGuVjxC084Isy52kQ2AwG28Fm0R74g817so9YoeSyuUrYsEEAw2X otDijT4NP5mKPnsbM9khAzwoX18gpbPQtHtf6FbwPqlUmqqgUe+BhkwiT5ew9+QUQfh0 GCcWuCfHEKQ/W9fEkxV2XMhq59wC+O6QwL8NI3kcug0IRSOh92oH8iIO28FfjPf3h1UF 3/+g== X-Gm-Message-State: ACrzQf0Mn6mZRXMyPi+3fVvOP+9uPFmiGYgrrvkSPQhtej7IzDCWqZZg LU0TvZ6hgN5or9Ogmjf3fZHGGyNuD2YtMQ== X-Google-Smtp-Source: AMsMyM5s2r1MCsUEqCwIfhgAOWd42+fV7GRVsCB/L54JET58STh/4c5m0fGQ7ZiUkFrJNDjeUYy5Iw== X-Received: by 2002:a2e:940f:0:b0:261:b9ca:6207 with SMTP id i15-20020a2e940f000000b00261b9ca6207mr4956248ljh.192.1663578765398; Mon, 19 Sep 2022 02:12:45 -0700 (PDT) From: Jens Wiklander To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand.Marquis@arm.com, Anthony PERARD , Juergen Gross , Wei Liu , Marc Bonnici , Achin Gupta , Jens Wiklander , Luca Fancellu Subject: [PATCH v6 1/9] xen/arm: smccc: add support for SMCCCv1.2 extended input/output registers Date: Mon, 19 Sep 2022 11:12:30 +0200 Message-Id: <20220919091238.2068052-2-jens.wiklander@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220919091238.2068052-1-jens.wiklander@linaro.org> References: <20220919091238.2068052-1-jens.wiklander@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1663578797222100005 Content-Type: text/plain; charset="utf-8" SMCCC v1.2 [1] AArch64 allows x0-x17 to be used as both parameter registers and result registers for the SMC and HVC instructions. Arm Firmware Framework for Armv8-A specification makes use of x0-x7 as parameter and result registers. Let us add new interface to support this extended set of input/output registers. This is based on 3fdc0cb59d97 ("arm64: smccc: Add support for SMCCCv1.2 extended input/output registers") by Sudeep Holla from the Linux kernel The SMCCC version reported to the VM is bumped to 1.2 in order to support handling FF-A messages. [1] https://developer.arm.com/documentation/den0028/c/?lang=3Den Reviewed-by: Luca Fancellu Signed-off-by: Jens Wiklander --- xen/arch/arm/arm64/asm-offsets.c | 9 +++++++ xen/arch/arm/arm64/smc.S | 42 ++++++++++++++++++++++++++++++++ xen/arch/arm/include/asm/smccc.h | 40 ++++++++++++++++++++++++++++++ xen/arch/arm/vsmc.c | 2 +- 4 files changed, 92 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/asm-offsets.c b/xen/arch/arm/arm64/asm-offs= ets.c index 280ddb55bfd4..1721e1ed26e1 100644 --- a/xen/arch/arm/arm64/asm-offsets.c +++ b/xen/arch/arm/arm64/asm-offsets.c @@ -56,6 +56,15 @@ void __dummy__(void) BLANK(); OFFSET(SMCCC_RES_a0, struct arm_smccc_res, a0); OFFSET(SMCCC_RES_a2, struct arm_smccc_res, a2); + OFFSET(ARM_SMCCC_1_2_REGS_X0_OFFS, struct arm_smccc_1_2_regs, a0); + OFFSET(ARM_SMCCC_1_2_REGS_X2_OFFS, struct arm_smccc_1_2_regs, a2); + OFFSET(ARM_SMCCC_1_2_REGS_X4_OFFS, struct arm_smccc_1_2_regs, a4); + OFFSET(ARM_SMCCC_1_2_REGS_X6_OFFS, struct arm_smccc_1_2_regs, a6); + OFFSET(ARM_SMCCC_1_2_REGS_X8_OFFS, struct arm_smccc_1_2_regs, a8); + OFFSET(ARM_SMCCC_1_2_REGS_X10_OFFS, struct arm_smccc_1_2_regs, a10); + OFFSET(ARM_SMCCC_1_2_REGS_X12_OFFS, struct arm_smccc_1_2_regs, a12); + OFFSET(ARM_SMCCC_1_2_REGS_X14_OFFS, struct arm_smccc_1_2_regs, a14); + OFFSET(ARM_SMCCC_1_2_REGS_X16_OFFS, struct arm_smccc_1_2_regs, a16); } =20 /* diff --git a/xen/arch/arm/arm64/smc.S b/xen/arch/arm/arm64/smc.S index 91bae62dd4d2..fc6b676e2ee3 100644 --- a/xen/arch/arm/arm64/smc.S +++ b/xen/arch/arm/arm64/smc.S @@ -27,3 +27,45 @@ ENTRY(__arm_smccc_1_0_smc) stp x2, x3, [x4, #SMCCC_RES_a2] 1: ret + +/* + * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, + * struct arm_smccc_1_2_regs *res) + */ +ENTRY(arm_smccc_1_2_smc) + /* Save `res` and free a GPR that won't be clobbered by SMC call */ + stp x1, x19, [sp, #-16]! + + /* Ensure `args` won't be clobbered while loading regs in next step */ + mov x19, x0 + + /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */ + ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] + ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] + ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] + ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] + ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] + ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] + ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] + ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] + ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] + + smc #0 + + /* Load the `res` from the stack */ + ldr x19, [sp] + + /* Store the registers x0 - x17 into the result structure */ + stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS] + stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS] + stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS] + stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS] + stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS] + stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS] + stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS] + stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS] + stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS] + + /* Restore original x19 */ + ldp xzr, x19, [sp], #16 + ret diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index b3dbeecc90ad..b5e3f67eb34e 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -33,6 +33,7 @@ =20 #define ARM_SMCCC_VERSION_1_0 SMCCC_VERSION(1, 0) #define ARM_SMCCC_VERSION_1_1 SMCCC_VERSION(1, 1) +#define ARM_SMCCC_VERSION_1_2 SMCCC_VERSION(1, 2) =20 /* * This file provides common defines for ARM SMC Calling Convention as @@ -265,6 +266,45 @@ void __arm_smccc_1_0_smc(register_t a0, register_t a1,= register_t a2, else \ arm_smccc_1_0_smc(__VA_ARGS__); \ } while ( 0 ) + +/** + * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call + * @a0-a17 argument values from registers 0 to 17 + */ +struct arm_smccc_1_2_regs { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long a8; + unsigned long a9; + unsigned long a10; + unsigned long a11; + unsigned long a12; + unsigned long a13; + unsigned long a14; + unsigned long a15; + unsigned long a16; + unsigned long a17; +}; + +/** + * arm_smccc_1_2_smc() - make SMC calls + * @args: arguments passed via struct arm_smccc_1_2_regs + * @res: result values via struct arm_smccc_1_2_regs + * + * This function is used to make SMC calls following SMC Calling Convention + * v1.2 or above. The content of the supplied param are copied from the + * structure to registers prior to the SMC instruction. The return values + * are updated with the content from registers on return from the SMC + * instruction. + */ +void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, + struct arm_smccc_1_2_regs *res); #endif /* CONFIG_ARM_64 */ =20 #endif /* __ASSEMBLY__ */ diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 676740ef1520..6f90c08a6304 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -93,7 +93,7 @@ static bool handle_arch(struct cpu_user_regs *regs) switch ( fid ) { case ARM_SMCCC_VERSION_FID: - set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_1); + set_user_reg(regs, 0, ARM_SMCCC_VERSION_1_2); return true; =20 case ARM_SMCCC_ARCH_FEATURES_FID: --=20 2.31.1