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Peter Anvin" Subject: [PATCH v2 05/10] x86/mtrr: split generic_set_all() Date: Sat, 20 Aug 2022 11:25:28 +0200 Message-Id: <20220820092533.29420-6-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220820092533.29420-1-jgross@suse.com> References: <20220820092533.29420-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1660987573682100005 Content-Type: text/plain; charset="utf-8" Split generic_set_all() into multiple parts, while moving the main function body into cacheinfo.c. This prepares the support of PAT without needing MTRR support by moving the main function body of generic_set_all() into cacheinfo.c while renaming it to cache_cpu_init(). The MTRR specific parts are moved into a dedicated small function called by cache_cpu_init(). The PAT and MTRR specific functions are called conditionally based on the cache_generic bit settings. The setting of smp_changes_mask is merged into the (new) function mtrr_generic_set_state() used to call set_mtrr_state(). It was probably split in ancient times, as atomic operations while running uncached might be quite expensive, but OTOH only systems with a broken BIOS should ever require to set any bit in smp_changes_mask, so just hurting those devices with a penalty of a few microseconds during boot shouldn't be a real issue. Signed-off-by: Juergen Gross --- V2: - new patch --- arch/x86/include/asm/cacheinfo.h | 1 + arch/x86/include/asm/mtrr.h | 2 ++ arch/x86/kernel/cpu/cacheinfo.c | 19 +++++++++++++++++++ arch/x86/kernel/cpu/mtrr/generic.c | 15 ++------------- 4 files changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cachei= nfo.h index 313a6920d0f9..563d9cb5fcf5 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -12,5 +12,6 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, i= nt cpu); =20 void cache_disable(void); void cache_enable(void); +void cache_cpu_init(void); =20 #endif /* _ASM_X86_CACHEINFO_H */ diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 12a16caed395..986249a2b9b6 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -50,6 +50,7 @@ extern int mtrr_trim_uncached_memory(unsigned long end_pf= n); extern int amd_special_default_mtrr(void); void mtrr_disable(void); void mtrr_enable(void); +void mtrr_generic_set_state(void); # else static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { @@ -91,6 +92,7 @@ static inline void mtrr_centaur_report_mcr(int mcr, u32 l= o, u32 hi) #define mtrr_bp_restore() do {} while (0) #define mtrr_disable() do {} while (0) #define mtrr_enable() do {} while (0) +#define mtrr_generic_set_state() do {} while (0) # endif =20 #ifdef CONFIG_COMPAT diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 47e2c72fa8a4..36378604ec61 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1120,3 +1120,22 @@ void cache_enable(void) __releases(cache_disable_loc= k) =20 raw_spin_unlock(&cache_disable_lock); } + +void cache_cpu_init(void) +{ + unsigned long flags; + + local_irq_save(flags); + cache_disable(); + + /* Set MTRR state. */ + if (cache_generic & CACHE_GENERIC_MTRR) + mtrr_generic_set_state(); + + /* Set PAT. */ + if (cache_generic & CACHE_GENERIC_PAT) + pat_init(); + + cache_enable(); + local_irq_restore(flags); +} diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index a9ac159b1566..0be6d43ec1fe 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -736,30 +736,19 @@ void mtrr_enable(void) mtrr_wrmsr(MSR_MTRRdefType, *lo, *hi); } =20 -static void generic_set_all(void) +void mtrr_generic_set_state(void) { unsigned long mask, count; - unsigned long flags; - - local_irq_save(flags); - cache_disable(); =20 /* Actually set the state */ mask =3D set_mtrr_state(); =20 - /* also set PAT */ - pat_init(); - - cache_enable(); - local_irq_restore(flags); - /* Use the atomic bitops to update the global mask */ for (count =3D 0; count < sizeof(mask) * 8; ++count) { if (mask & 0x01) set_bit(count, &smp_changes_mask); mask >>=3D 1; } - } =20 /** @@ -859,7 +848,7 @@ int positive_have_wrcomb(void) * Generic structure... */ const struct mtrr_ops generic_mtrr_ops =3D { - .set_all =3D generic_set_all, + .set_all =3D cache_cpu_init, .get =3D generic_get_mtrr, .get_free_region =3D generic_get_free_region, .set =3D generic_set_mtrr, --=20 2.35.3