From nobody Fri Apr 26 14:36:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1651751984637249.1278655706351; Thu, 5 May 2022 04:59:44 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.322047.543239 (Exim 4.92) (envelope-from ) id 1nma8f-0000Ag-Oo; Thu, 05 May 2022 11:59:21 +0000 Received: by outflank-mailman (output) from mailman id 322047.543239; Thu, 05 May 2022 11:59:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nma8f-0000AZ-LW; Thu, 05 May 2022 11:59:21 +0000 Received: by outflank-mailman (input) for mailman id 322047; Thu, 05 May 2022 11:59:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nma8e-0000AS-G4 for xen-devel@lists.xenproject.org; Thu, 05 May 2022 11:59:20 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id cb03a216-cc6a-11ec-a406-831a346695d4; Thu, 05 May 2022 13:59:18 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FACE106F; Thu, 5 May 2022 04:59:18 -0700 (PDT) Received: from e129167.arm.com (unknown [10.57.3.137]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4CE4F3F885; Thu, 5 May 2022 04:59:16 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: cb03a216-cc6a-11ec-a406-831a346695d4 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Catalin Marinas Subject: [PATCH v2] xen/arm: Avoid overflow using MIDR_IMPLEMENTOR_MASK Date: Thu, 5 May 2022 13:59:06 +0200 Message-Id: <20220505115906.380416-1-michal.orzel@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1651751986089100001 Content-Type: text/plain; charset="utf-8" Value of macro MIDR_IMPLEMENTOR_MASK exceeds the range of integer and can lead to overflow. Currently there is no issue as it is used in an expression implicitly casted to u32 in MIDR_IS_CPU_MODEL_RANGE. To avoid possible problems, fix the macro. Signed-off-by: Michal Orzel Link: https://lore.kernel.org/r/20220426070603.56031-1-michal.orzel@arm.com Signed-off-by: Catalin Marinas Origin: git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git (48e6f22e25= a4) Acked-by: Catalin Marinas --- Changes since v1: - add Origin tag as the patch was merged in upstream arm64 linux tree --- xen/arch/arm/include/asm/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/as= m/processor.h index 852b5f3c24..7a1c4c4410 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -39,7 +39,7 @@ #define MIDR_VARIANT(midr) \ (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) #define MIDR_IMPLEMENTOR_SHIFT 24 -#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) =20 --=20 2.25.1