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d="scan'208";a="68229048" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH] x86/cpuid: Clobber CPUID leaves 0x800000{1d..20} Date: Thu, 7 Apr 2022 02:01:21 +0100 Message-ID: <20220407010121.11301-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1649293345295100001 c/s 1a914256dca5 increased the AMD max leaf from 0x8000001c to 0x80000021, = but did not adjust anything in the calculate_*_policy() chain. As a result, on hardware supporting these leaves, we read the real hardware values into the raw policy, then copy into host, and all the way into the PV/HVM default policies. All 4 of these leaves have enable bits (first two by TopoExt, next by SEV, next by PQOS), so any software following the rules is fine and will leave t= hem alone. However, leaf 0x8000001d takes a subleaf input and at least two userspace utilities have been observed to loop indefinitely under Xen (clea= rly waiting for eax to report "no more cache levels"). Such userspace is buggy, but Xen's behaviour isn't great either. In the short term, clobber all information in these leaves. This is a giant bodge, but there are complexities with implementing all of these leaves properly. Fixes: 1a914256dca5 ("x86/cpuid: support LFENCE always serialising CPUID bi= t") Link: https://github.com/QubesOS/qubes-issues/issues/7392 Reported-by: fosslinux Reported-by: Marek Marczykowski-G=C3=B3recki Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu I was hoping to do something better, but it turned into a rats nest, and th= is fix wants backporting. It turns out that Intel leaf 4 and AMD leaf 0x8000001d are *almost* identic= al. They differ by the "complex" bit in edx, and the $X-per-cache fields in the top of eax (Intel is threads-per-cache, AMD is cores-per-cache and lacks the cores-per-package field). As neither vendor implement each others version, I'm incredibly tempted to reuse p->cache for both, rather than doubling the storage space. Reading t= he data out is easy to key on p->extd.topoext. Writing the data can be done without any further complexity if we simply trust the sending side to have = its indices the proper way around. Particularly, this avoids needing to ensure that p->extd.topoext is out of order and at the head of the stream. Though= ts? --- xen/arch/x86/cpuid.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index bb554b06a73f..7e0b39569847 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -328,8 +328,15 @@ static void recalculate_misc(struct cpuid_policy *p) =20 zero_leaves(p->extd.raw, 0xb, 0x18); =20 + /* 0x19 - TLB details. Pass through. */ + /* 0x1a - Perf hints. Pass through. */ + p->extd.raw[0x1b] =3D EMPTY_LEAF; /* IBS - not supported. */ p->extd.raw[0x1c] =3D EMPTY_LEAF; /* LWP - not supported. */ + p->extd.raw[0x1d] =3D EMPTY_LEAF; /* TopoExt Cache */ + p->extd.raw[0x1e] =3D EMPTY_LEAF; /* TopoExt APIC ID/Core/Node */ + p->extd.raw[0x1f] =3D EMPTY_LEAF; /* SEV */ + p->extd.raw[0x20] =3D EMPTY_LEAF; /* Platform QoS */ break; } } --=20 2.11.0