From nobody Fri May 17 02:03:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; a=rsa-sha256; t=1646824916; cv=none; d=zohomail.com; s=zohoarc; b=ZD+ZsHtnLftEgK7um1SeskoVSgMND8Mitn1aYAHYTiW+F2V8qqeVmq7rRphrrPoj8pQCEbV1YmTgRi3DatfPY9YPJxB+ZlP19rlFJLZ58/2FvXITNWD/JL5X4FNJmvbUcjEfRXOEvGmfISkIwG4D0435zlluashNsnwzvzg8e6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646824916; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Ia0Jnbi/QUOonrg8XOxt2CtfmBWEI2enlPU5FZKhQo=; b=ENe75/fTdQu9HFWnHL6RuPjkqrkqcdPkMX4Z/0zqt7WE5z8SDZcNAkSf4+A9wjBz7qtEIXtQdDPdgFPA0uJ/F1LageobPTcwr63w21OeCtG461uXMQkiuN0vO6b8P8kzD2hulNKUrUZH/NLauATZVE2C01ZZfA7FXB/C8s3xCgs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1646824916302584.3623261887348; Wed, 9 Mar 2022 03:21:56 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.287730.487875 (Exim 4.92) (envelope-from ) id 1nRuNn-0007Ck-SH; Wed, 09 Mar 2022 11:21:31 +0000 Received: by outflank-mailman (output) from mailman id 287730.487875; Wed, 09 Mar 2022 11:21:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nRuNn-0007CS-N1; Wed, 09 Mar 2022 11:21:31 +0000 Received: by outflank-mailman (input) for mailman id 287730; Wed, 09 Mar 2022 11:21:31 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nRuNm-0007AU-VH for xen-devel@lists.xenproject.org; Wed, 09 Mar 2022 11:21:30 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nRuNm-0002kI-Eh; Wed, 09 Mar 2022 11:21:30 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1nRuNm-0004wn-6U; Wed, 09 Mar 2022 11:21:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=8Ia0Jnbi/QUOonrg8XOxt2CtfmBWEI2enlPU5FZKhQo=; b=gCBf5W05J34Vo7gLWv0PbgzeQK 35rH3yeNxuOHfEYgvJbciWMHAF2nflPFQcLZZ0LJEn7XQ2+tJjqMfTuKaD4WvQ0NPxoGO6maIxq5H C3wUowuue0jN9Iou6WPDyJA5UJ5+lHfuCTnhUpjvSfLSbLaB8iRs0GsQV2L3rj5t36SA=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: marco.solieri@minervasys.tech, lucmiccio@gmail.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH early-RFC 1/5] xen/arm: Clean-up the memory layout Date: Wed, 9 Mar 2022 11:20:44 +0000 Message-Id: <20220309112048.17377-2-julien@xen.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220309112048.17377-1-julien@xen.org> References: <20220309112048.17377-1-julien@xen.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1646824918279100001 Content-Type: text/plain; charset="utf-8" From: Julien Grall In a follow-up patch, the base address for the common mappings will vary between arm32 and arm64. To avoid any duplication, define every mapping in the common region from the previous one. Take the opportunity to add mising *_SIZE for some mappings. Signed-off-by: Julien Grall Reviewed-by: Bertrand Marquis --- After the next patch, the term "common" will sound strange because the base address is different. Any better suggestion? --- xen/arch/arm/include/asm/config.h | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/c= onfig.h index aedb586c8d27..5db28a8dbd56 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -107,16 +107,26 @@ * Unused */ =20 -#define XEN_VIRT_START _AT(vaddr_t,0x00200000) -#define FIXMAP_ADDR(n) (_AT(vaddr_t,0x00400000) + (n) * PAGE_SIZE) +#define COMMON_VIRT_START _AT(vaddr_t, 0) =20 -#define BOOT_FDT_VIRT_START _AT(vaddr_t,0x00600000) -#define BOOT_FDT_SLOT_SIZE MB(4) -#define BOOT_FDT_VIRT_END (BOOT_FDT_VIRT_START + BOOT_FDT_SLOT_SIZE) +#define XEN_VIRT_START (COMMON_VIRT_START + MB(2)) +#define XEN_SLOT_SIZE MB(2) +#define XEN_VIRT_END (XEN_VIRT_START + XEN_SLOT_SIZE) + +#define FIXMAP_VIRT_START XEN_VIRT_END +#define FIXMAP_SLOT_SIZE MB(2) +#define FIXMAP_VIRT_END (FIXMAP_VIRT_START + FIXMAP_SLOT_SIZE) + +#define FIXMAP_ADDR(n) (FIXMAP_VIRT_START + (n) * PAGE_SIZE) + +#define BOOT_FDT_VIRT_START FIXMAP_VIRT_END +#define BOOT_FDT_SLOT_SIZE MB(4) +#define BOOT_FDT_VIRT_END (BOOT_FDT_VIRT_START + BOOT_FDT_SLOT_SIZE) =20 #ifdef CONFIG_LIVEPATCH -#define LIVEPATCH_VMAP_START _AT(vaddr_t,0x00a00000) -#define LIVEPATCH_VMAP_END (LIVEPATCH_VMAP_START + MB(2)) +#define LIVEPATCH_VMAP_START BOOT_FDT_VIRT_END +#define LIVEPATCH_SLOT_SIZE MB(2) +#define LIVEPATCH_VMAP_END (LIVEPATCH_VMAP_START + LIVEPATCH_SLOT_SIZE) #endif =20 #define HYPERVISOR_VIRT_START XEN_VIRT_START --=20 2.32.0 From nobody Fri May 17 02:03:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 09 Mar 2022 11:21:32 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nRuNn-0002kV-Jy; Wed, 09 Mar 2022 11:21:31 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1nRuNn-0004wn-CE; Wed, 09 Mar 2022 11:21:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=dYgEWr81tlTzWi28Pdn1NFHJfMGO9dd29hy4ZTHlKlQ=; b=nCGiFSchNCffHryZ9zn6E4ovmE qeyTdgG1TVW0VfYQcAHo5MD0Baz2sqTtvX87CZV9WBcOcrmiTBZFPN7U4bF0i2yihphkS6o1t0w4K P4MJtr7CjEeAOW124yqnZTiSU0thzSEtvEg+Yr7GQKX5L1ebFV6OZhlg8ocgVdrrHEUc=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: marco.solieri@minervasys.tech, lucmiccio@gmail.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH early-RFC 2/5] xen/arm64: Rework the memory layout Date: Wed, 9 Mar 2022 11:20:45 +0000 Message-Id: <20220309112048.17377-3-julien@xen.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220309112048.17377-1-julien@xen.org> References: <20220309112048.17377-1-julien@xen.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1646824911549100004 Content-Type: text/plain; charset="utf-8" From: Julien Grall Xen is currently not fully compliant with the Arm because it will switch the TTBR with the MMU on. In order to be compliant, we need to disable the MMU before switching the TTBR. The implication is the page-tables should contain an identity mapping of the code switching the TTBR. If we don't rework the memory layout, we would need to find a virtual address that matches a physical address and doesn't clash with the static virtual regions. This can be a bit tricky. On arm64, the memory layout has plenty of unused space. In most of the case we expect Xen to be loaded in low memory. The memory layout is reshuffled to keep the 0th slot free. Xen will now be loaded at (512GB + 2MB). This requires a slight tweak of the boot code as XEN_VIRT_START cannot be used as an immediate. Signed-off-by: Julien Grall --- TODO: - I vaguely recall that one of the early platform we supported add the memory starting in high memory (> 1TB). I need to check whether the new layout will be fine. - Update the documentation to reflect the new layout --- xen/arch/arm/arm64/head.S | 3 ++- xen/arch/arm/include/asm/config.h | 20 ++++++++++++++------ xen/arch/arm/mm.c | 14 +++++++------- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 66d862fc8137..878649280d73 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -594,7 +594,8 @@ create_page_tables: * need an additional 1:1 mapping, the virtual mapping will * suffice. */ - cmp x19, #XEN_VIRT_START + ldr x0, =3DXEN_VIRT_START + cmp x19, x0 bne 1f ret 1: diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/c= onfig.h index 5db28a8dbd56..b2f31a914103 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -107,8 +107,20 @@ * Unused */ =20 +#ifdef CONFIG_ARM_32 + #define COMMON_VIRT_START _AT(vaddr_t, 0) =20 +#else + +#define SLOT0_ENTRY_BITS 39 +#define SLOT0(slot) (_AT(vaddr_t,slot) << SLOT0_ENTRY_BITS) +#define SLOT0_ENTRY_SIZE SLOT0(1) + +#define COMMON_VIRT_START SLOT(1) + +#endif + #define XEN_VIRT_START (COMMON_VIRT_START + MB(2)) #define XEN_SLOT_SIZE MB(2) #define XEN_VIRT_END (XEN_VIRT_START + XEN_SLOT_SIZE) @@ -161,14 +173,10 @@ =20 #else /* ARM_64 */ =20 -#define SLOT0_ENTRY_BITS 39 -#define SLOT0(slot) (_AT(vaddr_t,slot) << SLOT0_ENTRY_BITS) -#define SLOT0_ENTRY_SIZE SLOT0(1) - -#define VMAP_VIRT_START GB(1) +#define VMAP_VIRT_START (SLOT0(1) + GB(1)) #define VMAP_VIRT_END (VMAP_VIRT_START + GB(1)) =20 -#define FRAMETABLE_VIRT_START GB(32) +#define FRAMETABLE_VIRT_START (SLOT0(1) + GB(32)) #define FRAMETABLE_SIZE GB(32) #define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - = 1) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6b7c41d827ca..75ed9a3ce249 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -187,11 +187,10 @@ static void __init __maybe_unused build_assertions(vo= id) BUILD_BUG_ON(DIRECTMAP_VIRT_START & ~FIRST_MASK); #endif /* Page table structure constraints */ -#ifdef CONFIG_ARM_64 - BUILD_BUG_ON(zeroeth_table_offset(XEN_VIRT_START)); -#endif BUILD_BUG_ON(first_table_offset(XEN_VIRT_START)); +#ifdef CONFIG_ARM_32 BUILD_BUG_ON(second_linear_offset(XEN_VIRT_START) >=3D XEN_PT_LPAE_ENT= RIES); +#endif #ifdef CONFIG_DOMAIN_PAGE BUILD_BUG_ON(DOMHEAP_VIRT_START & ~FIRST_MASK); #endif @@ -611,10 +610,11 @@ void __init setup_pagetables(unsigned long boot_phys_= offset) phys_offset =3D boot_phys_offset; =20 #ifdef CONFIG_ARM_64 - p =3D (void *) xen_pgtable; - p[0] =3D pte_of_xenaddr((uintptr_t)xen_first); - p[0].pt.table =3D 1; - p[0].pt.xn =3D 0; + pte =3D pte_of_xenaddr((uintptr_t)xen_first); + pte.pt.table =3D 1; + pte.pt.xn =3D 0; + xen_pgtable[zeroeth_table_offset(XEN_VIRT_START)] =3D pte; + p =3D (void *) xen_first; #else p =3D (void *) cpu0_pgtable; --=20 2.32.0 From nobody Fri May 17 02:03:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 09 Mar 2022 11:21:33 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nRuNo-0002kn-PP; Wed, 09 Mar 2022 11:21:32 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1nRuNo-0004wn-Hu; Wed, 09 Mar 2022 11:21:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=NfNSrIckdE3c1nYMf9yFQfxMFGcsuGH78c6BN9VFgpI=; b=QqRZkqbbN4TKLagpHWGkx8ciZi fpZhsQ23TTWc33JIMoCrCdAyH9uK+TsoLvXfZK4sYPJJ2nhg+eQceoIh5Nc01MbA3TopF8WpEE0se Sk9dkXqp5h3foYY0GLlT0A0a+rX265+Co5wYI26N6znioRNEyPn/3DBs5HHbuTbWpEw0=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: marco.solieri@minervasys.tech, lucmiccio@gmail.com, Julien GralL , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH early-RFC 3/5] xen/arm: mm: Introduce helpers to prepare/enable/disable the identity mapping Date: Wed, 9 Mar 2022 11:20:46 +0000 Message-Id: <20220309112048.17377-4-julien@xen.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220309112048.17377-1-julien@xen.org> References: <20220309112048.17377-1-julien@xen.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1646825813176100001 Content-Type: text/plain; charset="utf-8" From: Julien GralL In follow-up patches we will need to have part of Xen identity mapped in order to safely switch the TTBR. On some platform, the identity mapping may have to start at 0. If we always keep the identity region mapped, NULL pointer ference would lead to access to valid mapping. It would be possible to relocate Xen to avoid clashing with address 0. However the identity mapping is only meant to be used in very limited places. Therefore it would be better to keep the identity region invalid for most of the time. Two new helpers are introduced: - prepare_identity_mapping() will setup the page-tables so it is easy to create the mapping afterwards. - update_identity_mapping() will create/remove the identity mapping Signed-off-by: Julien Grall --- xen/arch/arm/include/asm/mm.h | 2 + xen/arch/arm/mm.c | 73 +++++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 045a8ba4bb63..76973ea9a0ff 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -177,6 +177,8 @@ extern unsigned long total_pages; =20 /* Boot-time pagetable setup */ extern void setup_pagetables(unsigned long boot_phys_offset); +/* Enable/disable the identity mapping */ +extern void update_identity_mapping(bool enable); /* Map FDT in boot pagetable */ extern void *early_fdt_map(paddr_t fdt_paddr); /* Remove early mappings */ diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 75ed9a3ce249..5c4dece16f7f 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -138,6 +138,12 @@ static DEFINE_PAGE_TABLE(cpu0_pgtable); static DEFINE_PAGE_TABLES(cpu0_dommap, DOMHEAP_SECOND_PAGES); #endif =20 +#ifdef CONFIG_ARM_64 +static DEFINE_PAGE_TABLE(xen_first_id); +static DEFINE_PAGE_TABLE(xen_second_id); +static DEFINE_PAGE_TABLE(xen_third_id); +#endif + /* Common pagetable leaves */ /* Second level page tables. * @@ -573,6 +579,70 @@ void __init remove_early_mappings(void) BUG_ON(rc); } =20 +/* + * The identity mapping may start at physical address 0. So don't want + * to keep it mapped longer than necessary. + * + * When this is called, we are still using the boot_pgtable. + * + * XXX: Handle Arm32 properly. + */ +static void prepare_identity_mapping(void) +{ + paddr_t id_addr =3D virt_to_maddr(_start); + lpae_t pte; + DECLARE_OFFSETS(id_offsets, id_addr); + + printk("id_addr 0x%lx\n", id_addr); +#ifdef CONFIG_ARM_64 + if ( id_offsets[0] !=3D 0 ) + panic("Cannot handled ID mapping above 512GB\n"); +#endif + + /* Link first ID table */ + pte =3D pte_of_xenaddr((vaddr_t)xen_first_id); + pte.pt.table =3D 1; + pte.pt.xn =3D 0; + + write_pte(&boot_pgtable[id_offsets[0]], pte); + + /* Link second ID table */ + pte =3D pte_of_xenaddr((vaddr_t)xen_second_id); + pte.pt.table =3D 1; + pte.pt.xn =3D 0; + + write_pte(&xen_first_id[id_offsets[1]], pte); + + /* Link third ID table */ + pte =3D pte_of_xenaddr((vaddr_t)xen_third_id); + pte.pt.table =3D 1; + pte.pt.xn =3D 0; + + write_pte(&xen_second_id[id_offsets[2]], pte); + + /* The mapping in the third table will be created at a later stage */ + + /* + * Link the identity mapping in the runtime Xen page tables. No need to + * use write_pte here as they are not live yet. + */ + xen_pgtable[id_offsets[0]] =3D boot_pgtable[id_offsets[0]]; +} + +void update_identity_mapping(bool enable) +{ + paddr_t id_addr =3D virt_to_maddr(_start); + int rc; + + if ( enable ) + rc =3D map_pages_to_xen(id_addr, maddr_to_mfn(id_addr), 1, + PAGE_HYPERVISOR_RX); + else + rc =3D destroy_xen_mappings(id_addr, id_addr + PAGE_SIZE); + + BUG_ON(rc); +} + /* * After boot, Xen page-tables should not contain mapping that are both * Writable and eXecutables. @@ -609,6 +679,9 @@ void __init setup_pagetables(unsigned long boot_phys_of= fset) =20 phys_offset =3D boot_phys_offset; =20 + /* XXX: Find a better place to call it */ + prepare_identity_mapping(); + #ifdef CONFIG_ARM_64 pte =3D pte_of_xenaddr((uintptr_t)xen_first); pte.pt.table =3D 1; --=20 2.32.0 From nobody Fri May 17 02:03:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Wed, 09 Mar 2022 11:21:34 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nRuNp-0002l7-VM; Wed, 09 Mar 2022 11:21:33 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1nRuNp-0004wn-NY; Wed, 09 Mar 2022 11:21:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=XzfP7FQZiQKfC2eU/eNRTo46unTVwCIHpPRL2SVGKE0=; b=JCOWKXWOV6mJbdieoB0sminCOz D98HJX2ducw2mQe2Gz3a9NCcf8wz8YqEZmYTn/8cifvZ2bf43XHTMLElNMoSvSbAMOKTztL4msko8 0OM2xKiuei5kMRDPctFD+70qdA1KLU+vLbrCFFukPqTL8CgtA/0W/hdYVBw1FbZ6MTJU=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: marco.solieri@minervasys.tech, lucmiccio@gmail.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH early-RFC 4/5] xen/arm: mm: Rework switch_ttbr() Date: Wed, 9 Mar 2022 11:20:47 +0000 Message-Id: <20220309112048.17377-5-julien@xen.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220309112048.17377-1-julien@xen.org> References: <20220309112048.17377-1-julien@xen.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1646825813177100002 Content-Type: text/plain; charset="utf-8" From: Julien Grall At the moment, switch_ttbr() is switching the TTBR whilst the MMU is still on. Switching TTBR is like replacing existing mappings with new ones. So we need to follow the break-before-make sequence. In this case, it means the MMU needs to be switched off while the TTBR is updated. In order to disable the MMU, we need to first jump to an identity mapping. Rename switch_ttbr() to switch_ttbr_id() and create an helper on top to temporary map the identity mapping and call switch_ttbr() via the identity address. switch_ttbr_id() is now reworked to temporarily turn off the MMU before updating the TTBR. We also need to make sure the helper switch_ttbr() is part of the identity mapping. So move _end_boot past it. Take the opportunity to instruction cache flush as the operation is only necessary when the memory is updated. Signed-off-by: Julien Grall --- TODO: * Rename _end_boot to _end_id_mapping or similar * Check the memory barriers * I suspect the instruction cache flush will be necessary for cache coloring. --- xen/arch/arm/arm64/head.S | 31 ++++++++++++++++++++----------- xen/arch/arm/mm.c | 14 +++++++++++++- 2 files changed, 33 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 878649280d73..c5cc72b8fe6f 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -803,36 +803,45 @@ fail: PRINT("- Boot failed -\r\n") b 1b ENDPROC(fail) =20 -GLOBAL(_end_boot) - /* * Switch TTBR * * x0 ttbr * - * TODO: This code does not comply with break-before-make. + * XXX: Check the barriers */ -ENTRY(switch_ttbr) +ENTRY(switch_ttbr_id) dsb sy /* Ensure the flushes happen before * continuing */ isb /* Ensure synchronization with previo= us * changes to text */ + + /* Turn off MMU */ + mrs x1, SCTLR_EL2 + bic x1, x1, #SCTLR_Axx_ELx_M + msr SCTLR_EL2, x1 + dsb sy + isb + tlbi alle2 /* Flush hypervisor TLB */ - ic iallu /* Flush I-cache */ dsb sy /* Ensure completion of TLB flush */ isb =20 - msr TTBR0_EL2, x0 + msr TTBR0_EL2, x0 + + mrs x1, SCTLR_EL2 + orr x1, x1, #SCTLR_Axx_ELx_M /* Enable MMU */ + msr SCTLR_EL2, x1 =20 isb /* Ensure synchronization with previo= us * changes to text */ - tlbi alle2 /* Flush hypervisor TLB */ - ic iallu /* Flush I-cache */ - dsb sy /* Ensure completion of TLB flush */ - isb + /* Turn on the MMU */ + =20 ret -ENDPROC(switch_ttbr) +ENDPROC(switch_ttbr_id) + +GLOBAL(_end_boot) =20 #ifdef CONFIG_EARLY_PRINTK /* diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 5c4dece16f7f..a53760af7af0 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -660,7 +660,19 @@ static void xen_pt_enforce_wnx(void) flush_xen_tlb_local(); } =20 -extern void switch_ttbr(uint64_t ttbr); +extern void switch_ttbr_id(uint64_t ttbr); + +typedef void (switch_ttbr_fn)(uint64_t ttbr); + +static void switch_ttbr(uint64_t ttbr) +{ + vaddr_t id_addr =3D virt_to_maddr(switch_ttbr_id); + switch_ttbr_fn *fn =3D (switch_ttbr_fn *)id_addr; + + update_identity_mapping(true); + fn(ttbr); + update_identity_mapping(false); +} =20 /* Clear a translation table and clean & invalidate the cache */ static void clear_table(void *table) --=20 2.32.0 From nobody Fri May 17 02:03:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org ARC-Seal: i=1; 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Wed, 09 Mar 2022 11:21:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=tjGVNBl+p1ZPAg1oGbm6UDq0DOV0mnkoPMAmBc++mKs=; b=Tk8L3eXtygKmHrlWShbwQR/9CN ZyDrKFjTNTZ1zyfZtb9WFiVFlbnGERbyaKr8D2PcVieZ3IM1d+8j6sRHreaXdmrC1AuQ0pMeF4DAr YvRfOBwqudW/lJTnvnf+C7vTQO689XUu1GgHIkCALBSk6U9yqJJaFB52XkiADamDmIs8=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: marco.solieri@minervasys.tech, lucmiccio@gmail.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH early-RFC 5/5] xen/arm: smpboot: Directly switch to the runtime page-tables Date: Wed, 9 Mar 2022 11:20:48 +0000 Message-Id: <20220309112048.17377-6-julien@xen.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220309112048.17377-1-julien@xen.org> References: <20220309112048.17377-1-julien@xen.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @xen.org) X-ZM-MESSAGEID: 1646824913700100001 Content-Type: text/plain; charset="utf-8" From: Julien Grall Switching TTBR while the MMU is on is not safe. Now that the identity mapping will not clash with the rest of the memory layout, we can avoid creating temporary page-tables every time a CPU is brought up. Signed-off-by: Julien Grall --- xen/arch/arm/arm64/head.S | 29 +++++++++-------------------- xen/arch/arm/mm.c | 19 ------------------- xen/arch/arm/smpboot.c | 3 +++ 3 files changed, 12 insertions(+), 39 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index c5cc72b8fe6f..f0ac5a3295cc 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -309,6 +309,7 @@ real_start_efi: bl check_cpu_mode bl cpu_init bl create_page_tables + load_paddr x0, boot_pgtable bl enable_mmu =20 /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ @@ -368,29 +369,14 @@ GLOBAL(init_secondary) #endif bl check_cpu_mode bl cpu_init - bl create_page_tables + load_paddr x0, init_ttbr + ldr x0, [x0] bl enable_mmu =20 /* We are still in the 1:1 mapping. Jump to the runtime Virtual Ad= dress. */ ldr x0, =3Dsecondary_switched br x0 secondary_switched: - /* - * Non-boot CPUs need to move on to the proper pagetables, which w= ere - * setup in init_secondary_pagetables. - * - * XXX: This is not compliant with the Arm Arm. - */ - ldr x4, =3Dinit_ttbr /* VA of TTBR0_EL2 stashed by CPU 0= */ - ldr x4, [x4] /* Actual value */ - dsb sy - msr TTBR0_EL2, x4 - dsb sy - isb - tlbi alle2 - dsb sy /* Ensure completion of TLB flush */ - isb - #ifdef CONFIG_EARLY_PRINTK /* Use a virtual address to access the UART. */ ldr x23, =3DEARLY_UART_VIRTUAL_ADDRESS @@ -661,9 +647,13 @@ ENDPROC(create_page_tables) * mapping. In other word, the caller is responsible to switch to the runt= ime * mapping. * - * Clobbers x0 - x3 + * Inputs: + * x0 : Physical address of the page tables. + * + * Clobbers x0 - x4 */ enable_mmu: + mov x4, x0 PRINT("- Turning on paging -\r\n") =20 /* @@ -674,8 +664,7 @@ enable_mmu: dsb nsh =20 /* Write Xen's PT's paddr into TTBR0_EL2 */ - load_paddr x0, boot_pgtable - msr TTBR0_EL2, x0 + msr TTBR0_EL2, x4 isb =20 mrs x0, SCTLR_EL2 diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index a53760af7af0..be808073844a 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -771,26 +771,9 @@ void __init setup_pagetables(unsigned long boot_phys_o= ffset) #endif } =20 -static void clear_boot_pagetables(void) -{ - /* - * Clear the copy of the boot pagetables. Each secondary CPU - * rebuilds these itself (see head.S). - */ - clear_table(boot_pgtable); -#ifdef CONFIG_ARM_64 - clear_table(boot_first); - clear_table(boot_first_id); -#endif - clear_table(boot_second); - clear_table(boot_third); -} - #ifdef CONFIG_ARM_64 int init_secondary_pagetables(int cpu) { - clear_boot_pagetables(); - /* Set init_ttbr for this CPU coming up. All CPus share a single setof * pagetables, but rewrite it each time for consistency with 32 bit. */ init_ttbr =3D (uintptr_t) xen_pgtable + phys_offset; @@ -833,8 +816,6 @@ int init_secondary_pagetables(int cpu) per_cpu(xen_pgtable, cpu) =3D first; per_cpu(xen_dommap, cpu) =3D domheap; =20 - clear_boot_pagetables(); - /* Set init_ttbr for this CPU coming up */ init_ttbr =3D __pa(first); clean_dcache(init_ttbr); diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 7bfd0a73a7d2..72931d0cef93 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -457,12 +457,14 @@ int __cpu_up(unsigned int cpu) smp_up_cpu =3D cpu_logical_map(cpu); clean_dcache(smp_up_cpu); =20 + update_identity_mapping(true); rc =3D arch_cpu_up(cpu); =20 console_end_sync(); =20 if ( rc < 0 ) { + update_identity_mapping(false); printk("Failed to bring up CPU%d\n", cpu); return rc; } @@ -493,6 +495,7 @@ int __cpu_up(unsigned int cpu) init_data.cpuid =3D ~0; smp_up_cpu =3D MPIDR_INVALID; clean_dcache(smp_up_cpu); + update_identity_mapping(false); =20 if ( !cpu_online(cpu) ) { --=20 2.32.0