From nobody Mon Feb 9 20:32:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1646417905396422.4011304327295; Fri, 4 Mar 2022 10:18:25 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.284482.484019 (Exim 4.92) (envelope-from ) id 1nQCVC-0000fh-12; Fri, 04 Mar 2022 18:18:06 +0000 Received: by outflank-mailman (output) from mailman id 284482.484019; Fri, 04 Mar 2022 18:18:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nQCV9-0000Vv-Gz; Fri, 04 Mar 2022 18:18:03 +0000 Received: by outflank-mailman (input) for mailman id 284482; Fri, 04 Mar 2022 17:56:15 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1nQC2F-0005R5-Lt for xen-devel@lists.xenproject.org; Fri, 04 Mar 2022 17:48:11 +0000 Received: from radon.xt3.it (radon.xt3.it [2a01:4f8:190:4055::2]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 41dd6d85-9be3-11ec-8539-5f4723681683; Fri, 04 Mar 2022 18:48:10 +0100 (CET) Received: from nb2assolieri.mat.unimo.it ([155.185.4.56] helo=localhost) by radon.xt3.it with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1nQC2E-00008L-6Q; Fri, 04 Mar 2022 18:48:10 +0100 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 41dd6d85-9be3-11ec-8539-5f4723681683 From: Marco Solieri To: xen-devel@lists.xenproject.org Cc: Marco Solieri , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Marco Solieri , Andrea Bastoni , Luca Miccio , Luca Miccio <206497@studenti.unimore.it> Subject: [PATCH 22/36] xen/arch: init cache coloring conf for Xen Date: Fri, 4 Mar 2022 18:46:47 +0100 Message-Id: <20220304174701.1453977-23-marco.solieri@minervasys.tech> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220304174701.1453977-1-marco.solieri@minervasys.tech> References: <20220304174701.1453977-1-marco.solieri@minervasys.tech> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1646417907178100001 Content-Type: text/plain; charset="utf-8" From: Luca Miccio Add initialization for Xen coloring data. By default, use the lowest color index available. Benchmarking the VM interrupt response time provides an estimation of LLC usage by Xen's most latency-critical runtime task. Results on Arm Cortex-A53 on Xilinx Zynq UltraScale+ XCZU9EG show that one color, which reserves 64 KiB of L2, is enough to attain best responsiveness. More colors are instead very likely to be needed on processors whose L1 cache is physically-indexed and physically-tagged, such as Cortex-A57. In such cases, coloring applies to L1 also, and there typically are two distinct L1-colors. Therefore, reserving only one color for Xen would senselessly partitions a cache memory that is already private, i.e. underutilize it. The default amount of Xen colors is thus set to one. Signed-off-by: Luca Miccio <206497@studenti.unimore.it> Signed-off-by: Marco Solieri --- xen/arch/arm/coloring.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/coloring.c b/xen/arch/arm/coloring.c index d1ac193a80..761414fcd7 100644 --- a/xen/arch/arm/coloring.c +++ b/xen/arch/arm/coloring.c @@ -30,10 +30,18 @@ #include #include =20 +/* By default Xen uses the lowestmost color */ +#define XEN_COLOR_DEFAULT_MASK 0x0001 +#define XEN_COLOR_DEFAULT_NUM 1 +/* Current maximum useful colors */ +#define MAX_XEN_COLOR 128 + /* Number of color(s) assigned to Xen */ static uint32_t xen_col_num; /* Coloring configuration of Xen as bitmask */ static uint32_t xen_col_mask[MAX_COLORS_CELLS]; +/* Xen colors IDs */ +static uint32_t xen_col_list[MAX_XEN_COLOR]; =20 /* Number of color(s) assigned to Dom0 */ static uint32_t dom0_col_num; @@ -216,7 +224,7 @@ uint32_t get_max_colors(void) =20 bool __init coloring_init(void) { - int i; + int i, rc; =20 printk(XENLOG_INFO "Initialize XEN coloring: \n"); /* @@ -266,6 +274,27 @@ bool __init coloring_init(void) printk(XENLOG_INFO "Color bits in address: 0x%"PRIx64"\n", addr_col_ma= sk); printk(XENLOG_INFO "Max number of colors: %u\n", max_col_num); =20 + if ( !xen_col_num ) + { + xen_col_mask[0] =3D XEN_COLOR_DEFAULT_MASK; + xen_col_num =3D XEN_COLOR_DEFAULT_NUM; + printk(XENLOG_WARNING "Xen color configuration not found. Using de= fault\n"); + } + + printk(XENLOG_INFO "Xen color configuration: 0x%"PRIx32"%"PRIx32"%"PRI= x32"%"PRIx32"\n", + xen_col_mask[3], xen_col_mask[2], xen_col_mask[1], xen_col_mas= k[0]); + rc =3D copy_mask_to_list(xen_col_mask, xen_col_list, xen_col_num); + + if ( rc ) + return false; + + for ( i =3D 0; i < xen_col_num; i++ ) + if ( xen_col_list[i] > (max_col_num - 1) ) + { + printk(XENLOG_ERR "ERROR: max. color value not supported\n"); + return false; + } + return true; } =20 --=20 2.30.2