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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2022 12:40:32.1618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44db705b-959e-4b2f-582d-08d9fb80acde X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0008.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6740 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1646138466534100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the abort was caused due to access to stage1 translation table, Xen will assume that the stage1 translation table is in the non MMIO region. It will try to resolve the translation fault. If it succeeds, it will return to the guest to retry the instruction. If not, then it means that the table is in MMIO region which is not expected by Xen. Thus, Xen will forward the abort to the guest. Signed-off-by: Ayan Kumar Halder --- Changelog :- v1..v8 - NA v9 - 1. Extracted this change from "[XEN v8 2/2] xen/arm64: io: Support instructions (for which ISS is not..." into a separate patch of its own. The reason being this is an existing bug in the codebase. xen/arch/arm/io.c | 11 +++++++++++ xen/arch/arm/traps.c | 12 +++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index bea69ffb08..ebcb8ed548 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -128,6 +128,17 @@ void try_decode_instruction(const struct cpu_user_regs= *regs, return; } =20 + /* + * At this point, we know that the stage1 translation table is in the = MMIO + * region. This is not expected by Xen and thus it forwards the abort = to the + * guest. + */ + if ( info->dabt.s1ptw ) + { + info->dabt_instr.state =3D INSTR_ERROR; + return; + } + /* * Armv8 processor does not provide a valid syndrome for decoding some * instructions. So in order to process these instructions, Xen must diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 120c971b0f..e491ca15d7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1923,6 +1923,7 @@ static void do_trap_stage2_abort_guest(struct cpu_use= r_regs *regs, bool is_data =3D (hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); mmio_info_t info; enum io_state state; + bool check_mmio_region =3D true; =20 /* * If this bit has been set, it means that this stage-2 abort is caused @@ -1987,7 +1988,16 @@ static void do_trap_stage2_abort_guest(struct cpu_us= er_regs *regs, */ if ( !is_data || !info.dabt.valid ) { - if ( check_p2m(is_data, gpa) ) + /* + * If the translation fault was caused due to access to stage 1 + * translation table, then we try to set the translation table= entry + * for page1 translation table (assuming that it is in the non= mmio + * region). + */ + if ( xabt.s1ptw ) + check_mmio_region =3D false; + + if ( check_p2m((is_data && check_mmio_region), gpa) ) return; =20 /* --=20 2.17.1