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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch01.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v9 1/4] xen/arm64: Decode ldr/str post increment operations Date: Tue, 1 Mar 2022 12:40:19 +0000 Message-ID: <20220301124022.10168-2-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220301124022.10168-1-ayankuma@xilinx.com> References: <20220301124022.10168-1-ayankuma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6defbd93-9392-4130-6e1c-08d9fb80ab89 X-MS-TrafficTypeDiagnostic: MN2PR02MB5789:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uAsw3kCEpuF9xuCyCTcGTWwwTIBaae0a3G805rvbUBXsGLqDZ5BAJx2XMQrYRkt+fJxsRJ2ZEA4xv7T8pMm9+RTKwp8lqFpnLP/uxRBMldPgZ1jF3NJGa655+A5WW17Or0lJn9rCP8Sg25nyfITxioy8h0JY4sWPIuzsEfajLAMO9qNENrt6SltaCVqffBnY32Wah5nPICHZSBEBcSOKtQsokWHHxmQxZhWmDfV0KtmmFWi+hms3a817A0KjU9sFj8+eaxk11zt0ct6Jg3elSZtp9CjXRHqv0rf7X8enfzUrETGIFBx0SfH28US8FzX63EM8WN4028SZPyeBEURde3VsyOiDaLAbY0ViEN8QroWyLF4uzD6LrH3xa66qLiYkArzGOta88tlR2TBku3j+J9Rdv3s42sKZnmwBAFQHvHksI29LBXEEwZ3P57WIo203Wo5vmkDc+4bN37Daojr2quD4MeDI4vM3VoXm8Oat1m1kXm7mSUz4oS+aUgw8yunApe5MwNm1sP+3lrnxL+O848djA3DExiP2PES9hiW+tUOabNEcnYuJzpzC4p+wWNqGFdVt/pryEnINpRA/Hc70Rm/uU7z3H9tzWK3UCE78BVtmMNaPHHaa2bQp9UcMyYylsWC3n/K5mEJ6I5rxR74eN2Pw1R2Ra2YVfjV4kZ6U60ZGjOR8IyLpGgfTCZNchnbj/1qTxgMqt8sSmYy0qf5U3Q== X-Forefront-Antispam-Report: CIP:149.199.80.198;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:xir-pvapexch01.xlnx.xilinx.com;PTR:unknown-80-198.xilinx.com;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(26005)(54906003)(40460700003)(6916009)(6666004)(186003)(36756003)(356005)(7416002)(82310400004)(107886003)(2616005)(5660300002)(1076003)(316002)(508600001)(47076005)(7636003)(7696005)(83380400001)(2906002)(70586007)(8676002)(70206006)(336012)(426003)(8936002)(4326008)(36860700001)(9786002)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2022 12:40:29.9276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6defbd93-9392-4130-6e1c-08d9fb80ab89 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0008.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB5789 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1646138464882100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment, Xen does not decode any of the arm64 instructions. This means that when hsr_dabt.isv =3D=3D 0, Xen cannot handle those instructions. This will lead to Xen to abort the guests (from which those instructions originate). With this patch, Xen is able to decode ldr/str post indexing instructions. These are a subset of instructions for which hsr_dabt.isv =3D=3D 0. The following instructions are now supported by Xen :- 1. ldr x2, [x1], #8 2. ldr w2, [x1], #-4 3. ldr x2, [x1], #-8 4. ldr w2, [x1], #4 5. ldrh w2, [x1], #2 6. ldrb w2, [x1], #1 7. str x2, [x1], #8 8. str w2, [x1], #-4 9. strh w2, [x1], #2 10. strb w2, [x1], #1 In the subsequent patch, decode_arm64() will get invoked when hsr_dabt.isv =3D=3D 0. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changelog :- v2..v5 - Mentioned in the cover letter. v6 - 1. Fixed the code style issues as mentioned in v5. v7 - No change. v8 - 1. Removed some un-necessary header files inclusion. 2. Some style changes pointed out in v7. v9 - 1. Rebased on top of the master. 2. Renamed psr_mode_is_32bit to regs_mode_is_32bit. xen/arch/arm/decode.c | 79 ++++++++++++++++++++++++++++++++- xen/arch/arm/decode.h | 48 +++++++++++++++++--- xen/arch/arm/include/asm/mmio.h | 4 ++ xen/arch/arm/io.c | 2 +- 4 files changed, 124 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 792c2e92a7..3add87e83a 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -84,6 +84,78 @@ bad_thumb2: return 1; } =20 +static int decode_arm64(register_t pc, mmio_info_t *info) +{ + union instr opcode =3D {0}; + struct hsr_dabt *dabt =3D &info->dabt; + struct instr_details *dabt_instr =3D &info->dabt_instr; + + if ( raw_copy_from_guest(&opcode.value, (void * __user)pc, sizeof (opc= ode)) ) + { + gprintk(XENLOG_ERR, "Could not copy the instruction from PC\n"); + return 1; + } + + /* + * Refer Arm v8 ARM DDI 0487G.b, Page - C6-1107 + * "Shared decode for all encodings" (under ldr immediate) + * If n =3D=3D t && n !=3D 31, then the return value is implementation= defined + * (can be WBSUPPRESS, UNKNOWN, UNDEFINED or NOP). Thus, we do not sup= port + * this. This holds true for ldrb/ldrh immediate as well. + * + * Also refer, Page - C6-1384, the above described behaviour is same f= or + * str immediate. This holds true for strb/strh immediate as well + */ + if ( (opcode.ldr_str.rn =3D=3D opcode.ldr_str.rt) && (opcode.ldr_str.r= n !=3D 31) ) + { + gprintk(XENLOG_ERR, "Rn should not be equal to Rt except for r31\n= "); + goto bad_loadstore; + } + + /* First, let's check for the fixed values */ + if ( (opcode.value & POST_INDEX_FIXED_MASK) !=3D POST_INDEX_FIXED_VALU= E ) + { + gprintk(XENLOG_ERR, + "Decoding instruction 0x%x is not supported\n", opcode.val= ue); + goto bad_loadstore; + } + + if ( opcode.ldr_str.v !=3D 0 ) + { + gprintk(XENLOG_ERR, + "ldr/str post indexing for vector types are not supported\= n"); + goto bad_loadstore; + } + + /* Check for STR (immediate) */ + if ( opcode.ldr_str.opc =3D=3D 0 ) + dabt->write =3D 1; + /* Check for LDR (immediate) */ + else if ( opcode.ldr_str.opc =3D=3D 1 ) + dabt->write =3D 0; + else + { + gprintk(XENLOG_ERR, + "Decoding ldr/str post indexing is not supported for this = variant\n"); + goto bad_loadstore; + } + + gprintk(XENLOG_INFO, + "opcode->ldr_str.rt =3D 0x%x, opcode->ldr_str.size =3D 0x%x, o= pcode->ldr_str.imm9 =3D %d\n", + opcode.ldr_str.rt, opcode.ldr_str.size, opcode.ldr_str.imm9); + + update_dabt(dabt, opcode.ldr_str.rt, opcode.ldr_str.size, false); + + dabt_instr->rn =3D opcode.ldr_str.rn; + dabt_instr->imm9 =3D opcode.ldr_str.imm9; + + return 0; + + bad_loadstore: + gprintk(XENLOG_ERR, "unhandled Arm instruction 0x%x\n", opcode.value); + return 1; +} + static int decode_thumb(register_t pc, struct hsr_dabt *dabt) { uint16_t instr; @@ -150,10 +222,13 @@ bad_thumb: return 1; } =20 -int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt) +int decode_instruction(const struct cpu_user_regs *regs, mmio_info_t *info) { if ( is_32bit_domain(current->domain) && regs->cpsr & PSR_THUMB ) - return decode_thumb(regs->pc, dabt); + return decode_thumb(regs->pc, &info->dabt); + + if ( !regs_mode_is_32bit(regs) ) + return decode_arm64(regs->pc, info); =20 /* TODO: Handle ARM instruction */ gprintk(XENLOG_ERR, "unhandled ARM instruction\n"); diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index 4613763bdb..13db8ac968 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -23,19 +23,55 @@ #include #include =20 -/** +/* + * Refer to the ARMv8 ARM (DDI 0487G.b), Section C4.1.4 Loads and Stores + * Page 318 specifies the following bit pattern for + * "load/store register (immediate post-indexed)". + * + * 31 30 29 27 26 25 23 21 20 11 9 4 0 + * ___________________________________________________________________ + * |size|1 1 1 |V |0 0 |opc |0 | imm9 |0 1 | Rn | Rt | + * |____|______|__|____|____|__|_______________|____|_________|_______| + */ +union instr { + uint32_t value; + struct { + unsigned int rt:5; /* Rt register */ + unsigned int rn:5; /* Rn register */ + unsigned int fixed1:2; /* value =3D=3D 01b */ + signed int imm9:9; /* imm9 */ + unsigned int fixed2:1; /* value =3D=3D 0b */ + unsigned int opc:2; /* opc */ + unsigned int fixed3:2; /* value =3D=3D 00b */ + unsigned int v:1; /* vector */ + unsigned int fixed4:3; /* value =3D=3D 111b */ + unsigned int size:2; /* size */ + } ldr_str; +}; + +#define POST_INDEX_FIXED_MASK 0x3B200C00 +#define POST_INDEX_FIXED_VALUE 0x38000400 + +/* * Decode an instruction from pc - * /!\ This function is not intended to fully decode an instruction. It - * considers that the instruction is valid. + * /!\ This function is intended to decode an instruction. It considers th= at the + * instruction is valid. * - * This function will get: - * - The transfer register + * In case of thumb mode, this function will get: + * - The transfer register (ie Rt) * - Sign bit * - Size + * + * In case of arm64 mode, this function will get: + * - The transfer register (ie Rt) + * - The source register (ie Rn) + * - Size + * - Immediate offset + * - Read or write */ =20 int decode_instruction(const struct cpu_user_regs *regs, - struct hsr_dabt *dabt); + mmio_info_t *info); =20 #endif /* __ARCH_ARM_DECODE_H_ */ =20 diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmi= o.h index 7ab873cb8f..3354d9c635 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -29,6 +29,10 @@ typedef struct { struct hsr_dabt dabt; + struct instr_details { + unsigned long rn:5; + signed int imm9:9; + } dabt_instr; paddr_t gpa; } mmio_info_t; =20 diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 1a066f9ae5..fad103bdbd 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -141,7 +141,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, { int rc; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch01.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v9 2/4] xen/arm64: io: Support instructions (for which ISS is not valid) on emulated MMIO region using MMIO/ioreq handler Date: Tue, 1 Mar 2022 12:40:20 +0000 Message-ID: <20220301124022.10168-3-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220301124022.10168-1-ayankuma@xilinx.com> References: <20220301124022.10168-1-ayankuma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5aff75a4-4b86-4aa3-fdd7-08d9fb80ac5f X-MS-TrafficTypeDiagnostic: CO6PR02MB8740:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2022 12:40:31.2400 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5aff75a4-4b86-4aa3-fdd7-08d9fb80ac5f X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0008.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR02MB8740 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1646139366856100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When an instruction is trapped in Xen due to translation fault, Xen checks if the ISS is invalid (for data abort) or it is an instruction abort. If so, Xen tries to resolve the translation fault using p2m page tables. In case of data abort, Xen will try to map the mmio region to the guest (ie tries to emulate the mmio region). If the ISS is not valid and it is a data abort, then Xen tries to decode the instruction. In case of ioreq, Xen saves the decoding state, rn and imm9 to vcpu_io. Whenever the vcpu handles the ioreq successfully, it will read the decoding state to determine if the instruction decoded was a ldr/str post indexing (ie INSTR_LDR_STR_POSTINDEXING). If so, it uses these details to post increment rn. In case of mmio handler, if the mmio operation was successful, then Xen retrives the decoding state, rn and imm9. For state =3D=3D INSTR_LDR_STR_POSTINDEXING, Xen will update rn. If there is an error encountered while decoding/executing the instruction, Xen will forward the abort to the guest. Signed-off-by: Ayan Kumar Halder --- Changelog :- v2..v5 - Mentioned in the cover letter. v6 - 1. Mantained the decoding state of the instruction. This is used by the caller to either abort the guest or retry or ignore or perform read/write on the mmio region. 2. try_decode() invokes decoding for both aarch64 and thumb state. (Previou= sly it used to invoke decoding only for aarch64 state). Thus, it handles all the checking of the registers before invoking any decoding of instruction. try_decode_instruction_invalid_iss() has thus been removed. 3. Introduced a new field('enum instr_decode_state state') inside 'struct instr_details'. This holds the decoding state of the instruction. This is later read by the post_increment_register() to determine if rn need= s to be incremented. Also, this is read by the callers of try_decode_instruction= () to determine if the instruction was valid or ignored or to be retried or error or decoded successfully. 4. Also stored 'instr_details' inside 'struct ioreq'. This enables arch_ioreq_complete_mmio() to invoke post_increment_register() without deco= ding the instruction again. 5. Check hsr.dabt.valid in do_trap_stage2_abort_guest(). If it is not valid, then decode the instruction. This ensures that try_handle_mmio() is invoked= only when the instruction is either valid or decoded successfully. 6. Inside do_trap_stage2_abort_guest(), if hsr.dabt.valid is not set, then resolve the translation fault before trying to decode the instruction. If translation fault is resolved, then return to the guest to execute the inst= ruction again. v7 - 1. Moved the decoding instruction details ie instr_details from 'struc= t ioreq' to 'struct vcpu_io'. 2. The instruction is decoded only when we get a data abort. 3. Replaced ASSERT_UNREACHABLE() with domain_crash(). The reason being asse= rts can be disabled in some builds. In this scenario when the guest's cpsr is i= n an erroneous state, Xen should crash the guest. 4. Introduced check_p2m() which invokes p2m_resolve_translation_fault() and try_map_mmio() to resolve translation fault by configuring the page tables.= This gets invoked first if ISS is invalid and it is an instruction abort. If it = is a data abort and hsr.dabt.s1ptw is set or try_handle_mmio() returns IO_UNHA= NDLED, then check_p2m() gets invoked again. v8 - 1. Removed the handling of data abort when info->dabt.cache is set. Th= is will be implemented in a subsequent patch. (Not as part of this series) 2. When the data abort is due to access to stage 1 translation tables, Xen = will try to fix the mapping of the page table for the corresponding address. If = this returns an error, Xen will abort the guest. Else, it will ask the guest to = retry the instruction. 3. Changed v->io.info.dabt_instr from pointer to variable. The reason being= that arch_ioreq_complete_mmio() is called from leave_hypervisor_to_guest(). That is after do_trap_stage2_abort_guest() has been invoked. So the origin= al variable will be no longer valid. 4. Some other style issues pointed out in v7. v9 - 1. Ensure that "Erratum 766422" is handled only when ISS is valid. 2. Whenever Xen receives and instruction abort or data abort (with invalid = ISS), Xen should first try to resolve the p2m translation fault or see if it it n= eeds to map a MMIO region. If it succeeds, it should return to the guest to retr= y the instruction. 3. Removed handling of "dabt.s1ptw =3D=3D 1" aborts. This is addressed in p= atch3 as it is an existing bug in codebase. 4. Various style issues pointed by Julien in v8. xen/arch/arm/arm32/traps.c | 11 ++++ xen/arch/arm/arm64/traps.c | 47 ++++++++++++++++ xen/arch/arm/decode.c | 1 + xen/arch/arm/include/asm/domain.h | 4 ++ xen/arch/arm/include/asm/mmio.h | 17 +++++- xen/arch/arm/include/asm/traps.h | 2 + xen/arch/arm/io.c | 90 +++++++++++++++++++------------ xen/arch/arm/ioreq.c | 7 ++- xen/arch/arm/traps.c | 77 ++++++++++++++++++++------ xen/arch/x86/include/asm/ioreq.h | 3 ++ xen/include/xen/sched.h | 2 + 11 files changed, 207 insertions(+), 54 deletions(-) diff --git a/xen/arch/arm/arm32/traps.c b/xen/arch/arm/arm32/traps.c index 9c9790a6d1..159e3cef8b 100644 --- a/xen/arch/arm/arm32/traps.c +++ b/xen/arch/arm/arm32/traps.c @@ -18,9 +18,11 @@ =20 #include #include +#include =20 #include =20 +#include #include #include =20 @@ -82,6 +84,15 @@ void do_trap_data_abort(struct cpu_user_regs *regs) do_unexpected_trap("Data Abort", regs); } =20 +void post_increment_register(const struct instr_details *instr) +{ + /* + * We have not implemented decoding of post indexing instructions for = 32 bit. + * Thus, this should be unreachable. + */ + domain_crash(current->domain); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c index 9113a15c7a..e18b6b2626 100644 --- a/xen/arch/arm/arm64/traps.c +++ b/xen/arch/arm/arm64/traps.c @@ -17,6 +17,7 @@ */ =20 #include +#include =20 #include #include @@ -44,6 +45,52 @@ void do_bad_mode(struct cpu_user_regs *regs, int reason) panic("bad mode\n"); } =20 +void post_increment_register(const struct instr_details *instr) +{ + struct cpu_user_regs *regs =3D guest_cpu_user_regs(); + register_t val =3D 0; + + /* Currently, we handle only ldr/str post indexing instructions */ + if ( instr->state !=3D INSTR_LDR_STR_POSTINDEXING ) + return; + + /* + * Handle when rn =3D SP + * Refer ArmV8 ARM DDI 0487G.b, Page - D1-2463 "Stack pointer register + * selection" + * t =3D SP_EL0 + * h =3D SP_ELx + * and M[3:0] (Page - C5-474 "When exception taken from AArch64 state:= ") + */ + if (instr->rn =3D=3D 31 ) + { + if ( (regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1h ) + val =3D regs->sp_el1; + else if ( ((regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1t) || + ((regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL0t) ) + val =3D regs->sp_el0; + else + { + domain_crash(current->domain); + return; + } + } + else + val =3D get_user_reg(regs, instr->rn); + + val +=3D instr->imm9; + + if ( instr->rn =3D=3D 31 ) + { + if ( (regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1h ) + regs->sp_el1 =3D val; + else + regs->sp_el0 =3D val; + } + else + set_user_reg(regs, instr->rn, val); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 3add87e83a..16ad0747bb 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -146,6 +146,7 @@ static int decode_arm64(register_t pc, mmio_info_t *inf= o) =20 update_dabt(dabt, opcode.ldr_str.rt, opcode.ldr_str.size, false); =20 + dabt_instr->state =3D INSTR_LDR_STR_POSTINDEXING; dabt_instr->rn =3D opcode.ldr_str.rn; dabt_instr->imm9 =3D opcode.ldr_str.imm9; =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index c56f6e4398..ed63c2b6f9 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -281,6 +281,10 @@ static inline void arch_vcpu_block(struct vcpu *v) {} /* vPCI is not available on Arm */ #define has_vpci(d) ({ (void)(d); false; }) =20 +struct arch_vcpu_io { + struct instr_details dabt_instr; /* when the instruction is decoded */ +}; + #endif /* __ASM_DOMAIN_H__ */ =20 /* diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmi= o.h index 3354d9c635..ef2c57a2d5 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -26,12 +26,24 @@ =20 #define MAX_IO_HANDLER 16 =20 +enum instr_decode_state +{ + INSTR_ERROR, /* Error encountered while decoding in= str */ + INSTR_VALID, /* ISS is valid, so no need to decode = */ + /* + * Instruction is decoded successfully. It is a ldr/str post indexing + * instruction. + */ + INSTR_LDR_STR_POSTINDEXING +}; + typedef struct { struct hsr_dabt dabt; struct instr_details { unsigned long rn:5; signed int imm9:9; + enum instr_decode_state state; } dabt_instr; paddr_t gpa; } mmio_info_t; @@ -69,14 +81,15 @@ struct vmmio { }; =20 enum io_state try_handle_mmio(struct cpu_user_regs *regs, - const union hsr hsr, - paddr_t gpa); + mmio_info_t *info); void register_mmio_handler(struct domain *d, const struct mmio_handler_ops *ops, paddr_t addr, paddr_t size, void *priv); int domain_io_init(struct domain *d, int max_count); void domain_io_free(struct domain *d); =20 +void try_decode_instruction(const struct cpu_user_regs *regs, + mmio_info_t *info); =20 #endif /* __ASM_ARM_MMIO_H__ */ =20 diff --git a/xen/arch/arm/include/asm/traps.h b/xen/arch/arm/include/asm/tr= aps.h index 2ed2b85c6f..95c46ad391 100644 --- a/xen/arch/arm/include/asm/traps.h +++ b/xen/arch/arm/include/asm/traps.h @@ -109,6 +109,8 @@ static inline register_t sign_extend(const struct hsr_d= abt dabt, register_t r) return r; } =20 +void post_increment_register(const struct instr_details *instr); + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index fad103bdbd..bea69ffb08 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -102,57 +102,79 @@ static const struct mmio_handler *find_mmio_handler(s= truct domain *d, return handler; } =20 +void try_decode_instruction(const struct cpu_user_regs *regs, + mmio_info_t *info) +{ + int rc; + + if ( info->dabt.valid ) + { + info->dabt_instr.state =3D INSTR_VALID; + + /* + * Erratum 766422: Thumb store translation fault to Hypervisor may + * not have correct HSR Rt value. + */ + if ( check_workaround_766422() && (regs->cpsr & PSR_THUMB) && + info->dabt.write ) + { + rc =3D decode_instruction(regs, info); + if ( rc ) + { + gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); + info->dabt_instr.state =3D INSTR_ERROR; + } + } + return; + } + + /* + * Armv8 processor does not provide a valid syndrome for decoding some + * instructions. So in order to process these instructions, Xen must + * decode them. + */ + rc =3D decode_instruction(regs, info); + if ( rc ) + { + gprintk(XENLOG_ERR, "Unable to decode instruction\n"); + info->dabt_instr.state =3D INSTR_ERROR; + } +} + enum io_state try_handle_mmio(struct cpu_user_regs *regs, - const union hsr hsr, - paddr_t gpa) + mmio_info_t *info) { struct vcpu *v =3D current; const struct mmio_handler *handler =3D NULL; - const struct hsr_dabt dabt =3D hsr.dabt; - mmio_info_t info =3D { - .gpa =3D gpa, - .dabt =3D dabt - }; + int rc; =20 - ASSERT(hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); + ASSERT(info->dabt.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); =20 - handler =3D find_mmio_handler(v->domain, info.gpa); - if ( !handler ) + if ( !((info->dabt_instr.state =3D=3D INSTR_VALID) || (info->dabt_inst= r.state =3D=3D INSTR_LDR_STR_POSTINDEXING)) ) { - int rc; + ASSERT_UNREACHABLE(); + return IO_ABORT; + } =20 - rc =3D try_fwd_ioserv(regs, v, &info); + handler =3D find_mmio_handler(v->domain, info->gpa); + if ( !handler ) + { + rc =3D try_fwd_ioserv(regs, v, info); if ( rc =3D=3D IO_HANDLED ) return handle_ioserv(regs, v); =20 return rc; } =20 - /* All the instructions used on emulated MMIO region should be valid */ - if ( !dabt.valid ) - return IO_ABORT; - /* - * Erratum 766422: Thumb store translation fault to Hypervisor may - * not have correct HSR Rt value. + * At this point, we know that the instruction is either valid or has = been + * decoded successfully. Thus, Xen should be allowed to execute the + * instruction on the emulated MMIO region. */ - if ( check_workaround_766422() && (regs->cpsr & PSR_THUMB) && - dabt.write ) - { - int rc; - - rc =3D decode_instruction(regs, &info); - if ( rc ) - { - gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); - return IO_ABORT; - } - } - - if ( info.dabt.write ) - return handle_write(handler, v, &info); + if ( info->dabt.write ) + return handle_write(handler, v, info); else - return handle_read(handler, v, &info); + return handle_read(handler, v, info); } =20 void register_mmio_handler(struct domain *d, diff --git a/xen/arch/arm/ioreq.c b/xen/arch/arm/ioreq.c index 308650b400..58cd320b5a 100644 --- a/xen/arch/arm/ioreq.c +++ b/xen/arch/arm/ioreq.c @@ -47,6 +47,7 @@ enum io_state try_fwd_ioserv(struct cpu_user_regs *regs, struct vcpu *v, mmio_info_t *info) { struct vcpu_io *vio =3D &v->io; + struct dabt_instr instr =3D info->dabt_instr; ioreq_t p =3D { .type =3D IOREQ_TYPE_COPY, .addr =3D info->gpa, @@ -76,10 +77,10 @@ enum io_state try_fwd_ioserv(struct cpu_user_regs *regs, if ( !s ) return IO_UNHANDLED; =20 - if ( !info->dabt.valid ) - return IO_ABORT; + ASSERT(dabt.valid); =20 vio->req =3D p; + vio->info.dabt_instr =3D instr; =20 rc =3D ioreq_send(s, &p, 0); if ( rc !=3D IO_RETRY || v->domain->is_shutting_down ) @@ -95,6 +96,7 @@ enum io_state try_fwd_ioserv(struct cpu_user_regs *regs, bool arch_ioreq_complete_mmio(void) { struct vcpu *v =3D current; + struct instr_details dabt_instr =3D v->io.info.dabt_instr; struct cpu_user_regs *regs =3D guest_cpu_user_regs(); const union hsr hsr =3D { .bits =3D regs->hsr }; =20 @@ -106,6 +108,7 @@ bool arch_ioreq_complete_mmio(void) =20 if ( handle_ioserv(regs, v) =3D=3D IO_HANDLED ) { + post_increment_register(&dabt_instr); advance_pc(regs, hsr); return true; } diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 7a1b679b8c..120c971b0f 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1893,6 +1893,21 @@ static bool try_map_mmio(gfn_t gfn) return !map_regions_p2mt(d, gfn, 1, mfn, p2m_mmio_direct_c); } =20 +static inline bool check_p2m(bool is_data, paddr_t gpa) +{ + /* + * First check if the translation fault can be resolved by the P2M sub= system. + * If that's the case nothing else to do. + */ + if ( p2m_resolve_translation_fault(current->domain , gaddr_to_gfn(gpa)= ) ) + return true; + + if ( is_data && try_map_mmio(gaddr_to_gfn(gpa)) ) + return true; + + return false; +} + static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, const union hsr hsr) { @@ -1906,6 +1921,8 @@ static void do_trap_stage2_abort_guest(struct cpu_use= r_regs *regs, paddr_t gpa; uint8_t fsc =3D xabt.fsc & ~FSC_LL_MASK; bool is_data =3D (hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); + mmio_info_t info; + enum io_state state; =20 /* * If this bit has been set, it means that this stage-2 abort is caused @@ -1959,21 +1976,52 @@ static void do_trap_stage2_abort_guest(struct cpu_u= ser_regs *regs, return; } case FSC_FLT_TRANS: + { + info.gpa =3D gpa; + info.dabt =3D hsr.dabt; + /* - * Attempt first to emulate the MMIO as the data abort will - * likely happen in an emulated region. - * - * Note that emulated region cannot be executed + * Assumption :- Most of the times when we get a data abort and th= e ISS + * is invalid or an instruction abort, the underlying cause is tha= t the + * page tables have not been set up correctly. */ - if ( is_data ) + if ( !is_data || !info.dabt.valid ) { - enum io_state state =3D try_handle_mmio(regs, hsr, gpa); + if ( check_p2m(is_data, gpa) ) + return; =20 - switch ( state ) - { + /* + * If the instruction abort could not be resolved by setting t= he + * appropriate bits in the translation table, then Xen should + * forward the abort to the guest. + */ + if ( !is_data ) + goto inject_abt; + } + + try_decode_instruction(regs, &info); + + /* + * If Xen could not decode the instruction or encountered an error + * while decoding, then it should forward the abort to the guest. + */ + if ( info.dabt_instr.state =3D=3D INSTR_ERROR ) + goto inject_abt; + + state =3D try_handle_mmio(regs, &info); + + switch ( state ) + { case IO_ABORT: goto inject_abt; case IO_HANDLED: + /* + * If the instruction was decoded and has executed success= fully + * on the MMIO region, then Xen should execute the next pa= rt of + * the instruction. (for eg increment the rn if it is a + * post-indexing instruction. + */ + post_increment_register(&info.dabt_instr); advance_pc(regs, hsr); return; case IO_RETRY: @@ -1982,21 +2030,18 @@ static void do_trap_stage2_abort_guest(struct cpu_u= ser_regs *regs, case IO_UNHANDLED: /* IO unhandled, try another way to handle it. */ break; - } } =20 /* - * First check if the translation fault can be resolved by the - * P2M subsystem. If that's the case nothing else to do. + * If the instruction syndrome was invalid, then we already checke= d if + * this was due to a P2M fault. So no point to check again as the = result + * will be the same. */ - if ( p2m_resolve_translation_fault(current->domain, - gaddr_to_gfn(gpa)) ) - return; - - if ( is_data && try_map_mmio(gaddr_to_gfn(gpa)) ) + if ( info.dabt.valid && check_p2m(is_data, gpa) ) return; =20 break; + } default: gprintk(XENLOG_WARNING, "Unsupported FSC: HSR=3D%#"PRIregister" DFSC=3D%#x\n", diff --git a/xen/arch/x86/include/asm/ioreq.h b/xen/arch/x86/include/asm/io= req.h index d06ce9a6ea..ecfe7f9fdb 100644 --- a/xen/arch/x86/include/asm/ioreq.h +++ b/xen/arch/x86/include/asm/ioreq.h @@ -26,6 +26,9 @@ #include #endif =20 +struct arch_vcpu_io { +}; + #endif /* __ASM_X86_IOREQ_H__ */ =20 /* diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 10ea969c7a..406d9bc610 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -160,6 +160,8 @@ struct vcpu_io { /* I/O request in flight to device model. */ enum vio_completion completion; ioreq_t req; + /* Arch specific info pertaining to the io request */ + struct arch_vcpu_io info; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2022 12:40:32.1618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44db705b-959e-4b2f-582d-08d9fb80acde X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0008.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6740 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1646138466534100009 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the abort was caused due to access to stage1 translation table, Xen will assume that the stage1 translation table is in the non MMIO region. It will try to resolve the translation fault. If it succeeds, it will return to the guest to retry the instruction. If not, then it means that the table is in MMIO region which is not expected by Xen. Thus, Xen will forward the abort to the guest. Signed-off-by: Ayan Kumar Halder --- Changelog :- v1..v8 - NA v9 - 1. Extracted this change from "[XEN v8 2/2] xen/arm64: io: Support instructions (for which ISS is not..." into a separate patch of its own. The reason being this is an existing bug in the codebase. xen/arch/arm/io.c | 11 +++++++++++ xen/arch/arm/traps.c | 12 +++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index bea69ffb08..ebcb8ed548 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -128,6 +128,17 @@ void try_decode_instruction(const struct cpu_user_regs= *regs, return; } =20 + /* + * At this point, we know that the stage1 translation table is in the = MMIO + * region. This is not expected by Xen and thus it forwards the abort = to the + * guest. + */ + if ( info->dabt.s1ptw ) + { + info->dabt_instr.state =3D INSTR_ERROR; + return; + } + /* * Armv8 processor does not provide a valid syndrome for decoding some * instructions. So in order to process these instructions, Xen must diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 120c971b0f..e491ca15d7 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1923,6 +1923,7 @@ static void do_trap_stage2_abort_guest(struct cpu_use= r_regs *regs, bool is_data =3D (hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); mmio_info_t info; enum io_state state; + bool check_mmio_region =3D true; =20 /* * If this bit has been set, it means that this stage-2 abort is caused @@ -1987,7 +1988,16 @@ static void do_trap_stage2_abort_guest(struct cpu_us= er_regs *regs, */ if ( !is_data || !info.dabt.valid ) { - if ( check_p2m(is_data, gpa) ) + /* + * If the translation fault was caused due to access to stage 1 + * translation table, then we try to set the translation table= entry + * for page1 translation table (assuming that it is in the non= mmio + * region). + */ + if ( xabt.s1ptw ) + check_mmio_region =3D false; + + if ( check_p2m((is_data && check_mmio_region), gpa) ) return; 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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch01.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v9 4/4] xen/arm64: io: Handle data abort due to cache maintenance instructions Date: Tue, 1 Mar 2022 12:40:22 +0000 Message-ID: <20220301124022.10168-5-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220301124022.10168-1-ayankuma@xilinx.com> References: <20220301124022.10168-1-ayankuma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 085d2622-7828-4709-ca18-08d9fb80ae8f X-MS-TrafficTypeDiagnostic: SA2PR02MB7595:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2022 12:40:35.0024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 085d2622-7828-4709-ca18-08d9fb80ae8f X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0034.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR02MB7595 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1646138464661100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the data abort is caused due to cache maintenance for an address, there are two scenarios:- 1. Address belonging to a non emulated region - For this, Xen should set the corresponding bit in the translation table entry to valid and return to the guest to retry the instruction. This can happen sometimes as Xen need to set the translation table entry to invalid. (for eg 'Break-Before-Make' sequence). 2. Address belongs to an emulated region - Xen should ignore the instruction (ie increment the PC) and return to the guest. We try to deal with scenario#1, by invoking check_p2m(). If this is unsuccessful, then we assume scenario#2. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changelog:- v1...v8 - NA v9 - Extracted this change from "[XEN v7 2/2] xen/arm64: io: Support instructions (for which ISS is not ..." into a separate patch of its own. The reason being this addresses an existing bug in the codebase. xen/arch/arm/include/asm/mmio.h | 3 ++- xen/arch/arm/io.c | 11 +++++++++++ xen/arch/arm/traps.c | 6 ++++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmi= o.h index ef2c57a2d5..75d362d5f5 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -34,7 +34,8 @@ enum instr_decode_state * Instruction is decoded successfully. It is a ldr/str post indexing * instruction. */ - INSTR_LDR_STR_POSTINDEXING + INSTR_LDR_STR_POSTINDEXING, + INSTR_IGNORE /* Instruction is ignored */ }; =20 typedef struct diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index ebcb8ed548..7e9dd4bb08 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -139,6 +139,17 @@ void try_decode_instruction(const struct cpu_user_regs= *regs, return; } =20 + /* + * When the data abort is caused due to cache maintenance, Xen should = ignore + * this instruction as the cache maintenance was caused on an address = belonging + * to the emulated region. + */ + if ( info->dabt.cache ) + { + info->dabt_instr.state =3D INSTR_IGNORE; + return; + } + /* * Armv8 processor does not provide a valid syndrome for decoding some * instructions. So in order to process these instructions, Xen must diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index e491ca15d7..5879640b73 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2011,6 +2011,12 @@ static void do_trap_stage2_abort_guest(struct cpu_us= er_regs *regs, =20 try_decode_instruction(regs, &info); =20 + if ( info.dabt_instr.state =3D=3D INSTR_IGNORE ) + { + advance_pc(regs, hsr); + return; + } + /* * If Xen could not decode the instruction or encountered an error * while decoding, then it should forward the abort to the guest. --=20 2.17.1