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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch01.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v6 1/3] xen/arm64: Decode ldr/str post increment operations Date: Wed, 2 Feb 2022 17:30:15 +0000 Message-ID: <20220202173017.48463-2-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220202173017.48463-1-ayankuma@xilinx.com> References: <20220202173017.48463-1-ayankuma@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0f04e706-26ab-4a20-21be-08d9e671b1a9 X-MS-TrafficTypeDiagnostic: MN2PR02MB6047:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2022 17:30:23.4261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f04e706-26ab-4a20-21be-08d9e671b1a9 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT016.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6047 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1643823067260100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment, Xen does not decode any of the arm64 instructions. This means that hsr_dabt.isv =3D 0, Xen cannot handle those instructions. This will lead to Xen abort the guests (from which those instructions originated). With this patch, Xen is able to decode ldr/str post indexing instructions. These are a subset of instructions for which hsr_dabt.isv =3D 0 The following instructions are now supported by Xen :- 1. ldr x2, [x1], #8 2. ldr w2, [x1], #-4 3. ldr x2, [x1], #-8 4. ldr w2, [x1], #4 5. ldrh w2, [x1], #2 6. ldrb w2, [x1], #1 7. str x2, [x1], #8 8. str w2, [x1], #-4 9. strh w2, [x1], #2 10. strb w2, [x1], #1 In the subsequent patches, decode_arm64() will get invoked when hsr_dabt.isv=3D0. Signed-off-by: Ayan Kumar Halder --- Changelog :- v2..v5 - Mentioned in the cover letter. v6 - 1. Fixed the code style issues as mentioned in v5. xen/arch/arm/decode.c | 80 ++++++++++++++++++++++++++++++++- xen/arch/arm/decode.h | 49 +++++++++++++++++--- xen/arch/arm/include/asm/mmio.h | 4 ++ xen/arch/arm/io.c | 2 +- 4 files changed, 125 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 792c2e92a7..3f2d2a3f62 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -23,6 +23,7 @@ #include =20 #include +#include =20 #include "decode.h" =20 @@ -84,6 +85,78 @@ bad_thumb2: return 1; } =20 +static int decode_arm64(register_t pc, mmio_info_t *info) +{ + union instr opcode =3D {0}; + struct hsr_dabt *dabt =3D &info->dabt; + struct instr_details *dabt_instr =3D &info->dabt_instr; + + if ( raw_copy_from_guest(&opcode.value, (void * __user)pc, sizeof (opc= ode)) ) + { + gprintk(XENLOG_ERR, "Could not copy the instruction from PC\n"); + goto bad_loadstore; + } + + /* + * Refer Arm v8 ARM DDI 0487G.b, Page - C6-1107 + * "Shared decode for all encodings" (under ldr immediate) + * If n =3D=3D t && n !=3D 31, then the return value is implementation= defined + * (can be WBSUPPRESS, UNKNOWN, UNDEFINED or NOP). Thus, we do not sup= port + * this. This holds true for ldrb/ldrh immediate as well. + * + * Also refer, Page - C6-1384, the above described behaviour is same f= or + * str immediate. This holds true for strb/strh immediate as well + */ + if ( (opcode.ldr_str.rn =3D=3D opcode.ldr_str.rt) && (opcode.ldr_str.r= n !=3D 31) ) + { + gprintk(XENLOG_ERR, "Rn should not be equal to Rt except for r31\n= "); + goto bad_loadstore; + } + + /* First, let's check for the fixed values */ + if ( (opcode.value & POST_INDEX_FIXED_MASK) !=3D POST_INDEX_FIXED_VALU= E ) + { + gprintk(XENLOG_ERR, + "Decoding instruction 0x%x is not supported", opcode.value= ); + goto bad_loadstore; + } + + if ( opcode.ldr_str.v !=3D 0 ) + { + gprintk(XENLOG_ERR, + "ldr/str post indexing for vector types are not supported\= n"); + goto bad_loadstore; + } + + /* Check for STR (immediate) */ + if ( opcode.ldr_str.opc =3D=3D 0 ) + dabt->write =3D 1; + /* Check for LDR (immediate) */ + else if ( opcode.ldr_str.opc =3D=3D 1 ) + dabt->write =3D 0; + else + { + gprintk(XENLOG_ERR, + "Decoding ldr/str post indexing is not supported for this = variant\n"); + goto bad_loadstore; + } + + gprintk(XENLOG_INFO, + "opcode->ldr_str.rt =3D 0x%x, opcode->ldr_str.size =3D 0x%x, o= pcode->ldr_str.imm9 =3D %d\n", + opcode.ldr_str.rt, opcode.ldr_str.size, opcode.ldr_str.imm9); + + update_dabt(dabt, opcode.ldr_str.rt, opcode.ldr_str.size, false); + + dabt_instr->rn =3D opcode.ldr_str.rn; + dabt_instr->imm9 =3D opcode.ldr_str.imm9; + + return 0; + + bad_loadstore: + gprintk(XENLOG_ERR, "unhandled Arm instruction 0x%x\n", opcode.value); + return 1; +} + static int decode_thumb(register_t pc, struct hsr_dabt *dabt) { uint16_t instr; @@ -150,10 +223,13 @@ bad_thumb: return 1; } =20 -int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt) +int decode_instruction(const struct cpu_user_regs *regs, mmio_info_t *info) { if ( is_32bit_domain(current->domain) && regs->cpsr & PSR_THUMB ) - return decode_thumb(regs->pc, dabt); + return decode_thumb(regs->pc, &info->dabt); + + if ( !psr_mode_is_32bit(regs) ) + return decode_arm64(regs->pc, info); =20 /* TODO: Handle ARM instruction */ gprintk(XENLOG_ERR, "unhandled ARM instruction\n"); diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index 4613763bdb..fe7512a053 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -23,19 +23,54 @@ #include #include =20 -/** - * Decode an instruction from pc - * /!\ This function is not intended to fully decode an instruction. It - * considers that the instruction is valid. +/* + * Refer to the ARMv8 ARM (DDI 0487G.b), Section C4.1.4 Loads and Stores + * Page 318 specifies the following bit pattern for + * "load/store register (immediate post-indexed)". + * + * 31 30 29 27 26 25 23 21 20 11 9 4 0 + * ___________________________________________________________________ + * |size|1 1 1 |V |0 0 |opc |0 | imm9 |0 1 | Rn | Rt | + * |____|______|__|____|____|__|_______________|____|_________|_______| + */ +union instr { + uint32_t value; + struct { + unsigned int rt:5; /* Rt register */ + unsigned int rn:5; /* Rn register */ + unsigned int fixed1:2; /* value =3D=3D 01b */ + signed int imm9:9; /* imm9 */ + unsigned int fixed2:1; /* value =3D=3D 0b */ + unsigned int opc:2; /* opc */ + unsigned int fixed3:2; /* value =3D=3D 00b */ + unsigned int v:1; /* vector */ + unsigned int fixed4:3; /* value =3D=3D 111b */ + unsigned int size:2; /* size */ + } ldr_str; +}; + +#define POST_INDEX_FIXED_MASK 0x3B200C00 +#define POST_INDEX_FIXED_VALUE 0x38000400 + +/* Decode an instruction from pc + * /!\ This function is intended to decode an instruction. It considers th= at the + * instruction is valid. * - * This function will get: - * - The transfer register + * In case of thumb mode, this function will get: + * - The transfer register (ie Rt) * - Sign bit * - Size + * + * In case of arm64 mode, this function will get: + * - The transfer register (ie Rt) + * - The source register (ie Rn) + * - Size + * - Immediate offset + * - Read or write */ =20 int decode_instruction(const struct cpu_user_regs *regs, - struct hsr_dabt *dabt); + mmio_info_t *info); =20 #endif /* __ARCH_ARM_DECODE_H_ */ =20 diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmi= o.h index 7ab873cb8f..3354d9c635 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -29,6 +29,10 @@ typedef struct { struct hsr_dabt dabt; + struct instr_details { + unsigned long rn:5; + signed int imm9:9; + } dabt_instr; paddr_t gpa; } mmio_info_t; =20 diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 729287e37c..a289d393f9 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -134,7 +134,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, { int rc; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2022 17:30:24.4795 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f3963ef-38f8-40c3-ddbc-08d9e671b249 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT032.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB7059 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1643823067267100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For instructions on MMIO regions emulated by Xen, Xen reads the remaining bits of the HSR. It determines if the instruction is to be ignored, retried or decoded. If it gets an error while decoding the instruction, then it sends an abort to the guest. If the instruction is valid or successfully decoded, Xen tries to execute the instruction for the emulated MMIO region. If the instruction was successfully executed, then Xen determines if the instruction needs further processing. For eg:- In case of ldr/str post indexing on arm64, the rn register needs to be updated. Signed-off-by: Ayan Kumar Halder --- Changelog :- v2..v5 - Mentioned in the cover letter. v6 - 1. Mantained the decoding state of the instruction. This is used by the caller to either abort the guest or retry or ignore or perform read/write on the mmio region. 2. try_decode() invokes decoding for both aarch64 and thumb state. (Previou= sly it used to invoke decoding only for aarch64 state). Thus, it handles all the checking of the registers before invoking any decoding of instruction. try_decode_instruction_invalid_iss() has thus been removed. xen/arch/arm/arm32/traps.c | 6 ++ xen/arch/arm/arm64/traps.c | 41 ++++++++++++ xen/arch/arm/decode.h | 12 +++- xen/arch/arm/include/asm/traps.h | 2 + xen/arch/arm/io.c | 108 +++++++++++++++++++++++++------ 5 files changed, 148 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/traps.c b/xen/arch/arm/arm32/traps.c index 9c9790a6d1..6ad9a31499 100644 --- a/xen/arch/arm/arm32/traps.c +++ b/xen/arch/arm/arm32/traps.c @@ -21,6 +21,7 @@ =20 #include =20 +#include #include #include =20 @@ -82,6 +83,11 @@ void do_trap_data_abort(struct cpu_user_regs *regs) do_unexpected_trap("Data Abort", regs); } =20 +void post_increment_register(const struct instr_details *instr) +{ + ASSERT_UNREACHABLE(); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c index 9113a15c7a..4de2206801 100644 --- a/xen/arch/arm/arm64/traps.c +++ b/xen/arch/arm/arm64/traps.c @@ -18,9 +18,12 @@ =20 #include =20 +#include #include +#include #include #include +#include =20 #include =20 @@ -44,6 +47,44 @@ void do_bad_mode(struct cpu_user_regs *regs, int reason) panic("bad mode\n"); } =20 +void post_increment_register(const struct instr_details *instr) +{ + struct cpu_user_regs *regs =3D guest_cpu_user_regs(); + register_t val; + + /* + * Handle when rn =3D SP + * Refer ArmV8 ARM DDI 0487G.b, Page - D1-2463 "Stack pointer register= selection" + * t =3D SP_EL0 + * h =3D SP_ELx + * and M[3:0] (Page - C5-474 "When exception taken from AArch64 state:= ") + */ + if (instr->rn =3D=3D 31 ) + { + if ( (regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1h ) + val =3D regs->sp_el1; + else if ( ((regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1t) || + ((regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL0t) ) + val =3D regs->sp_el0; + else + ASSERT_UNREACHABLE(); + } + else + val =3D get_user_reg(regs, instr->rn); + + val +=3D instr->imm9; + + if ( instr->rn =3D=3D 31 ) + { + if ( (regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1h ) + regs->sp_el1 =3D val; + else + regs->sp_el0 =3D val; + } + else + set_user_reg(regs, instr->rn, val); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index fe7512a053..5efd72405e 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -52,7 +52,17 @@ union instr { #define POST_INDEX_FIXED_MASK 0x3B200C00 #define POST_INDEX_FIXED_VALUE 0x38000400 =20 -/* Decode an instruction from pc +enum instr_decode_state +{ + INSTR_ERROR, /* Error encountered while decoding the instruction */ + INSTR_VALID, /* ISS is valid, so there is no need to decode */ + INSTR_SUCCESS, /* Instruction is decoded successfully */ + INSTR_IGNORE, /* Instruction is to be ignored (similar to NOP) */ + INSTR_RETRY /* Instruction is to be retried */ +}; + +/* + * Decode an instruction from pc * /!\ This function is intended to decode an instruction. It considers th= at the * instruction is valid. * diff --git a/xen/arch/arm/include/asm/traps.h b/xen/arch/arm/include/asm/tr= aps.h index 2ed2b85c6f..95c46ad391 100644 --- a/xen/arch/arm/include/asm/traps.h +++ b/xen/arch/arm/include/asm/traps.h @@ -109,6 +109,8 @@ static inline register_t sign_extend(const struct hsr_d= abt dabt, register_t r) return r; } =20 +void post_increment_register(const struct instr_details *instr); + #endif /* __ASM_ARM_TRAPS__ */ /* * Local variables: diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index a289d393f9..1011327058 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -95,6 +95,59 @@ static const struct mmio_handler *find_mmio_handler(stru= ct domain *d, return handler; } =20 +enum instr_decode_state try_decode_instruction(const struct cpu_user_regs = *regs, + mmio_info_t *info) +{ + int rc; + + /* + * Erratum 766422: Thumb store translation fault to Hypervisor may + * not have correct HSR Rt value. + */ + if ( check_workaround_766422() && (regs->cpsr & PSR_THUMB) && + info->dabt.write ) + { + rc =3D decode_instruction(regs, info); + if ( rc ) + { + gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); + return INSTR_ERROR; + } + } + + /* If ISS is valid, then no need to decode the instruction any further= */ + if (info->dabt.valid) + return INSTR_VALID; + + /* + * Xen should not decode the instruction when it was trapped due to + * translation fault. + */ + if ( info->dabt.s1ptw ) + return INSTR_RETRY; + + /* + * If the fault occurred due to cache maintenance or address translati= on + * instructions, then Xen needs to ignore these instructions. + */ + if ( info->dabt.cache ) + return INSTR_IGNORE; + + /* + * Armv8 processor does not provide a valid syndrome for decoding some + * instructions. So in order to process these instructions, Xen must + * decode them. + */ + rc =3D decode_instruction(regs, info); + if ( rc ) + { + gprintk(XENLOG_ERR, "Unable to decode instruction\n"); + return INSTR_ERROR; + } + else + return INSTR_SUCCESS; +} + enum io_state try_handle_mmio(struct cpu_user_regs *regs, const union hsr hsr, paddr_t gpa) @@ -106,14 +159,14 @@ enum io_state try_handle_mmio(struct cpu_user_regs *r= egs, .gpa =3D gpa, .dabt =3D dabt }; + int rc; + enum instr_decode_state state; =20 ASSERT(hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); =20 handler =3D find_mmio_handler(v->domain, info.gpa); if ( !handler ) { - int rc; - rc =3D try_fwd_ioserv(regs, v, &info); if ( rc =3D=3D IO_HANDLED ) return handle_ioserv(regs, v); @@ -121,31 +174,46 @@ enum io_state try_handle_mmio(struct cpu_user_regs *r= egs, return rc; } =20 - /* All the instructions used on emulated MMIO region should be valid */ - if ( !dabt.valid ) + state =3D try_decode_instruction(regs, &info); + + /* + * If the instruction was to be ignored by Xen, then it should return = to the + * caller which will increment the PC, so that the guest can execute t= he + * next instruction. + */ + if ( state =3D=3D INSTR_IGNORE ) + return IO_HANDLED; + /* + * If Xen could not decode the instruction for any reason, then it sho= uld + * ask the caller to abort the guest. + */ + else if ( state =3D=3D INSTR_ERROR ) return IO_ABORT; + /* When the instruction needs to be retried by the guest */ + else if ( state =3D=3D INSTR_RETRY ) + return IO_UNHANDLED; =20 /* - * Erratum 766422: Thumb store translation fault to Hypervisor may - * not have correct HSR Rt value. + * At this point, we know that the instruction is either valid or has = been + * decoded successfully. Thus, Xen should be allowed to execute the + * instruction on the emulated MMIO region. */ - if ( check_workaround_766422() && (regs->cpsr & PSR_THUMB) && - dabt.write ) - { - int rc; + if ( info.dabt.write ) + rc =3D handle_write(handler, v, &info); + else + rc =3D handle_read(handler, v, &info); =20 - rc =3D decode_instruction(regs, &info); - if ( rc ) - { - gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); - return IO_ABORT; - } + /* + * If the instruction was decoded and has executed successfully on the= MMIO + * region, then Xen should execute the next part of the instruction. (= for eg + * increment the rn if it is a post-indexing instruction. + */ + if ( (rc =3D=3D IO_HANDLED) && (state =3D=3D INSTR_SUCCESS) ) + { + post_increment_register(&info.dabt_instr); } =20 - if ( info.dabt.write ) - return handle_write(handler, v, &info); - else - return handle_read(handler, v, &info); + return rc; } =20 void register_mmio_handler(struct domain *d, --=20 2.17.1 From nobody Sun May 19 09:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=xilinx.com); dmarc=fail(p=none dis=none) header.from=xilinx.com ARC-Seal: i=2; a=rsa-sha256; t=1643823063; cv=pass; d=zohomail.com; s=zohoarc; b=VXAMyyPsoqdlxLJYuH45lFTgGMKxefW7+77TjyrLIKxdurB0aSrT4J4LIQy8NaFqXdwXlMbDG7fgSr1y1EbXi82TKaZT7Fjn7X62nUBTJoj2R0ianHxZSdPdc8q74fs2WR8hqvrGI+tYX80zSjLnz8P+6Y4MFHvV6bNM+BymIXs= ARC-Message-Signature: i=2; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2022 17:30:26.3046 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9ccfdd79-e2d4-4e90-5ac6-08d9e671b360 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT059.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR02MB3723 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1643823067277100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When an instruction is trapped in Xen due to translation fault, Xen checks = if the ISS is valid. If not, Xen tries to resolve the translation fault using p2m page tables. In case if it is a data abort, Xen will try to map the mmio region to the guest (ie tries to emulate the mmio region). If it is not successfull, then it tries to decode the instruction. It saves the decoding state, rn and imm9 to ioreq. Whenever the vcpu handles the ioreq successfully, it will read the decoding state to determine if the instruction decoded was a ldr/str post indexing (ie INSTR_LDR_STR_POSTINDEX= ING). If so, it uses these details to post increment rn. Signed-off-by: Ayan Kumar Halder --- Changelog :- v2..v5 - Provided in cover letter. v6 - 1. Introduced a new field('enum instr_decode_state state') inside 'struct instr_details'. This holds the decoding state of the instruction. This is later read by the post_increment_register() to determine if rn need= s to be incremented. Also, this is read by the callers of try_decode_instruction= () to determine if the instruction was valid or ignored or to be retried or error or decoded successfully. 2. Also stored 'instr_details' inside 'struct ioreq'. This enables arch_ioreq_complete_mmio() to invoke post_increment_register() without deco= ding the instruction again. 3. Check hsr.dabt.valid in do_trap_stage2_abort_guest(). If it is not valid, then decode the instruction. This ensures that try_handle_mmio() is invoked= only when the instruction is either valid or decoded successfully. 4. Inside do_trap_stage2_abort_guest(), if hsr.dabt.valid is not set, then resolve the translation fault before trying to decode the instruction. If translation fault is resolved, then return to the guest to execute the inst= ruction again. xen/arch/arm/arm64/traps.c | 4 +++ xen/arch/arm/decode.c | 1 + xen/arch/arm/decode.h | 9 ------ xen/arch/arm/include/asm/mmio.h | 13 ++++++++ xen/arch/arm/io.c | 56 ++++++++++----------------------- xen/arch/arm/ioreq.c | 13 +++++--- xen/arch/arm/traps.c | 56 +++++++++++++++++++++++++++++++-- xen/include/public/hvm/ioreq.h | 19 +++++------ 8 files changed, 108 insertions(+), 63 deletions(-) diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c index 4de2206801..505a843b07 100644 --- a/xen/arch/arm/arm64/traps.c +++ b/xen/arch/arm/arm64/traps.c @@ -52,6 +52,10 @@ void post_increment_register(const struct instr_details = *instr) struct cpu_user_regs *regs =3D guest_cpu_user_regs(); register_t val; =20 + /* Currently, we handle only ldr/str post indexing instructions */ + if ( instr->state !=3D INSTR_LDR_STR_POSTINDEXING ) + return; + /* * Handle when rn =3D SP * Refer ArmV8 ARM DDI 0487G.b, Page - D1-2463 "Stack pointer register= selection" diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 3f2d2a3f62..0a4d9d2772 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -147,6 +147,7 @@ static int decode_arm64(register_t pc, mmio_info_t *inf= o) =20 update_dabt(dabt, opcode.ldr_str.rt, opcode.ldr_str.size, false); =20 + dabt_instr->state =3D INSTR_LDR_STR_POSTINDEXING; dabt_instr->rn =3D opcode.ldr_str.rn; dabt_instr->imm9 =3D opcode.ldr_str.imm9; =20 diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index 5efd72405e..6a09b07b46 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -52,15 +52,6 @@ union instr { #define POST_INDEX_FIXED_MASK 0x3B200C00 #define POST_INDEX_FIXED_VALUE 0x38000400 =20 -enum instr_decode_state -{ - INSTR_ERROR, /* Error encountered while decoding the instruction */ - INSTR_VALID, /* ISS is valid, so there is no need to decode */ - INSTR_SUCCESS, /* Instruction is decoded successfully */ - INSTR_IGNORE, /* Instruction is to be ignored (similar to NOP) */ - INSTR_RETRY /* Instruction is to be retried */ -}; - /* * Decode an instruction from pc * /!\ This function is intended to decode an instruction. It considers th= at the diff --git a/xen/arch/arm/include/asm/mmio.h b/xen/arch/arm/include/asm/mmi= o.h index 3354d9c635..f7cdf66a5b 100644 --- a/xen/arch/arm/include/asm/mmio.h +++ b/xen/arch/arm/include/asm/mmio.h @@ -26,12 +26,23 @@ =20 #define MAX_IO_HANDLER 16 =20 +enum instr_decode_state +{ + INSTR_ERROR, /* Error encountered while decoding th= e instruction */ + INSTR_VALID, /* ISS is valid, so there is no need t= o decode */ + INSTR_LDR_STR_POSTINDEXING, /* Instruction is decoded successfully. + It is ldr/str post indexing */ + INSTR_IGNORE, /* Instruction is to be ignored (simil= ar to NOP) */ + INSTR_RETRY /* Instruction is to be retried */ +}; + typedef struct { struct hsr_dabt dabt; struct instr_details { unsigned long rn:5; signed int imm9:9; + enum instr_decode_state state; } dabt_instr; paddr_t gpa; } mmio_info_t; @@ -77,6 +88,8 @@ void register_mmio_handler(struct domain *d, int domain_io_init(struct domain *d, int max_count); void domain_io_free(struct domain *d); =20 +void try_decode_instruction(const struct cpu_user_regs *regs, + mmio_info_t *info); =20 #endif /* __ASM_ARM_MMIO_H__ */ =20 diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 1011327058..46726637c6 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -95,8 +95,8 @@ static const struct mmio_handler *find_mmio_handler(struc= t domain *d, return handler; } =20 -enum instr_decode_state try_decode_instruction(const struct cpu_user_regs = *regs, - mmio_info_t *info) +void try_decode_instruction(const struct cpu_user_regs *regs, + mmio_info_t *info) { int rc; =20 @@ -111,27 +111,37 @@ enum instr_decode_state try_decode_instruction(const = struct cpu_user_regs *regs, if ( rc ) { gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); - return INSTR_ERROR; + info->dabt_instr.state =3D INSTR_ERROR; + return; } } =20 /* If ISS is valid, then no need to decode the instruction any further= */ if (info->dabt.valid) - return INSTR_VALID; + { + info->dabt_instr.state =3D INSTR_VALID; + return; + } =20 /* * Xen should not decode the instruction when it was trapped due to * translation fault. */ if ( info->dabt.s1ptw ) - return INSTR_RETRY; + { + info->dabt_instr.state =3D INSTR_RETRY; + return; + } =20 /* * If the fault occurred due to cache maintenance or address translati= on * instructions, then Xen needs to ignore these instructions. */ if ( info->dabt.cache ) - return INSTR_IGNORE; + { + info->dabt_instr.state =3D INSTR_IGNORE; + return; + } =20 /* * Armv8 processor does not provide a valid syndrome for decoding some @@ -142,10 +152,8 @@ enum instr_decode_state try_decode_instruction(const s= truct cpu_user_regs *regs, if ( rc ) { gprintk(XENLOG_ERR, "Unable to decode instruction\n"); - return INSTR_ERROR; + info->dabt_instr.state =3D INSTR_ERROR; } - else - return INSTR_SUCCESS; } =20 enum io_state try_handle_mmio(struct cpu_user_regs *regs, @@ -160,7 +168,6 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, .dabt =3D dabt }; int rc; - enum instr_decode_state state; =20 ASSERT(hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); =20 @@ -174,25 +181,6 @@ enum io_state try_handle_mmio(struct cpu_user_regs *re= gs, return rc; } =20 - state =3D try_decode_instruction(regs, &info); - - /* - * If the instruction was to be ignored by Xen, then it should return = to the - * caller which will increment the PC, so that the guest can execute t= he - * next instruction. - */ - if ( state =3D=3D INSTR_IGNORE ) - return IO_HANDLED; - /* - * If Xen could not decode the instruction for any reason, then it sho= uld - * ask the caller to abort the guest. - */ - else if ( state =3D=3D INSTR_ERROR ) - return IO_ABORT; - /* When the instruction needs to be retried by the guest */ - else if ( state =3D=3D INSTR_RETRY ) - return IO_UNHANDLED; - /* * At this point, we know that the instruction is either valid or has = been * decoded successfully. Thus, Xen should be allowed to execute the @@ -203,16 +191,6 @@ enum io_state try_handle_mmio(struct cpu_user_regs *re= gs, else rc =3D handle_read(handler, v, &info); =20 - /* - * If the instruction was decoded and has executed successfully on the= MMIO - * region, then Xen should execute the next part of the instruction. (= for eg - * increment the rn if it is a post-indexing instruction. - */ - if ( (rc =3D=3D IO_HANDLED) && (state =3D=3D INSTR_SUCCESS) ) - { - post_increment_register(&info.dabt_instr); - } - return rc; } =20 diff --git a/xen/arch/arm/ioreq.c b/xen/arch/arm/ioreq.c index 308650b400..d8909aa903 100644 --- a/xen/arch/arm/ioreq.c +++ b/xen/arch/arm/ioreq.c @@ -23,10 +23,13 @@ =20 #include =20 +#include "decode.h" + enum io_state handle_ioserv(struct cpu_user_regs *regs, struct vcpu *v) { const union hsr hsr =3D { .bits =3D regs->hsr }; - const struct hsr_dabt dabt =3D hsr.dabt; + struct hsr_dabt dabt =3D hsr.dabt; + /* Code is similar to handle_read */ register_t r =3D v->io.req.data; =20 @@ -61,10 +64,13 @@ enum io_state try_fwd_ioserv(struct cpu_user_regs *regs, */ .df =3D 0, .data =3D get_user_reg(regs, info->dabt.reg), + .dabt_instr =3D &info->dabt_instr, .state =3D STATE_IOREQ_READY, }; struct ioreq_server *s =3D NULL; enum io_state rc; + bool instr_decoded =3D false; + const union hsr hsr =3D { .bits =3D regs->hsr }; =20 if ( vio->req.state !=3D STATE_IOREQ_NONE ) { @@ -76,9 +82,6 @@ enum io_state try_fwd_ioserv(struct cpu_user_regs *regs, if ( !s ) return IO_UNHANDLED; =20 - if ( !info->dabt.valid ) - return IO_ABORT; - vio->req =3D p; =20 rc =3D ioreq_send(s, &p, 0); @@ -95,6 +98,7 @@ enum io_state try_fwd_ioserv(struct cpu_user_regs *regs, bool arch_ioreq_complete_mmio(void) { struct vcpu *v =3D current; + struct instr_details *dabt_instr =3D v->io.req.dabt_instr; struct cpu_user_regs *regs =3D guest_cpu_user_regs(); const union hsr hsr =3D { .bits =3D regs->hsr }; =20 @@ -106,6 +110,7 @@ bool arch_ioreq_complete_mmio(void) =20 if ( handle_ioserv(regs, v) =3D=3D IO_HANDLED ) { + post_increment_register(dabt_instr); advance_pc(regs, hsr); return true; } diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 9339d12f58..6cce2379fa 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1906,6 +1906,7 @@ static void do_trap_stage2_abort_guest(struct cpu_use= r_regs *regs, paddr_t gpa; uint8_t fsc =3D xabt.fsc & ~FSC_LL_MASK; bool is_data =3D (hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); + mmio_info_t info; =20 /* * If this bit has been set, it means that this stage-2 abort is caused @@ -1959,6 +1960,51 @@ static void do_trap_stage2_abort_guest(struct cpu_us= er_regs *regs, return; } case FSC_FLT_TRANS: + + info.gpa =3D gpa; + info.dabt =3D hsr.dabt; + + /* Check if the ISS is valid. */ + if ( !hsr.dabt.valid ) + { + + /* + * Assumption :- Most of the times when we get a translation f= ault + * and the ISS is invalid, the underlying cause is that the pa= ge + * tables have not been set up correctly. + * First check if the translation fault can be resolved by the + * P2M subsystem. If that's the case nothing else to do. + */ + if ( p2m_resolve_translation_fault(current->domain, + gaddr_to_gfn(gpa)) ) + return; + + if ( is_data && try_map_mmio(gaddr_to_gfn(gpa)) ) + return; + + try_decode_instruction(regs, &info); + + /* + * If the instruction was to be ignored by Xen, then it should= return to the + * caller which will increment the PC, so that the guest can e= xecute the + * next instruction. + */ + if ( info.dabt_instr.state =3D=3D INSTR_IGNORE ) + { + advance_pc(regs, hsr); + return; + } + /* + * If Xen could not decode the instruction for any reason, the= n it should + * ask the caller to abort the guest. + */ + else if ( info.dabt_instr.state =3D=3D INSTR_ERROR ) + goto inject_abt; + /* When the instruction needs to be retried by the guest */ + else if ( info.dabt_instr.state =3D=3D INSTR_RETRY ) + return; + } + /* * Attempt first to emulate the MMIO as the data abort will * likely happen in an emulated region. @@ -1975,6 +2021,13 @@ static void do_trap_stage2_abort_guest(struct cpu_us= er_regs *regs, goto inject_abt; case IO_HANDLED: advance_pc(regs, hsr); + /* + * If the instruction was decoded and has executed success= fully + * on the MMIO region, then Xen should execute the next pa= rt of + * the instruction. (for eg increment the rn if it is a + * post-indexing instruction. + */ + post_increment_register(&info.dabt_instr); return; case IO_RETRY: /* finish later */ @@ -1985,8 +2038,7 @@ static void do_trap_stage2_abort_guest(struct cpu_use= r_regs *regs, } } =20 - /* - * First check if the translation fault can be resolved by the + /* First check if the translation fault can be resolved by the * P2M subsystem. If that's the case nothing else to do. */ if ( p2m_resolve_translation_fault(current->domain, diff --git a/xen/include/public/hvm/ioreq.h b/xen/include/public/hvm/ioreq.h index c511fae8e7..e4183960d8 100644 --- a/xen/include/public/hvm/ioreq.h +++ b/xen/include/public/hvm/ioreq.h @@ -50,19 +50,20 @@ * SEGMENT |BUS |DEV |FN |OFFSET */ struct ioreq { - uint64_t addr; /* physical address */ - uint64_t data; /* data (or paddr of data) */ - uint32_t count; /* for rep prefixes */ - uint32_t size; /* size in bytes */ - uint32_t vp_eport; /* evtchn for notifications to/from device mod= el */ + uint64_t addr; /* physical address */ + uint64_t data; /* data (or paddr of data) */ + uint32_t count; /* for rep prefixes */ + uint32_t size; /* size in bytes */ + uint32_t vp_eport; /* evtchn for notifications to/from d= evice model */ uint16_t _pad0; uint8_t state:4; - uint8_t data_is_ptr:1; /* if 1, data above is the guest paddr - * of the real data to use. */ - uint8_t dir:1; /* 1=3Dread, 0=3Dwrite */ + uint8_t data_is_ptr:1; /* if 1, data above is the guest paddr + * of the real data to use. */ + uint8_t dir:1; /* 1=3Dread, 0=3Dwrite */ uint8_t df:1; uint8_t _pad1:1; - uint8_t type; /* I/O type */ + uint8_t type; /* I/O type */ + struct instr_details *dabt_instr; /* when the instruction is decoded */ }; typedef struct ioreq ioreq_t; =20 --=20 2.17.1