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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch01.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v4] xen/arm64: io: Decode ldr/str post-indexing instructions Date: Tue, 25 Jan 2022 21:18:08 +0000 Message-ID: <20220125211808.23810-1-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 52cac653-2b89-441b-74a2-08d9e04832f2 X-MS-TrafficTypeDiagnostic: CY4PR02MB2583:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YT9mgZ9sdPTW/8yZ3r35a1v3d700xlk2wa88GLnjnBFI1UPy5l4DDkZcL+8yko5SPDyUTGrVOQ7PdE1hxQXTJjlDmzFKYdRQkFU06ImJmvBXEU4r9gPEkCN0a/7jLutaU0ZX/AWJN6nGbKnzpQjx5u1u+sqac+jqOqitEL6RMuXju8fODrphtzZIBy2ZVC3wM/Wu43gDT0icAr4RGPPthT15Awf+72tJrQjgcCz1DN8f7Of0BdleaS/UhkpKNIu10i4qSgKTlvFzuZw+llum/mY0undY/NU/Du9G01FsLvNCyHKOS45Qs01z2fGfJYmQINpXlorn+1i/AiHQX1qxftZUhUKob4Xyc+0GZIXeW9gsTqSwy/YNf/7VOgQbq4g+oeT49YtGAR7mM1tedPgR1YEZWwpKvn5aad240WdxUqgW4GQL9cfcwAnSgYmPItM7/QM+LHl+ClzLtuI84H2nf3ulC6CYF334ZJoMWR2uyHnC6RS4Gv9mnYzhBDHqsL+CtbCQeCpl4pAQMJIX+l+dGu4QlkZPj5N5qzgIvDDYJOkSsn5qMQVYmc0CCzzUz0ALDihRu/vacP3d4KzuHk1Xggec+gDb5h1Ou9ZkzfSJ15xZglyRdY8sOnat4cV0WyieuO9iQNxLwIm43w9dqc+UgbowK0bKIGEM5tPP6SmyhnAs6ijhO0dH4qzps1drofOqSjVXvph7rCD4OLNrUZF3qneUYn7m7PlrcKpP8WhkVAO401LeZAY3zraxq4qvmcUPq8slclwa5kRtNO3tSTG2KML2ioTxbQskRC4TL93ZXqyF1SrgUZ0Ovp2H2EQdUG2ZLjIMgcMsQLwhaKrc/J/8+XlS8Ctu9RMpn8+AOfz6rFQqn++iPSKOc4/DO9UPwO0Cc2qpTgp6pNYmV/F21tap2rCtJBsYN1KQrDgKyV8ziRY= X-Forefront-Antispam-Report: CIP:149.199.80.198;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:xir-pvapexch01.xlnx.xilinx.com;PTR:unknown-80-198.xilinx.com;CAT:NONE;SFS:(4636009)(36840700001)(40470700004)(46966006)(2906002)(26005)(356005)(966005)(83380400001)(7696005)(7636003)(9786002)(8936002)(508600001)(6916009)(4326008)(82310400004)(186003)(70206006)(8676002)(30864003)(107886003)(2616005)(6666004)(5660300002)(54906003)(426003)(47076005)(36860700001)(36756003)(70586007)(316002)(1076003)(336012)(40460700003)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2022 21:18:14.3841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52cac653-2b89-441b-74a2-08d9e04832f2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0032.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2583 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1643145542248100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment, Xen is only handling data abort with valid syndrome (i.e. ISV=3D0). Unfortunately, this doesn't cover all the instructions a domain could use to access MMIO regions. For instance, a baremetal OS can use any of the following instructions, whe= re x1 contains the address of the MMIO region: 1. ldr x2, [x1], #8 2. ldr w2, [x1], #-4 3. ldr x2, [x1], #-8 4. ldr w2, [x1], #4 5. ldrh w2, [x1], #2 6. ldrb w2, [x1], #1 7. str x2, [x1], #8 8. str w2, [x1], #-4 9. strh w2, [x1], #2 10. strb w2, [x1], #1 In the following two instructions, Rn could theoretically be stack pointer = which might contain the address of the MMIO region:- 11. ldrb w2, [Rn], #1 12. ldrb wzr, [Rn], #1 In order to handle post-indexing store/load instructions (like those mentio= ned above), Xen will need to fetch and decode the instruction. This patch only cover post-index store/load instructions from AArch64 mode. For now, this is left unimplemented for trap from AArch32 mode. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changelog :- v2 - 1. Updated the rn register after reading from it. (Pointed by Julien, Stefano) 2. Used a union to represent the instruction opcode (Suggestd by Bertr= and) 3. Fixed coding style issues (Pointed by Julien) 4. In the previous patch, I was updating dabt->sign based on the signe= dness of imm9. This was incorrect. As mentioned in ARMv8 ARM DDI 0487G.b, Page 3221, SSE indicates the signedness of the data item loaded. In= our case, the data item loaded is always unsigned. v3- 1. Handled all the variants of ldr/str (ie 64, 32, 16, 8 bit variants). Thus, I have removed the check for "instr->code.opc =3D=3D 0" (Sugge= sted by Andre) 2. Handled the scenario when rn =3D SP, rt =3D XZR (Suggested by Jan, A= ndre) 3. Added restriction for "rt !=3D rn" (Suggested by Andre) 4. Moved union ldr_str_instr_class {} to decode.h. This is the header i= ncluded by io.c and decode.c (where the union is referred). (Suggested by Ja= n) 5. Indentation and typo fixes (Suggested by Jan) v4- 1. Fixed the patch as per Stefano's comments on v3. They are as follows= :- 1.1 Use macros to determine the fixed values in the instruction opc= ode 1.2 Checked if instr !=3D NULL 1.3 Changed some data types and added #define ARM_64 for AArch64 sp= ecific code=20 1.4 Moved post_increment_register() to decode.c so that the decoding logic is confined to a single file. 1.5 Moved some checks from post_increment_register() to decode_loadstore_postindexing() 1.6 Removed a duplicate check 2. Updated the commit message as per Andre's comments. 3. Changed the names of a label and some comments. *32bit* was erroneou= sly mentioned in a label and comments in decode_loadstore_postindexing() although the function handled all variants of ldr/str post indexing. xen/arch/arm/decode.c | 124 +++++++++++++++++++++++++++++++++++++++++- xen/arch/arm/decode.h | 41 +++++++++++++- xen/arch/arm/io.c | 41 +++++++++++--- 3 files changed, 195 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 792c2e92a7..0c12af7afa 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -84,6 +84,101 @@ bad_thumb2: return 1; } =20 +static int decode_loadstore_postindexing(register_t pc, + struct hsr_dabt *dabt, + union ldr_str_instr_class *instr) +{ + struct cpu_user_regs *regs =3D guest_cpu_user_regs(); + + if ( instr =3D=3D NULL ) + { + gprintk(XENLOG_ERR, "instr should not be NULL\n"); + return -EINVAL; + } + + if ( raw_copy_from_guest(&instr->value, (void * __user)pc, sizeof (ins= tr)) ) + { + gprintk(XENLOG_ERR, "Could not copy the instruction from PC\n"); + return -EFAULT; + } + + /* + * Rn -ne Rt for ldr/str instruction. + * Check https://developer.arm.com/documentation/dui0802/a/CIHGJHED + * (Register restrictions) + * + * The only exception for this is when rn =3D 31. It denotes SP ("Use = of SP") + * + * And when rt =3D 31, it denotes wzr/xzr. (Refer + * https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/A= Arch64-special-registers + * "There is no register called X31 or W31. Many instructions are enco= ded + * such that the number 31 represents the zero register, ZR (WZR/XZR)." + */ + if ( (instr->code.rn =3D=3D instr->code.rt) && (instr->code.rn !=3D 31= ) ) + { + gprintk(XENLOG_ERR, "Rn should not be equal to Rt except for r31\n= "); + return -EINVAL; + } + + /* First, let's check for the fixed values */ + if ( (instr->value & POST_INDEX_FIXED_MASK) !=3D POST_INDEX_FIXED_VALU= E ) + { + gprintk(XENLOG_ERR, "Cannot decode instruction 0x%x",instr->value); + gprintk(XENLOG_ERR, "Decoding not supported for instructions other= than" + " ldr/str post indexing\n"); + goto bad_loadstore; + } + + /* + * Handle when rn =3D SP + * Refer ArmV8 ARM DDI 0487G.b, Page - D1-2463 "Stack pointer register= selection" + * As we are interested in handling exceptions only from EL1 in AArch6= 4 state, + * thus M[3:0] =3D=3D EL1h (Page - C5-480 "When exception taken from A= Arch64 state:") + */ + if ( (instr->code.rn =3D=3D 31) && ((regs->cpsr & PSR_MODE_MASK) !=3D = PSR_MODE_EL1h) ) + { + gprintk(XENLOG_ERR, "SP is valid only for EL1h\n"); + goto bad_loadstore; + } + + if ( instr->code.v !=3D 0 ) + { + gprintk(XENLOG_ERR, + "ldr/str post indexing for vector types are not supported\n"); + goto bad_loadstore; + } + + /* Check for STR (immediate) */ + if ( instr->code.opc =3D=3D 0 ) + { + dabt->write =3D 1; + } + /* Check for LDR (immediate) */ + else if ( instr->code.opc =3D=3D 1 ) + { + dabt->write =3D 0; + } + else + { + gprintk(XENLOG_ERR, + "Decoding ldr/str post indexing is not supported for this vari= ant\n"); + goto bad_loadstore; + } + + gprintk(XENLOG_INFO, + "instr->code.rt =3D 0x%x, instr->code.size =3D 0x%x, instr->code.i= mm9 =3D %d\n", + instr->code.rt, instr->code.size, instr->code.imm9); + + update_dabt(dabt, instr->code.rt, instr->code.size, false); + dabt->valid =3D 1; + + return 0; + + bad_loadstore: + gprintk(XENLOG_ERR, "unhandled Arm instruction 0x%x\n", instr->value); + return 1; +} + static int decode_thumb(register_t pc, struct hsr_dabt *dabt) { uint16_t instr; @@ -150,17 +245,44 @@ bad_thumb: return 1; } =20 -int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt) +int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt, + union ldr_str_instr_class *instr) { if ( is_32bit_domain(current->domain) && regs->cpsr & PSR_THUMB ) return decode_thumb(regs->pc, dabt); =20 + if ( (is_64bit_domain(current->domain) && !psr_mode_is_32bit(regs)) ) + { + return decode_loadstore_postindexing(regs->pc, dabt, instr); + } + /* TODO: Handle ARM instruction */ gprintk(XENLOG_ERR, "unhandled ARM instruction\n"); =20 return 1; } =20 +#if CONFIG_ARM_64 +void post_increment_register(union ldr_str_instr_class *instr) +{ + struct cpu_user_regs *regs =3D guest_cpu_user_regs(); + register_t val; + + /* handle when rn =3D SP */ + if ( instr->code.rn =3D=3D 31 ) + val =3D regs->sp_el1; + else + val =3D get_user_reg(regs, instr->code.rn); + + val +=3D instr->code.imm9; + + if ( instr->code.rn =3D=3D 31 ) + regs->sp_el1 =3D val; + else + set_user_reg(regs, instr->code.rn, val); +} +#endif + /* * Local variables: * mode: C diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index 4613763bdb..511cd4a05f 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -23,6 +23,35 @@ #include #include =20 +/* + * Refer to the ARMv8 ARM (DDI 0487G.b), Section C4.1.4 Loads and Stores + * Page 318 specifies the following bit pattern for + * "load/store register (immediate post-indexed)". + * + * 31 30 29 27 26 25 23 21 20 11 9 4 0 + * ___________________________________________________________________ + * |size|1 1 1 |V |0 0 |opc |0 | imm9 |0 1 | Rn | Rt | + * |____|______|__|____|____|__|_______________|____|_________|_______| + */ +union ldr_str_instr_class { + uint32_t value; + struct ldr_str { + unsigned int rt:5; /* Rt register */ + unsigned int rn:5; /* Rn register */ + unsigned int fixed1:2; /* value =3D=3D 01b */ + signed int imm9:9; /* imm9 */ + unsigned int fixed2:1; /* value =3D=3D 0b */ + unsigned int opc:2; /* opc */ + unsigned int fixed3:2; /* value =3D=3D 00b */ + unsigned int v:1; /* vector */ + unsigned int fixed4:3; /* value =3D=3D 111b */ + unsigned int size:2; /* size */ + } code; +}; + +#define POST_INDEX_FIXED_MASK 0x3B200C00 +#define POST_INDEX_FIXED_VALUE 0x38000400 + /** * Decode an instruction from pc * /!\ This function is not intended to fully decode an instruction. It @@ -35,8 +64,18 @@ */ =20 int decode_instruction(const struct cpu_user_regs *regs, - struct hsr_dabt *dabt); + struct hsr_dabt *dabt, + union ldr_str_instr_class *instr); =20 +/** + * Update the register value for Rn + * /!\ This function is used to update the register value for Rn when a + * post indexing ldr/str instruction is decoded. + * + * This function will get: + * - The post indexing ldr/str instruction opcode + */ +void post_increment_register(union ldr_str_instr_class *instr); #endif /* __ARCH_ARM_DECODE_H_ */ =20 /* diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 729287e37c..b9c15e1fe7 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -106,14 +106,29 @@ enum io_state try_handle_mmio(struct cpu_user_regs *r= egs, .gpa =3D gpa, .dabt =3D dabt }; + int rc; + union ldr_str_instr_class instr =3D {0}; =20 ASSERT(hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); =20 + /* + * Armv8 processor does not provide a valid syndrome for post-indexing + * ldr/str instructions. So in order to process these instructions, + * Xen must decode them. + */ + if ( !info.dabt.valid ) + { + rc =3D decode_instruction(regs, &info.dabt, &instr); + if ( rc ) + { + gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); + return IO_ABORT; + } + } + handler =3D find_mmio_handler(v->domain, info.gpa); if ( !handler ) { - int rc; - rc =3D try_fwd_ioserv(regs, v, &info); if ( rc =3D=3D IO_HANDLED ) return handle_ioserv(regs, v); @@ -121,10 +136,6 @@ enum io_state try_handle_mmio(struct cpu_user_regs *re= gs, return rc; } =20 - /* All the instructions used on emulated MMIO region should be valid */ - if ( !dabt.valid ) - return IO_ABORT; - /* * Erratum 766422: Thumb store translation fault to Hypervisor may * not have correct HSR Rt value. @@ -134,7 +145,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, { int rc; =20 - rc =3D decode_instruction(regs, &info.dabt); + rc =3D decode_instruction(regs, &info.dabt, NULL); if ( rc ) { gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); @@ -143,9 +154,21 @@ enum io_state try_handle_mmio(struct cpu_user_regs *re= gs, } =20 if ( info.dabt.write ) - return handle_write(handler, v, &info); + rc =3D handle_write(handler, v, &info); else - return handle_read(handler, v, &info); + rc =3D handle_read(handler, v, &info); + +#if CONFIG_ARM_64 + if ( (is_64bit_domain(current->domain) && !psr_mode_is_32bit(regs)) ) + { + if ( instr.value !=3D 0 ) + { + post_increment_register(&instr); + } + } +#endif + + return rc; } =20 void register_mmio_handler(struct domain *d, --=20 2.17.1