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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch02.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , , , , "Ayan Kumar Halder" Subject: [XEN v3] xen/arm64: io: Decode ldr/str post-indexing instructions Date: Thu, 20 Jan 2022 21:55:27 +0000 Message-ID: <20220120215527.28138-1-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 29d8353d-22dd-4abc-3d30-08d9dc5f97d5 X-MS-TrafficTypeDiagnostic: CO6PR02MB8820:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BheGQWmeefeIopGz3xmde/ww5DC4a/apJWFELGyWIqyyYYIKeGEPmJFU01lppfD1iOcFR/D+ZGrLEhfNU7iu+s1kgR6173T8PzWyOsvmeoGu3pnODoiyhkywq8J/m+szsqA1iQjO5OwtlfSP2BCjg2ztEm/1scH8lMCrk+gVKG/jtiXC0EpthsakOIXYHL0+zTV7sXt968n71YlOCsT1kSBd9SePhaDWiQJ/5b26ssJm3I3gxejKZC4dfSjW9azBy4V1ChJGTQVAJUBthNDdWIjUHM3ZezkqN2IXBkokVZ2BkPJiD6xCeNy36XcV+tmGqhfHHmE8+0aLrkhOwCb7WNg318/OAJQ4k5crT1AmhXC7zTioxUCrT17jreM2kEXU+fhAPp0ZPWPXZhpCljPOjC0kKbXZzru6q2IL1sZd2mIa49I1HxuIOVRr/UQnzB7FDmFJliDuH65LGK0U25wll5fBloeGGQuPCSC2sAg55T4jLpybGaTR4qAg9+NZ9oz2MkdwwKEjdoW4lj4/Y0HbYRcI+KhTJzDv+vNPhZIBse6v404Ved1olVxKd5FmOQ45MibaLnF1OIW5r1gvULaAXlVVc6F/HFn/xTuRAk17zU6HNphTjuUxOU1pgIYH5xo+DAnciyBQfIJyiHv1O5dbkdpL8QJ/9a6xcLN/eILfgnVX6mFrnC9HiwYik/MT5dwlkK+VHyLsmiK9LY9PeSAcaB8i+OKgHESNGX7P1R5Lro+Ct/yQU/ZQ7kdV7rSQ/FrOW7f4XZMI5MhetwvrL2eWng6JxUMHj1UPYNQd5edr+e0bU9KwNiJDYZlcfmZRn3L+LPVAz+b8rF+xtBcjT25YIXFEiOGgI3aKe37kl37lHCA= X-Forefront-Antispam-Report: CIP:149.199.80.198;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:xir-pvapexch02.xlnx.xilinx.com;PTR:unknown-80-198.xilinx.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(6916009)(26005)(8936002)(107886003)(7696005)(9786002)(70206006)(508600001)(336012)(5660300002)(6666004)(966005)(186003)(2616005)(4326008)(7636003)(82310400004)(2906002)(356005)(36756003)(8676002)(316002)(1076003)(54906003)(36860700001)(70586007)(47076005)(83380400001)(426003)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2022 21:55:37.4943 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29d8353d-22dd-4abc-3d30-08d9dc5f97d5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT027.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR02MB8820 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1642715794799100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment, Xen is only handling data abort with valid syndrome (i.e. ISV=3D0). Unfortunately, this doesn't cover all the instructions a domain could use to access MMIO regions. For instance, a baremetal OS can use any of the following instructions, whe= re x1 contains the address of the MMIO region: 1. ldr x2, [x1], #4 2. ldr w2, [x1], #-4 3. ldr x2, [x1], #-8 4. ldr w2, [x1], #4 5. ldrh w2, [x1], #8 6. ldrb w2, [x1], #16 7. str x2, [x1], #4 8. str w2, [x1], #-4 9. strh w2, [x1], #8 10. strb w2, [x1], #16 In the following two instructions, sp contains the address of the MMIO regi= on:- 11. ldrb w2, [sp], #16 12. ldrb wzr, [sp], #16 In order to handle post-indexing store/load instructions (like those mentio= ned above), Xen will need to fetch and decode the instruction. This patch only cover post-index store/load instructions from AArch64 mode. For now, this is left unimplemented for trap from AArch32 mode. Signed-off-by: Ayan Kumar Halder --- Changelog :- v2 - 1. Updated the rn register after reading from it. (Pointed by Julien, Stefano) 2. Used a union to represent the instruction opcode (Suggestd by Bertr= and) 3. Fixed coding style issues (Pointed by Julien) 4. In the previous patch, I was updating dabt->sign based on the signe= dness of imm9. This was incorrect. As mentioned in ARMv8 ARM DDI 0487G.b, Page 3221, SSE indicates the signedness of the data item loaded. In= our case, the data item loaded is always unsigned. v3- 1. Handled all the variants of ldr/str (ie 64, 32, 16, 8 bit variants). Thus, I have removed the check for "instr->code.opc =3D=3D 0" (Sugge= sted by Andre) 2. Handled the scenario when rn =3D SP, rt =3D XZR (Suggested by Jan, A= ndre) 3. Added restriction for "rt !=3D rn" (Suggested by Andre) 4. Moved union ldr_str_instr_class {} to decode.h. This is the header i= ncluded by io.c and decode.c (where the union is referred). (Suggested by Ja= n) 5. Indentation and typo fixes (Suggested by Jan) Changes suggested but could not be considered due to reasons :- 1. Using accessor macros instead of bitfields for "ldr_str_instr_class"= . (Andre) Reason - I could not find a simple way to represent 9 bit signed int= eger (ie imm9) without using bitfields. If I use accessor macros, then I = need to manually calculate two's complement to obtain the value when sign= ed bit is present. 2. I/D cache cohenerncy (Andre) Reason :- I could not see any instruction to flush the I cache. Refer https://developer.arm.com/documentation/ddi0596/2021-12/Base-I= nstructions/IC--Instruction-Cache-operation--an-alias-of-SYS-?lang=3Den#sa_= ic_op So, this patch assumes that the I/D caches are coherent. xen/arch/arm/decode.c | 78 ++++++++++++++++++++++++++++++++++++++++++- xen/arch/arm/decode.h | 29 +++++++++++++++- xen/arch/arm/io.c | 66 ++++++++++++++++++++++++++++++++---- 3 files changed, 165 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 792c2e92a7..f1c59ddd1a 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -84,6 +84,76 @@ bad_thumb2: return 1; } =20 +static int decode_loadstore_postindexing(register_t pc, + struct hsr_dabt *dabt, + union ldr_str_instr_class *instr) +{ + if ( raw_copy_from_guest(&instr->value, (void * __user)pc, sizeof (ins= tr)) ) + return -EFAULT; + + /* + * Rn -ne Rt for ldr/str instruction. + * Check https://developer.arm.com/documentation/dui0802/a/CIHGJHED + * (Register restrictions) + * + * The only exception for this is when rn =3D 31. It denotes SP ("Use = of SP") + * + * And when rt =3D 31, it denotes wzr/xzr. (Refer + * https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/A= Arch64-special-registers + * "There is no register called X31 or W31. Many instructions are enco= ded + * such that the number 31 represents the zero register, ZR (WZR/XZR)." + */ + if ( (instr->code.rn =3D=3D instr->code.rt) && (instr->code.rn !=3D 31= ) ) + return -EINVAL; + + /* First, let's check for the fixed values */ + if ( !((instr->code.fixed1 =3D=3D 1) && (instr->code.fixed2 =3D=3D 0) = && + (instr->code.fixed3 =3D=3D 0) && (instr->code.fixed4 =3D=3D 7)) ) + { + gprintk(XENLOG_ERR, "Cannot decode instruction 0x%x",instr->value); + gprintk(XENLOG_ERR, "Decoding not supported for instructions other= than" + " ldr/str post indexing\n"); + goto bad_32bit_loadstore; + } + + if ( instr->code.v !=3D 0 ) + { + gprintk(XENLOG_ERR, + "ldr/str post indexing for vector types are not supported\n"); + goto bad_32bit_loadstore; + } + + /* Check for STR (immediate) - 32 bit variant */ + if ( instr->code.opc =3D=3D 0 ) + { + dabt->write =3D 1; + } + /* Check for LDR (immediate) - 32 bit variant */ + else if ( instr->code.opc =3D=3D 1 ) + { + dabt->write =3D 0; + } + else + { + gprintk(XENLOG_ERR, + "Decoding ldr/str post indexing is not supported for this vari= ant\n"); + goto bad_32bit_loadstore; + } + + gprintk(XENLOG_INFO, + "instr->code.rt =3D 0x%x, instr->code.size =3D 0x%x, instr->code.i= mm9 =3D %d\n", + instr->code.rt, instr->code.size, instr->code.imm9); + + update_dabt(dabt, instr->code.rt, instr->code.size, false); + dabt->valid =3D 1; + + return 0; + + bad_32bit_loadstore: + gprintk(XENLOG_ERR, "unhandled 32bit Arm instruction 0x%x\n", instr->v= alue); + return 1; +} + static int decode_thumb(register_t pc, struct hsr_dabt *dabt) { uint16_t instr; @@ -150,11 +220,17 @@ bad_thumb: return 1; } =20 -int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt) +int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt, + union ldr_str_instr_class *instr) { if ( is_32bit_domain(current->domain) && regs->cpsr & PSR_THUMB ) return decode_thumb(regs->pc, dabt); =20 + if ( (is_64bit_domain(current->domain) && !psr_mode_is_32bit(regs)) ) + { + return decode_loadstore_postindexing(regs->pc, dabt, instr); + } + /* TODO: Handle ARM instruction */ gprintk(XENLOG_ERR, "unhandled ARM instruction\n"); =20 diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index 4613763bdb..5c918c9bed 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -23,6 +23,32 @@ #include #include =20 +/* + * Refer to the ARMv8 ARM (DDI 0487G.b), Section C4.1.4 Loads and Stores + * Page 318 specifies the following bit pattern for + * "load/store register (immediate post-indexed)". + * + * 31 30 29 27 26 25 23 21 20 11 9 4 0 + * ___________________________________________________________________ + * |size|1 1 1 |V |0 0 |opc |0 | imm9 |0 1 | Rn | Rt | + * |____|______|__|____|____|__|_______________|____|_________|_______| + */ +union ldr_str_instr_class { + uint32_t value; + struct ldr_str { + unsigned int rt:5; /* Rt register */ + unsigned int rn:5; /* Rn register */ + unsigned int fixed1:2; /* value =3D=3D 01b */ + signed int imm9:9; /* imm9 */ + unsigned int fixed2:1; /* value =3D=3D 0b */ + unsigned int opc:2; /* opc */ + unsigned int fixed3:2; /* value =3D=3D 00b */ + unsigned int v:1; /* vector */ + unsigned int fixed4:3; /* value =3D=3D 111b */ + unsigned int size:2; /* size */ + } code; +}; + /** * Decode an instruction from pc * /!\ This function is not intended to fully decode an instruction. It @@ -35,7 +61,8 @@ */ =20 int decode_instruction(const struct cpu_user_regs *regs, - struct hsr_dabt *dabt); + struct hsr_dabt *dabt, + union ldr_str_instr_class *instr); =20 #endif /* __ARCH_ARM_DECODE_H_ */ =20 diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 729287e37c..acb483f235 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -65,6 +65,39 @@ static enum io_state handle_write(const struct mmio_hand= ler *handler, return ret ? IO_HANDLED : IO_ABORT; } =20 +static void post_increment_register(union ldr_str_instr_class *instr) +{ + struct cpu_user_regs *regs =3D guest_cpu_user_regs(); + unsigned int val; + + /* handle when rn =3D SP */ + if ( instr->code.rn =3D=3D 31 ) + { + if ( (regs->cpsr & PSR_MODE_MASK) =3D=3D PSR_MODE_EL1h ) + { + val =3D regs->sp_el1; + } + else + { + BUG(); + } + } + else + { + val =3D get_user_reg(regs, instr->code.rn); + } + val +=3D instr->code.imm9; + + if ( instr->code.rn =3D=3D 31 ) + { + regs->sp_el1 =3D val; + } + else + { + set_user_reg(regs, instr->code.rn, val); + } +} + /* This function assumes that mmio regions are not overlapped */ static int cmp_mmio_handler(const void *key, const void *elem) { @@ -106,14 +139,29 @@ enum io_state try_handle_mmio(struct cpu_user_regs *r= egs, .gpa =3D gpa, .dabt =3D dabt }; + int rc; + union ldr_str_instr_class instr =3D {0}; =20 ASSERT(hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); =20 + /* + * Armv8 processor does not provide a valid syndrome for post-indexing + * ldr/str instructions. So in order to process these instructions, + * Xen must decode them. + */ + if ( !info.dabt.valid ) + { + rc =3D decode_instruction(regs, &info.dabt, &instr); + if ( rc ) + { + gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); + return IO_ABORT; + } + } + handler =3D find_mmio_handler(v->domain, info.gpa); if ( !handler ) { - int rc; - rc =3D try_fwd_ioserv(regs, v, &info); if ( rc =3D=3D IO_HANDLED ) return handle_ioserv(regs, v); @@ -122,7 +170,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, } =20 /* All the instructions used on emulated MMIO region should be valid */ - if ( !dabt.valid ) + if ( !info.dabt.valid ) return IO_ABORT; =20 /* @@ -134,7 +182,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, { int rc; =20 - rc =3D decode_instruction(regs, &info.dabt); + rc =3D decode_instruction(regs, &info.dabt, NULL); if ( rc ) { gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); @@ -143,9 +191,15 @@ enum io_state try_handle_mmio(struct cpu_user_regs *re= gs, } =20 if ( info.dabt.write ) - return handle_write(handler, v, &info); + rc =3D handle_write(handler, v, &info); else - return handle_read(handler, v, &info); + rc =3D handle_read(handler, v, &info); + + if ( instr.value !=3D 0 ) + { + post_increment_register(&instr); + } + return rc; } =20 void register_mmio_handler(struct domain *d, --=20 2.17.1