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d="scan'208";a="62573949" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 2/4] x86/msr: Split MSR_SPEC_CTRL handling Date: Mon, 17 Jan 2022 18:34:13 +0000 Message-ID: <20220117183415.11150-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20220117183415.11150-1-andrew.cooper3@citrix.com> References: <20220117183415.11150-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1642444536186100002 In order to fix a VT-x bug, and support MSR_SPEC_CTRL on AMD, move MSR_SPEC_CTRL handling into the new {get,set}_reg() infrastructure. Duplicate the msrs->spec_ctrl.raw accesses in the PV and VT-x paths for now. The SVM path is currently unreachable because of the CPUID policy. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu v2: * Rework on top of {get,set}_reg() --- xen/arch/x86/hvm/vmx/vmx.c | 7 +++++++ xen/arch/x86/msr.c | 21 +++++++++++++++++---- xen/arch/x86/pv/emulate.c | 9 +++++++++ 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 4ff92ab4e94e..c32967f190ff 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2410,6 +2410,9 @@ static uint64_t vmx_get_reg(struct vcpu *v, unsigned = int reg) =20 switch ( reg ) { + case MSR_SPEC_CTRL: + return v->arch.msrs->spec_ctrl.raw; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x) Bad register\n", __func__, v, reg); @@ -2424,6 +2427,10 @@ static void vmx_set_reg(struct vcpu *v, unsigned int= reg, uint64_t val) =20 switch ( reg ) { + case MSR_SPEC_CTRL: + v->arch.msrs->spec_ctrl.raw =3D val; + break; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x, 0x%016"PRIx64") Bad register\= n", __func__, v, reg, val); diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index b834456c7b02..fd4012808472 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -28,6 +28,7 @@ #include #include #include +#include #include =20 #include @@ -265,8 +266,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_SPEC_CTRL: if ( !cp->feat.ibrsb ) goto gp_fault; - *val =3D msrs->spec_ctrl.raw; - break; + goto get_reg; =20 case MSR_INTEL_PLATFORM_INFO: *val =3D mp->platform_info.raw; @@ -424,6 +424,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t= *val) =20 return ret; =20 + get_reg: /* Delegate register access to per-vm-type logic. */ + if ( is_pv_domain(d) ) + *val =3D pv_get_reg(v, msr); + else + *val =3D hvm_get_reg(v, msr); + return X86EMUL_OKAY; + gp_fault: return X86EMUL_EXCEPTION; } @@ -514,8 +521,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) if ( val & rsvd ) goto gp_fault; /* Rsvd bit set? */ =20 - msrs->spec_ctrl.raw =3D val; - break; + goto set_reg; =20 case MSR_PRED_CMD: if ( !cp->feat.ibrsb && !cp->extd.ibpb ) @@ -663,6 +669,13 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t= val) =20 return ret; =20 + set_reg: /* Delegate register access to per-vm-type logic. */ + if ( is_pv_domain(d) ) + pv_set_reg(v, msr, val); + else + hvm_set_reg(v, msr, val); + return X86EMUL_OKAY; + gp_fault: return X86EMUL_EXCEPTION; } diff --git a/xen/arch/x86/pv/emulate.c b/xen/arch/x86/pv/emulate.c index ae049b60f2fc..0a7907ec5e84 100644 --- a/xen/arch/x86/pv/emulate.c +++ b/xen/arch/x86/pv/emulate.c @@ -92,12 +92,16 @@ void pv_emul_instruction_done(struct cpu_user_regs *reg= s, unsigned long rip) =20 uint64_t pv_get_reg(struct vcpu *v, unsigned int reg) { + const struct vcpu_msrs *msrs =3D v->arch.msrs; struct domain *d =3D v->domain; =20 ASSERT(v =3D=3D current || !vcpu_runnable(v)); =20 switch ( reg ) { + case MSR_SPEC_CTRL: + return msrs->spec_ctrl.raw; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x) Bad register\n", __func__, v, reg); @@ -108,12 +112,17 @@ uint64_t pv_get_reg(struct vcpu *v, unsigned int reg) =20 void pv_set_reg(struct vcpu *v, unsigned int reg, uint64_t val) { + struct vcpu_msrs *msrs =3D v->arch.msrs; struct domain *d =3D v->domain; =20 ASSERT(v =3D=3D current || !vcpu_runnable(v)); =20 switch ( reg ) { + case MSR_SPEC_CTRL: + msrs->spec_ctrl.raw =3D val; + break; + default: printk(XENLOG_G_ERR "%s(%pv, 0x%08x, 0x%016"PRIx64") Bad register\= n", __func__, v, reg, val); --=20 2.11.0