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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 01/11] xen: introduce internal CDF_xxx flags for domain creation Date: Mon, 20 Dec 2021 05:21:13 +0000 Message-ID: <20211220052123.969876-2-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 08bb28af-c0da-43d2-bf6b-08d9c378a0a5 X-MS-TrafficTypeDiagnostic: AM0PR08MB5171:EE_|VE1EUR03FT010:EE_|AM0PR08MB3556:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:1051;OLM:1051; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Rj+kn3NOwfWJBF/+eC3AcCvxedWz9G30IUXa6w3xkEPQ7I0ptTxdUWvjtXEu/qgzto29IGzVTiufuqANNRILHdycHd9eYKad7udSNqQ99hUI+i9LuMvnxjk6H8ybnoNJrKkRyznFR3gZJVIljqvUfr0o4cBJ2vjWqoksE9ONGD8tFO+hcWbg4j/Get92NJePNOkmeWH4ZEJFM1UaP9iLa4fXqYAsEmi4CCykP0hcrLnQm/3EbWVOyOSr/kZhzRItkMVIJmwkdCHyL9dxsuN3q4LUpBQsElZy82WHULB3zdzAp/UvtVa/BdnOAypq1Qu5kGPdB17j11rKCQhqwzRzSkGw5f+7EFjQlw1fC40cfR896vPylXcv4YiHWUYaGBjy4n08wUBWB/wBAs/r2gAMjTS0fohge0691sQMyjkCi1HdWJ2+rzygfGGl0e+65FhW3gO9ZPLXADfH1yx66ha3PnnVpgMTm/1L4Gn9s4RBO9qs4/14ZMKA1uoqPncfIudRpycsLsBRpkRWcAFpWh1JueNgaUIeivKpmnxoXeXlU/rRC0yiK9v7BuQPUZtdiECm404G8ucZj4LNtNp6dBEKHb0dYrbXbT6xgT5QEIHDcIh19PkOAoMZ3Qj7WUxcaL744dRTUxI0HYDDpqydch2Ly30UGeUhDsN8l+8Y2BJcktApNtDRe/fwHwDNvsEEvmLWQwojln+Rl5dWKuHIoi8ytUngc5w7JeikiGEXEeBZ2T4CHvu4vXzJ6zdHVRKvg25olsNNW1xNHTolrc+OAeWFgch2qvaGA7LF+aY7UObOyc+j8U4Jv7dC0zAwRlFEqvBm X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(36756003)(1076003)(36860700001)(2906002)(47076005)(81166007)(2616005)(44832011)(86362001)(83380400001)(356005)(5660300002)(54906003)(426003)(82310400004)(336012)(186003)(110136005)(4326008)(8676002)(8936002)(26005)(316002)(70586007)(7696005)(70206006)(40460700001)(6666004)(508600001)(21314003)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:21:50.7266 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08bb28af-c0da-43d2-bf6b-08d9c378a0a5 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT010.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB3556 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977766006100004 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini We are passing an internal-only boolean flag at domain creation to specify whether we want the domain to be privileged (i.e. dom0) or not. Another flag will be introduced later in this series. This commit extends original "boolean" to an "unsigned int" covering both the existing "is_priv" and our new "directmap", which will be introduced la= ter. To make visible the relationship, we name the respective constants CDF_xxx (with no XEN_DOMCTL_ prefix) to represent the difference with the public constants XEN_DOMCTL_CDF_xxx. Allocate bit 0 as CDF_privileged: whether a domain is privileged or not. Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng Reviewed-by: Jan Beulich --- v4 changes: - new commit --- xen/arch/arm/domain_build.c | 4 ++-- xen/arch/x86/setup.c | 2 +- xen/common/domain.c | 10 +++++----- xen/common/sched/core.c | 2 +- xen/include/xen/domain.h | 4 ++++ xen/include/xen/sched.h | 2 +- 6 files changed, 14 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 6931c022a2..0fab8604de 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -3058,7 +3058,7 @@ void __init create_domUs(void) * very important to use the pre-increment operator to call * domain_create() with a domid > 0. (domid =3D=3D 0 is reserved f= or Dom0) */ - d =3D domain_create(++max_init_domid, &d_cfg, false); + d =3D domain_create(++max_init_domid, &d_cfg, 0); if ( IS_ERR(d) ) panic("Error creating domain %s\n", dt_node_name(node)); =20 @@ -3160,7 +3160,7 @@ void __init create_dom0(void) if ( iommu_enabled ) dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu; =20 - dom0 =3D domain_create(0, &dom0_cfg, true); + dom0 =3D domain_create(0, &dom0_cfg, CDF_privileged); if ( IS_ERR(dom0) || (alloc_dom0_vcpu0(dom0) =3D=3D NULL) ) panic("Error creating domain 0\n"); =20 diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index e716005145..a14271488c 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -789,7 +789,7 @@ static struct domain *__init create_dom0(const module_t= *image, =20 /* Create initial domain. Not d0 for pvshim. */ domid =3D get_initial_domain_id(); - d =3D domain_create(domid, &dom0_cfg, !pv_shim); + d =3D domain_create(domid, &dom0_cfg, pv_shim ? 0 : CDF_privileged); if ( IS_ERR(d) ) panic("Error creating d%u: %ld\n", domid, PTR_ERR(d)); =20 diff --git a/xen/common/domain.c b/xen/common/domain.c index 2048ebad86..023c89c0ea 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -552,7 +552,7 @@ static int sanitise_domain_config(struct xen_domctl_cre= atedomain *config) =20 struct domain *domain_create(domid_t domid, struct xen_domctl_createdomain *config, - bool is_priv) + const unsigned int flags) { struct domain *d, **pd, *old_hwdom =3D NULL; enum { INIT_watchdog =3D 1u<<1, @@ -578,7 +578,7 @@ struct domain *domain_create(domid_t domid, } =20 /* Sort out our idea of is_control_domain(). */ - d->is_privileged =3D is_priv; + d->is_privileged =3D flags & CDF_privileged; =20 /* Sort out our idea of is_hardware_domain(). */ if ( domid =3D=3D 0 || domid =3D=3D hardware_domid ) @@ -772,7 +772,7 @@ void __init setup_system_domains(void) * Hidden PCI devices will also be associated with this domain * (but be [partly] controlled by Dom0 nevertheless). */ - dom_xen =3D domain_create(DOMID_XEN, NULL, false); + dom_xen =3D domain_create(DOMID_XEN, NULL, 0); if ( IS_ERR(dom_xen) ) panic("Failed to create d[XEN]: %ld\n", PTR_ERR(dom_xen)); =20 @@ -782,7 +782,7 @@ void __init setup_system_domains(void) * array. Mappings occur at the priv of the caller. * Quarantined PCI devices will be associated with this domain. */ - dom_io =3D domain_create(DOMID_IO, NULL, false); + dom_io =3D domain_create(DOMID_IO, NULL, 0); if ( IS_ERR(dom_io) ) panic("Failed to create d[IO]: %ld\n", PTR_ERR(dom_io)); =20 @@ -791,7 +791,7 @@ void __init setup_system_domains(void) * Initialise our COW domain. * This domain owns sharable pages. */ - dom_cow =3D domain_create(DOMID_COW, NULL, false); + dom_cow =3D domain_create(DOMID_COW, NULL, 0); if ( IS_ERR(dom_cow) ) panic("Failed to create d[COW]: %ld\n", PTR_ERR(dom_cow)); #endif diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index 8f4b1ca10d..f5c819349b 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -3021,7 +3021,7 @@ void __init scheduler_init(void) sched_ratelimit_us =3D SCHED_DEFAULT_RATELIMIT_US; } =20 - idle_domain =3D domain_create(DOMID_IDLE, NULL, false); + idle_domain =3D domain_create(DOMID_IDLE, NULL, 0); BUG_ON(IS_ERR(idle_domain)); BUG_ON(nr_cpu_ids > ARRAY_SIZE(idle_vcpu)); idle_domain->vcpu =3D idle_vcpu; diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 160c8dbdab..cfb0b47f13 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -28,6 +28,10 @@ void getdomaininfo(struct domain *d, struct xen_domctl_g= etdomaininfo *info); void arch_get_domain_info(const struct domain *d, struct xen_domctl_getdomaininfo *info); =20 +/* CDF_* constant. Internal flags for domain creation. */ +/* Is this a privileged domain? */ +#define CDF_privileged (1U << 0) + /* * Arch-specifics. */ diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 37f78cc4c4..972877bc28 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -665,7 +665,7 @@ int arch_sanitise_domain_config(struct xen_domctl_creat= edomain *config); */ struct domain *domain_create(domid_t domid, struct xen_domctl_createdomain *config, - bool is_priv); + const unsigned int flags); =20 /* * rcu_lock_domain_by_id() is more efficient than get_domain_by_id(). --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=2; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:21:52.6208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24063700-3c33-4182-a20f-08d9c378a1c4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT058.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5711 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977766019100008 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini This commit introduces a new arm-specific flag CDF_directmap to specify that a domain should have its memory direct-map(guest physical address =3D=3D physical address) at domain creation. Also, add a directmap flag under struct arch_domain and use it to reimplement is_domain_direct_mapped. For now, direct-map is only available when statically allocated memory is used for the domain, that is, "xen,static-mem" must be also defined in the domain configuration. Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng Acked-by: Jan Beulich --- v2 changes - remove the introduce of internal flag - remove flag direct_map since we already store this flag in d->options - Refine is_domain_direct_mapped to check whether the flag XEN_DOMCTL_CDF_directmap is set - reword "1:1 direct-map" to just "direct-map" --- v3 changes - move flag back to xen/include/xen/domain.h, to let it be only available f= or domain created by XEN. - name it with extra "INTERNAL" and add comments to warn developers not to accidently use its bitfield when introducing new XEN_DOMCTL_CDF_xxx flag. - reject this flag in x86'es arch_sanitise_domain_config() --- v4 changes - introduce new internal flag CDF_directmap - add a directmap flag under struct arch_domain and use it to reimplement is_domain_direct_mapped. - expand arch_domain_create to include internal-only parameter "const unsig= ned int flags" for domain creation --- docs/misc/arm/device-tree/booting.txt | 6 ++++++ xen/arch/arm/domain.c | 5 ++++- xen/arch/arm/domain_build.c | 14 ++++++++++++-- xen/arch/arm/include/asm/domain.h | 5 +++-- xen/arch/x86/domain.c | 3 ++- xen/common/domain.c | 2 +- xen/include/xen/domain.h | 5 ++++- 7 files changed, 32 insertions(+), 8 deletions(-) diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t= ree/booting.txt index 71895663a4..a94125394e 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -182,6 +182,12 @@ with the following properties: Both #address-cells and #size-cells need to be specified because both sub-nodes (described shortly) have reg properties. =20 +- direct-map + + Only available when statically allocated memory is used for the domain. + An empty property to request the memory of the domain to be + direct-map (guest physical address =3D=3D physical address). + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. =20 diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 92a6c509e5..fa18dfa544 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -692,7 +692,8 @@ int arch_sanitise_domain_config(struct xen_domctl_creat= edomain *config) } =20 int arch_domain_create(struct domain *d, - struct xen_domctl_createdomain *config) + struct xen_domctl_createdomain *config, + const unsigned int flags) { int rc, count =3D 0; =20 @@ -708,6 +709,8 @@ int arch_domain_create(struct domain *d, ioreq_domain_init(d); #endif =20 + d->arch.directmap =3D flags & CDF_directmap; + /* p2m_init relies on some value initialized by the IOMMU subsystem */ if ( (rc =3D iommu_domain_init(d, config->iommu_opts)) !=3D 0 ) goto fail; diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 0fab8604de..9b1a5e38d3 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -3029,10 +3029,20 @@ void __init create_domUs(void) .max_maptrack_frames =3D -1, .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_versio= n), }; + unsigned int flags =3D 0U; =20 if ( !dt_device_is_compatible(node, "xen,domain") ) continue; =20 + if ( dt_property_read_bool(node, "direct-map") ) + { + if ( !IS_ENABLED(CONFIG_STATIC_MEMORY) ) + panic("direct-map is not valid for domain %s without CONFI= G_STATIC_MEMORY\n", + dt_node_name(node)); + + flags |=3D CDF_directmap; + } + if ( !dt_property_read_u32(node, "cpus", &d_cfg.max_vcpus) ) panic("Missing property 'cpus' for domain %s\n", dt_node_name(node)); @@ -3058,7 +3068,7 @@ void __init create_domUs(void) * very important to use the pre-increment operator to call * domain_create() with a domid > 0. (domid =3D=3D 0 is reserved f= or Dom0) */ - d =3D domain_create(++max_init_domid, &d_cfg, 0); + d =3D domain_create(++max_init_domid, &d_cfg, flags); if ( IS_ERR(d) ) panic("Error creating domain %s\n", dt_node_name(node)); =20 @@ -3160,7 +3170,7 @@ void __init create_dom0(void) if ( iommu_enabled ) dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu; =20 - dom0 =3D domain_create(0, &dom0_cfg, CDF_privileged); + dom0 =3D domain_create(0, &dom0_cfg, CDF_privileged | CDF_directmap); if ( IS_ERR(dom0) || (alloc_dom0_vcpu0(dom0) =3D=3D NULL) ) panic("Error creating domain 0\n"); =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index 9b3647587a..cb37ce89ec 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -29,8 +29,7 @@ enum domain_type { #define is_64bit_domain(d) (0) #endif =20 -/* The hardware domain has always its memory direct mapped. */ -#define is_domain_direct_mapped(d) is_hardware_domain(d) +#define is_domain_direct_mapped(d) (d->arch.directmap) =20 struct vtimer { struct vcpu *v; @@ -89,6 +88,8 @@ struct arch_domain #ifdef CONFIG_TEE void *tee; #endif + + bool directmap; } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index ef1812dc14..f6de7a9697 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -722,7 +722,8 @@ static bool emulation_flags_ok(const struct domain *d, = uint32_t emflags) } =20 int arch_domain_create(struct domain *d, - struct xen_domctl_createdomain *config) + struct xen_domctl_createdomain *config, + const unsigned int flags) { bool paging_initialised =3D false; uint32_t emflags; diff --git a/xen/common/domain.c b/xen/common/domain.c index 023c89c0ea..c9bcd77e00 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -659,7 +659,7 @@ struct domain *domain_create(domid_t domid, radix_tree_init(&d->pirq_tree); } =20 - if ( (err =3D arch_domain_create(d, config)) !=3D 0 ) + if ( (err =3D arch_domain_create(d, config, flags)) !=3D 0 ) goto fail; init_status |=3D INIT_arch; =20 diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index cfb0b47f13..2f1e172957 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -31,6 +31,8 @@ void arch_get_domain_info(const struct domain *d, /* CDF_* constant. Internal flags for domain creation. */ /* Is this a privileged domain? */ #define CDF_privileged (1U << 0) +/* Should domain memory be directly mapped? */ +#define CDF_directmap (1U << 1) =20 /* * Arch-specifics. @@ -65,7 +67,8 @@ int map_vcpu_info(struct vcpu *v, unsigned long gfn, unsi= gned offset); void unmap_vcpu_info(struct vcpu *v); =20 int arch_domain_create(struct domain *d, - struct xen_domctl_createdomain *config); + struct xen_domctl_createdomain *config, + const unsigned int flags); =20 void arch_domain_destroy(struct domain *d); =20 --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=2; a=rsa-sha256; t=1639977764; cv=pass; d=zohomail.com; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:21:53.3496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41fa8410-e15a-4553-d70a-08d9c378a233 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT061.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS1PR08MB7498 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977765983100002 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini When IOMMU is absent or shall not be used (trusted domain, performance, hardware limitation, ..., etc), in which cases this commit avoids setting XEN_DOMCTL_CDF_iommu to make those user cases possible and prevent failure later during device assignment. Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng --- v3 changes: - new commit, split from the original "[PATCH v2 2/6] xen/arm: introduce direct-map for domUs" --- v4 changes - explain briefly in the commit message why we want to do device assignment without IOMMU. --- xen/arch/arm/domain_build.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 9b1a5e38d3..5a106a977c 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -3047,7 +3047,8 @@ void __init create_domUs(void) panic("Missing property 'cpus' for domain %s\n", dt_node_name(node)); =20 - if ( dt_find_compatible_node(node, NULL, "multiboot,device-tree") ) + if ( dt_find_compatible_node(node, NULL, "multiboot,device-tree") = && + iommu_enabled ) d_cfg.flags |=3D XEN_DOMCTL_CDF_iommu; =20 if ( !dt_property_read_u32(node, "nr_spis", &d_cfg.arch.nr_spis) ) --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 04/11] xen/arm: introduce new helper parse_static_mem_prop and acquire_static_memory_bank Date: Mon, 20 Dec 2021 05:21:16 +0000 Message-ID: <20211220052123.969876-5-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: cbfcf30c-3c23-4aad-3dfd-08d9c378a404 X-MS-TrafficTypeDiagnostic: AM7PR08MB5365:EE_|AM5EUR03FT025:EE_|DBBPR08MB6170:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:331;OLM:331; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: wnSEqD9lVm2ZFN6rwrINuxgHk46MWk/V+umzCzOY0l2/TQUPExkKxBoXX2pujpRIMAhPYC5SjpOsFkX6fzTRISFy08dBu9s56wanH3KP5LTK5R2IPrBfzU/9eZpgp8oafbbWo9Ek/Ixz7TDJ+dB+UoB82LpnQwG86EwE3l/exLzgxjtI6UEuYrdiMWLG9OAqsc2xyRun8e70UE4N0jVpdtwbYKkT8/Qir7FP0QfrgfvbKHGVggJm2mqeQygXgapd4NpklbuLGFGim+LNlxdI6h/nkpMbuMPqOF9jGMT2uba6r8A2OOWBAJEIbzEwYE1cdd1gGV+ez1Kldr93r/mBxB0xLqOHc5eVVVQe+/HDAtHwYMAmeGfDms86h7dslnvgmwNbRGbeJYZbo9dOCGgO8MsTsyTl5aW2D+sMorW7ZjlLE9tCTlOAHck8KH77w5vMmkus81R1EJoyreR8iLXTEM7F5OG8kCQvKjOW8zQhsrPTAUiy0AZr6gRH43KbtkmI57MyxQxwGthZAS6hHRCp/m8kbXmpnPzWQr/pQXSM+Kg2ubcLv6cZ9uxMEgBth1UAGteZAU26ODrW4G0KNFs7l+Vtxib7IoYTYgp/W5v28qUUwGdpRe/1IgpXMFjEP1YQBgowEv6RDSQAZBnFEdKMcSFXyL7l6yBpVSQe3FlYAr29+IlGMitsrDd76O3gZJWkzd5N/FzJVcWA5K2SuoBcfnwrhLUjnsNfSzrKddiK37QBvi+f9tIEXasgyLKhDF1+l0qC7Gc/KXH9iZa8tVIdQ70XpzJZxNzhGt0hqgAACgE= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(7696005)(110136005)(44832011)(356005)(26005)(1076003)(47076005)(36756003)(86362001)(70586007)(81166007)(54906003)(70206006)(2906002)(8676002)(82310400004)(426003)(6666004)(8936002)(83380400001)(40460700001)(316002)(36860700001)(5660300002)(336012)(4326008)(2616005)(186003)(508600001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:21:56.4244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbfcf30c-3c23-4aad-3dfd-08d9c378a404 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6170 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977767648100013 Content-Type: text/plain; charset="utf-8" Later, we will introduce allocate_static_memory_11 for allocating static memory for direct-map domains, and it will share a lot common codes with the existing allocate_static_memory. In order not to bring a lot of duplicate codes, and also to make the whole code more readable, this commit extracts common codes into two new helpers parse_static_mem_prop and acquire_static_memory_bank. Signed-off-by: Penny Zheng Reviewed-by: Stefano Stabellini --- v3 changes: - new commit to move the split off of the code outside in a separate patch --- v4 changes: - use mfn_eq() instead, because it is the only value used to indicate there is an error and this is more lightweight than mfn_valid() --- xen/arch/arm/domain_build.c | 100 +++++++++++++++++++++++------------- 1 file changed, 64 insertions(+), 36 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 5a106a977c..9206ec908d 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -509,12 +509,69 @@ static bool __init append_static_memory_to_bank(struc= t domain *d, return true; } =20 +static mfn_t __init acquire_static_memory_bank(struct domain *d, + const __be32 **cell, + u32 addr_cells, u32 size_cell= s, + paddr_t *pbase, paddr_t *psiz= e) +{ + mfn_t smfn; + int res; + + device_tree_get_reg(cell, addr_cells, size_cells, pbase, psize); + ASSERT(IS_ALIGNED(*pbase, PAGE_SIZE) && IS_ALIGNED(*psize, PAGE_SIZE)); + if ( PFN_DOWN(*psize) > UINT_MAX ) + { + printk(XENLOG_ERR "%pd: static memory size too large: %#"PRIpaddr, + d, *psize); + return INVALID_MFN; + } + + smfn =3D maddr_to_mfn(*pbase); + res =3D acquire_domstatic_pages(d, smfn, PFN_DOWN(*psize), 0); + if ( res ) + { + printk(XENLOG_ERR + "%pd: failed to acquire static memory: %d.\n", d, res); + return INVALID_MFN; + } + + return smfn; +} + +static int __init parse_static_mem_prop(const struct dt_device_node *node, + u32 *addr_cells, u32 *size_cells, + int *length, const __be32 **cell) +{ + const struct dt_property *prop; + + prop =3D dt_find_property(node, "xen,static-mem", NULL); + if ( !dt_property_read_u32(node, "#xen,static-mem-address-cells", + addr_cells) ) + { + printk(XENLOG_ERR + "failed to read \"#xen,static-mem-address-cells\".\n"); + return -EINVAL; + } + + if ( !dt_property_read_u32(node, "#xen,static-mem-size-cells", + size_cells) ) + { + printk(XENLOG_ERR + "failed to read \"#xen,static-mem-size-cells\".\n"); + return -EINVAL; + } + + *cell =3D (const __be32 *)prop->value; + *length =3D prop->length; + + return 0; +} + /* Allocate memory from static memory as RAM for one specific domain d. */ static void __init allocate_static_memory(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *nod= e) { - const struct dt_property *prop; u32 addr_cells, size_cells, reg_cells; unsigned int nr_banks, gbank, bank =3D 0; const uint64_t rambase[] =3D GUEST_RAM_BANK_BASES; @@ -523,24 +580,10 @@ static void __init allocate_static_memory(struct doma= in *d, u64 tot_size =3D 0; paddr_t pbase, psize, gsize; mfn_t smfn; - int res; - - prop =3D dt_find_property(node, "xen,static-mem", NULL); - if ( !dt_property_read_u32(node, "#xen,static-mem-address-cells", - &addr_cells) ) - { - printk(XENLOG_ERR - "%pd: failed to read \"#xen,static-mem-address-cells\".\n",= d); - goto fail; - } + int length; =20 - if ( !dt_property_read_u32(node, "#xen,static-mem-size-cells", - &size_cells) ) - { - printk(XENLOG_ERR - "%pd: failed to read \"#xen,static-mem-size-cells\".\n", d); + if ( parse_static_mem_prop(node, &addr_cells, &size_cells, &length, &c= ell) ) goto fail; - } reg_cells =3D addr_cells + size_cells; =20 /* @@ -551,29 +594,14 @@ static void __init allocate_static_memory(struct doma= in *d, gbank =3D 0; gsize =3D ramsize[gbank]; kinfo->mem.bank[gbank].start =3D rambase[gbank]; - - cell =3D (const __be32 *)prop->value; - nr_banks =3D (prop->length) / (reg_cells * sizeof (u32)); + nr_banks =3D length / (reg_cells * sizeof (u32)); =20 for ( ; bank < nr_banks; bank++ ) { - device_tree_get_reg(&cell, addr_cells, size_cells, &pbase, &psize); - ASSERT(IS_ALIGNED(pbase, PAGE_SIZE) && IS_ALIGNED(psize, PAGE_SIZE= )); - - if ( PFN_DOWN(psize) > UINT_MAX ) - { - printk(XENLOG_ERR "%pd: static memory size too large: %#"PRIpa= ddr, - d, psize); + smfn =3D acquire_static_memory_bank(d, &cell, addr_cells, size_cel= ls, + &pbase, &psize); + if ( mfn_eq(smfn, INVALID_MFN) ) goto fail; - } - smfn =3D maddr_to_mfn(pbase); - res =3D acquire_domstatic_pages(d, smfn, PFN_DOWN(psize), 0); - if ( res ) - { - printk(XENLOG_ERR - "%pd: failed to acquire static memory: %d.\n", d, res); - goto fail; - } =20 printk(XENLOG_INFO "%pd: STATIC BANK[%u] %#"PRIpaddr"-%#"PRIpaddr"= \n", d, bank, pbase, pbase + psize); --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=2; a=rsa-sha256; t=1639977764; cv=pass; d=zohomail.com; s=zohoarc; b=OEzXXz/ED2Z8U5UYxlBNbcYl9tHFeOHIo1w0lnY4Z8Pue6rIrqcVmP/MEqjHRqmaP/GawqjYhkzASMdOFPUJGv+xO8oq+ud2Mx6Le+jvfq8oSwGTs1hmol5dv6Lt/+I+oJCyNXUAiBz8g0ocSVVvMxbtzL0CqPX2Vwkm6a0kvQg= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639977764; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 05/11] xen/arm: introduce direct-map for domUs Date: Mon, 20 Dec 2021 05:21:17 +0000 Message-ID: <20211220052123.969876-6-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: c8d1b557-70e5-418b-c94d-08d9c378a582 X-MS-TrafficTypeDiagnostic: VI1PR0801MB1984:EE_|DB5EUR03FT006:EE_|DB9PR08MB6505:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:1332;OLM:1332; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 5rkz5Th8QweEvQeJmmx0hY4JHXNUg5CjH3Ve03QWZzMRHcs6aFlhHC6aH2dEUlSiEJHAyriNAgZpfY3JyGLLtpaD1EQgYrSoT6/r27tbqjnyzHJrFI4Ha9gTSE2F7rmWaz/DQm57PpRp3Vu1LLHRR4dDe2UygpKVg7EVCOTghod1jPgbi/vdi/Isu4cs64e7X0kYH4gOwaYhbbjHduYXq9Zz1vwqA6xxxsM81uucpj/Dubd8lQWvpy2Yk8MoiGT7JDhNQ1QPWkYDORqz0udg+F3ztjM0c2l3xLAziXCaCKBcL+xnayaExlesZXLYDT0y32jXv/JHdQZgPVdXAXKk/WWktTcr5nEdRlxuw3vjvpwa1OwcAihGStVpbk+a0seixQ1yvj3XPyJIxTstuIghDQKgU+FQDEpSTz/aqnAJlPHA9D/c+fBg5qqKnX+BGglzRuIs5jMJQXoJFo4CUVWHW0etyIM7lEXQrkzbmzyWLER3/s5JoCIVKUf+Tuhzt5oJ+t44XdjOfu9DDWUZj3z4Qp7TxfiNho9NZjs7SrmP90lvY3Jjd0QBmiyRCm0JVI7LIkaQZhPDt4tPhyZEZUhwFiI8qZBMBU5XIeJaM2yrwG5bplwfIQlZV8IKm+VvzJwF6AbkAiICXPNl2l7pK8BiA8FcCjDi0/A+abFGaFbGsay4EDp2vxDbdfEhcY6cll4hbGAECLRpQUUS0Njg2snBfK1PElorGksCKmj4J+6tCiAgDYvQXun01zKgomGsKpIZKDC8IumOJd6g4qYEie84w4d9toJQWuxXVe9cJ3MGcyw= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(356005)(81166007)(44832011)(70586007)(36860700001)(47076005)(110136005)(54906003)(70206006)(82310400004)(36756003)(316002)(4326008)(5660300002)(508600001)(8936002)(8676002)(2906002)(2616005)(7696005)(1076003)(83380400001)(26005)(426003)(86362001)(186003)(336012)(6666004)(40460700001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:21:58.9939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8d1b557-70e5-418b-c94d-08d9c378a582 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6505 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977766003100003 Content-Type: text/plain; charset="utf-8" Cases where domU needs direct-map memory map: * IOMMU not present in the system. * IOMMU disabled if it doesn't cover a specific device and all the guests are trusted. Thinking a mixed scenario, where a few devices with IOMMU and a few without, then guest DMA security still could not be totally guarantee= d. So users may want to disable the IOMMU, to at least gain some performance improvement from IOMMU disabled. * IOMMU disabled as a workaround when it doesn't have enough bandwidth. To be specific, in a few extreme situation, when multiple devices do DMA concurrently, these requests may exceed IOMMU's transmission capacity. * IOMMU disabled when it adds too much latency on DMA. For example, TLB may be missing in some IOMMU hardware, which may bring latency in DMA progress, so users may want to disable it in some realtime scenario. * Guest OS relies on the host memory layout This commit introduces a new helper assign_static_memory_11 to allocate static memory as guest RAM for direct-map domain. Signed-off-by: Penny Zheng Reviewed-by: Stefano Stabellini --- v2 changes: - split the common codes into two helpers: parse_static_mem_prop and acquire_static_memory_bank to deduce complexity. - introduce a new helper allocate_static_memory_11 for allocating static memory for direct-map guests - remove redundant use "bool direct_map", to be replaced by d_cfg.flags & XEN_DOMCTL_CDF_directmap - remove panic action since it is fine to assign a non-DMA capable device w= hen IOMMU and direct-map both off --- v3 changes: - doc refinement - drop the pointless gbank - add check of the size of nr_banks shall not exceed NR_MEM_BANKS - add ASSERT_UNREACHABLE to catch any misuse - add another check of validating flag XEN_DOMCTL_CDF_INTERNAL_directmap on= ly when CONFIG_STATIC_MEMORY is set. --- v4 changes: - comment refinement - rename function allocate_static_memory_11() to assign_static_memory_11() to make clear there is actually no allocation done. Instead we are only mapping pre-defined host regions to pre-defined guest regions. - remove tot_size to directly substract psize from kinfo->unassigned_mem - check kinfo->unassigned_mem doesn't underflow or overflow - remove nested if/else - refine "panic" info --- xen/arch/arm/domain_build.c | 97 +++++++++++++++++++++++++++++++++++-- 1 file changed, 94 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 9206ec908d..d74a3eb908 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -494,8 +494,17 @@ static bool __init append_static_memory_to_bank(struct= domain *d, { int res; unsigned int nr_pages =3D PFN_DOWN(size); - /* Infer next GFN. */ - gfn_t sgfn =3D gaddr_to_gfn(bank->start + bank->size); + gfn_t sgfn; + + /* + * For direct-mapped domain, the GFN match the MFN. + * Otherwise, this is inferred on what has already been allocated + * in the bank. + */ + if ( !is_domain_direct_mapped(d) ) + sgfn =3D gaddr_to_gfn(bank->start + bank->size); + else + sgfn =3D gaddr_to_gfn(mfn_to_maddr(smfn)); =20 res =3D guest_physmap_add_pages(d, sgfn, smfn, nr_pages); if ( res ) @@ -668,12 +677,92 @@ static void __init allocate_static_memory(struct doma= in *d, fail: panic("Failed to allocate requested static memory for domain %pd.", d); } + +/* + * Allocate static memory as RAM for one specific domain d. + * The static memory will be directly mapped in the guest(Guest Physical + * Address =3D=3D Physical Address). + */ +static void __init assign_static_memory_11(struct domain *d, + struct kernel_info *kinfo, + const struct dt_device_node *= node) +{ + u32 addr_cells, size_cells, reg_cells; + unsigned int nr_banks, bank =3D 0; + const __be32 *cell; + paddr_t pbase, psize; + mfn_t smfn; + int length; + + if ( parse_static_mem_prop(node, &addr_cells, &size_cells, &length, &c= ell) ) + { + printk(XENLOG_ERR + "%pd: failed to parse \"xen,static-mem\" property.\n", d); + goto fail; + } + reg_cells =3D addr_cells + size_cells; + nr_banks =3D length / (reg_cells * sizeof (u32)); + + if ( nr_banks > NR_MEM_BANKS ) + { + printk(XENLOG_ERR + "%pd: exceed max number of supported guest memory banks.\n"= , d); + goto fail; + } + + for ( ; bank < nr_banks; bank++ ) + { + smfn =3D acquire_static_memory_bank(d, &cell, addr_cells, size_cel= ls, + &pbase, &psize); + if ( mfn_eq(smfn, INVALID_MFN) ) + goto fail; + + printk(XENLOG_INFO "%pd: STATIC BANK[%u] %#"PRIpaddr"-%#"PRIpaddr"= \n", + d, bank, pbase, pbase + psize); + + /* One guest memory bank is matched with one physical memory bank.= */ + kinfo->mem.bank[bank].start =3D pbase; + if ( !append_static_memory_to_bank(d, &kinfo->mem.bank[bank], + smfn, psize) ) + goto fail; + + kinfo->unassigned_mem -=3D psize; + } + + kinfo->mem.nr_banks =3D nr_banks; + + /* + * The property 'memory' should match the amount of memory given to + * the guest. + * Currently, it is only possible to either acquire static memory or + * let Xen allocate. *Mixing* is not supported. + */ + if ( kinfo->unassigned_mem !=3D 0 ) + { + printk(XENLOG_ERR + "Size of \"memory\" property doesn't match up with the sum-= up of \"xen,static-mem\". Unsupported configuration.\n"); + goto fail; + } + + return; + + fail: + panic("Failed to assign requested static memory for direct-map domain = %pd.", + d); +} #else static void __init allocate_static_memory(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *nod= e) { } + +static void __init assign_static_memory_11(struct domain *d, + struct kernel_info *kinfo, + const struct dt_device_node *= node) +{ + ASSERT_UNREACHABLE(); +} #endif =20 /* @@ -3023,8 +3112,10 @@ static int __init construct_domU(struct domain *d, #endif if ( !dt_find_property(node, "xen,static-mem", NULL) ) allocate_memory(d, &kinfo); - else + else if ( !is_domain_direct_mapped(d) ) allocate_static_memory(d, &kinfo, node); + else + assign_static_memory_11(d, &kinfo, node); =20 rc =3D prepare_dtb_domU(d, &kinfo); if ( rc < 0 ) --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 06/11] xen/arm: add ASSERT_UNREACHABLE in allocate_static_memory Date: Mon, 20 Dec 2021 05:21:18 +0000 Message-ID: <20211220052123.969876-7-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: bd8877a3-9b4d-4e02-3189-08d9c378a7fa X-MS-TrafficTypeDiagnostic: DB9PR08MB7147:EE_|AM5EUR03FT040:EE_|AM4PR08MB2641:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:326;OLM:326; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 0Zs4f0UwIqYxF88zbt4weHSwIDHtVqFlgU8QWkxXbXPSu7YqFTcg812DbuCWiLfwHPjCRJeLo9kOJ4i2SvFygj1TVX+RQVKr4Bha5Mi52czEYQiQPydrhQJmtrV7mxUk+VcM7/EgWvS4weQcuIemp567vo9KODpZF1kg48zIucgkN7vx+u/JldRn5ZarmN18eypetaF8Od5uDKjMvtaqEqDB/FYUK99mX0tpYPTluMjGR+r9tu89g/7PgJ6DVhR/ll6JUvj2M+uTGjZVMt+CnF3/eESOPkzZrDu+tRbt+Ln4X8Od0NI9eentx4458ec9QMw8acx/+vIh7VRzirmGTrOxy6VVXIjY2afIYZh5lRpuZmWghwdYq/Cj5xGPO2lyx4Dq1dIIvNI0ceSercNQZY5+97qIx5A9kgIg9ii8U5avoASTof7jdm0TPDieNNd3TiwyMmchm7awpIGBjdBateNCFBk7niXrfntLb+fzalAPToZIiHM5bDBHXN9LUfctNnK+hDrq5DAVoz8mmXPDteF2bP3oBAr+eWFBP2AvwGIMYlHhz2EOCRmrm7kjLWnV2tAkfuAFeenAZYyQr/KE9xQWOpls64mxlxDm7qXIQd1jy+doC020GShmCNBV9pPDd06Klx4Juyn3asQljdYNnDbE/RTeyn73wIHOLpqV4k6sU2+aftCd+vqLTsjbqnfJrE+kHQpQGbWquyh5wLKuV/59rqLad2j2jZ+OE19AJBaK+7KGhE7nIySIjft0VxAB3yZafBhMa6ZhLogMSkmvDykJe0kAEwImyOdJri9RGTQ= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(44832011)(8676002)(5660300002)(40460700001)(70206006)(1076003)(81166007)(2616005)(6666004)(186003)(4744005)(82310400004)(4326008)(26005)(426003)(356005)(336012)(70586007)(110136005)(54906003)(36860700001)(86362001)(47076005)(316002)(36756003)(508600001)(7696005)(2906002)(8936002)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:22:03.0694 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd8877a3-9b4d-4e02-3189-08d9c378a7fa X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT040.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR08MB2641 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977765976100001 Content-Type: text/plain; charset="utf-8" Helper allocate_static_memory is not meant to be reachable when built with !CONFIG_STATIC_MEMORY, so this commit adds ASSERT_UNREACHABLE in it to catch potential misuse. Signed-off-by: Penny Zheng Acked-by: Julien Grall --- v3 changes: - new commit --- xen/arch/arm/domain_build.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index d74a3eb908..b706e674c9 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -755,6 +755,7 @@ static void __init allocate_static_memory(struct domain= *d, struct kernel_info *kinfo, const struct dt_device_node *nod= e) { + ASSERT_UNREACHABLE(); } =20 static void __init assign_static_memory_11(struct domain *d, --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=2; a=rsa-sha256; t=1639977765; cv=pass; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 07/11] xen/arm: if direct-map domain use native addresses for GICv2 Date: Mon, 20 Dec 2021 05:21:19 +0000 Message-ID: <20211220052123.969876-8-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: b645d35f-e08a-4f75-521c-08d9c378a8f8 X-MS-TrafficTypeDiagnostic: PR3PR08MB5705:EE_|DB5EUR03FT043:EE_|AM6PR08MB4280:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:9508;OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: /0kL8LQHnspemuLNv/coXD+8MO3dwDVlLci8MUFdswrNtjjhDOhIxGjnYbd0co6+LZx6eK0yK8uMHeNv5lftZd5FE5A+UpOOdklL26ueZWTEHj6BxOnJw2lcK6wMcKLE+475YHrT2jLk1tYqulO45zYisM+IWbqQlfU5g7L9fJrY010tie+6oIwObAvbBMHsG1g4+z/HcIECofNc4t7dbaWvqG79fmyeB/KhikWBsu75W4VYPsie0K2TcoezyUb5fMQk1Z04xXdxvT9CiS0vlqpzUIBDpQp9XguMJ+2HIC1SNCkH8Dv7yruwhxQWQUqftgut8IWzQaD1+ojMdQebAiHDY5uKk14DidwGdbUGjOMSX6/CV7xc/5jbnGKAAehJetAngWnvuswJb15SvKDMBu1OhftX7ejVll/1JCGfFl5ND53lGCSoAWg/ShNwbawV3lMVceg4doXsgvx880yG45PbOP1q/uFC5ucUQKKHgTgUDCPkse0xlzTwk2ft9PYIBJvKUsLOSCc3BZO1eMRWu2DHtK/lEhOZPiTkhkaTSK4/tZRQgovzMhojnp8ZDyOzZNri1hEg/tVuzacHLw14cTJdat3542/u6go4nB7ziks2NpPqAvrZZOR32bDXu8Dj9Oeun5f1fnVG4rbITF/KwTM3yhbqbRxpNM5GTrRnK8U1mjXXmrN00mbNk1d6GFQc/x9I/EWbhZzQphUh7BYDeRDks3BsVrVchGh3L/MPO8J4uXyxgl+H4IONyaCelqQCmFrno2O5EYxZxDlrimU3x7i3dxMQXyXiD9AMyHfWhgw= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(36860700001)(1076003)(508600001)(54906003)(4326008)(186003)(86362001)(336012)(316002)(356005)(110136005)(6666004)(81166007)(82310400004)(36756003)(47076005)(44832011)(7696005)(40460700001)(83380400001)(2616005)(5660300002)(426003)(2906002)(8936002)(8676002)(70586007)(70206006)(26005)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:22:04.7817 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b645d35f-e08a-4f75-521c-08d9c378a8f8 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT043.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4280 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639978668876100003 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini Today we use native addresses to map the GICv2 for Dom0 and fixed addresses for DomUs. This patch changes the behavior so that native addresses are used for all domains that are direct-mapped. NEW VGIC has different naming schemes, like referring distributor base address as vgic_dist_base, other than the dbase. So this patch also introdu= ces vgic_dist_base/vgic_cpu_base accessor to access correct distributor base address/cpu interface base address on varied scenarios, Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng --- v2 changes - combine all changes in patch 4-6 here --- v3 changes - refine comment message - add a comment explaining how the 38 was found of "char buf[38]" - simply map the CPU interface at the GPA vgic_v2_hw.cbase - remove a spurious change --- v4 changes: - refine comment to let it be a summary of the if/else if/else. --- xen/arch/arm/domain_build.c | 11 +++++++--- xen/arch/arm/include/asm/new_vgic.h | 10 +++++++++ xen/arch/arm/include/asm/vgic.h | 11 ++++++++++ xen/arch/arm/vgic-v2.c | 34 +++++++++++++++++++++++------ xen/arch/arm/vgic/vgic-v2.c | 34 +++++++++++++++++++++++------ 5 files changed, 83 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index b706e674c9..4788b03d8b 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2273,8 +2273,13 @@ static int __init make_gicv2_domU_node(struct kernel= _info *kinfo) int res =3D 0; __be32 reg[(GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS) * 2]; __be32 *cells; + const struct domain *d =3D kinfo->d; + /* Placeholder for interrupt-controller@ + a 64-bit number + \0 */ + char buf[38]; =20 - res =3D fdt_begin_node(fdt, "interrupt-controller@"__stringify(GUEST_G= ICD_BASE)); + snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, + vgic_dist_base(&d->arch.vgic)); + res =3D fdt_begin_node(fdt, buf); if ( res ) return res; =20 @@ -2296,9 +2301,9 @@ static int __init make_gicv2_domU_node(struct kernel_= info *kinfo) =20 cells =3D ®[0]; dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_C= ELLS, - GUEST_GICD_BASE, GUEST_GICD_SIZE); + vgic_dist_base(&d->arch.vgic), GUEST_GICD_SIZE); dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_C= ELLS, - GUEST_GICC_BASE, GUEST_GICC_SIZE); + vgic_cpu_base(&d->arch.vgic), GUEST_GICC_SIZE); =20 res =3D fdt_property(fdt, "reg", reg, sizeof(reg)); if (res) diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm= /new_vgic.h index 97d622bff6..ab57fcd91d 100644 --- a/xen/arch/arm/include/asm/new_vgic.h +++ b/xen/arch/arm/include/asm/new_vgic.h @@ -186,6 +186,16 @@ struct vgic_cpu { uint32_t num_id_bits; }; =20 +static inline paddr_t vgic_cpu_base(const struct vgic_dist *vgic) +{ + return vgic->vgic_cpu_base; +} + +static inline paddr_t vgic_dist_base(const struct vgic_dist *vgic) +{ + return vgic->vgic_dist_base; +} + #endif /* __ASM_ARM_NEW_VGIC_H */ =20 /* diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi= c.h index ade427a808..d2a9fc7d83 100644 --- a/xen/arch/arm/include/asm/vgic.h +++ b/xen/arch/arm/include/asm/vgic.h @@ -152,6 +152,7 @@ struct vgic_dist { struct pending_irq *pending_irqs; /* Base address for guest GIC */ paddr_t dbase; /* Distributor base address */ + paddr_t cbase; /* CPU interface base address */ #ifdef CONFIG_GICV3 /* GIC V3 addressing */ /* List of contiguous occupied by the redistributors */ @@ -271,6 +272,16 @@ static inline int REG_RANK_NR(int b, uint32_t n) =20 enum gic_sgi_mode; =20 +static inline paddr_t vgic_cpu_base(const struct vgic_dist *vgic) +{ + return vgic->cbase; +} + +static inline paddr_t vgic_dist_base(const struct vgic_dist *vgic) +{ + return vgic->dbase; +} + /* * Offset of GICD_ with its rank, for GICD_ size with * -bits-per-interrupt. diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 589c033eda..b1bd7a46ad 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -654,12 +654,16 @@ static int vgic_v2_vcpu_init(struct vcpu *v) static int vgic_v2_domain_init(struct domain *d) { int ret; - paddr_t cbase, csize; + paddr_t csize; paddr_t vbase; =20 /* - * The hardware domain gets the hardware address. - * Guests get the virtual platform layout. + * The hardware domain and direct-mapped domain both get the hardware + * address. + * We have to handle them separately because the hwdom is re-using the + * same Device-Tree as the host (see more details below). + * + * Other domains get the virtual platform layout. */ if ( is_hardware_domain(d) ) { @@ -671,10 +675,26 @@ static int vgic_v2_domain_init(struct domain *d) * Note that we assume the size of the CPU interface is always * aligned to PAGE_SIZE. */ - cbase =3D vgic_v2_hw.cbase; + d->arch.vgic.cbase =3D vgic_v2_hw.cbase; csize =3D vgic_v2_hw.csize; vbase =3D vgic_v2_hw.vbase; } + else if ( is_domain_direct_mapped(d) ) + { + /* + * For all the direct-mapped domain other than the hardware domain, + * we only map a 8kB CPU interface but we make sure it is at a + * location occupied by the physical GIC in the host device tree. + * + * We need to add an offset to the virtual CPU interface base + * address when the GIC is aliased to get a 8kB contiguous + * region. + */ + d->arch.vgic.dbase =3D vgic_v2_hw.dbase; + d->arch.vgic.cbase =3D vgic_v2_hw.cbase; + csize =3D GUEST_GICC_SIZE; + vbase =3D vgic_v2_hw.vbase + vgic_v2_hw.aliased_offset; + } else { d->arch.vgic.dbase =3D GUEST_GICD_BASE; @@ -685,7 +705,7 @@ static int vgic_v2_domain_init(struct domain *d) * region. */ BUILD_BUG_ON(GUEST_GICC_SIZE !=3D SZ_8K); - cbase =3D GUEST_GICC_BASE; + d->arch.vgic.cbase =3D GUEST_GICC_BASE; csize =3D GUEST_GICC_SIZE; vbase =3D vgic_v2_hw.vbase + vgic_v2_hw.aliased_offset; } @@ -694,8 +714,8 @@ static int vgic_v2_domain_init(struct domain *d) * Map the gic virtual cpu interface in the gic cpu interface * region of the guest. */ - ret =3D map_mmio_regions(d, gaddr_to_gfn(cbase), csize / PAGE_SIZE, - maddr_to_mfn(vbase)); + ret =3D map_mmio_regions(d, gaddr_to_gfn(d->arch.vgic.cbase), + csize / PAGE_SIZE, maddr_to_mfn(vbase)); if ( ret ) return ret; =20 diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index b5ba4ace87..1a99d3a8b4 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -258,13 +258,17 @@ void vgic_v2_enable(struct vcpu *vcpu) int vgic_v2_map_resources(struct domain *d) { struct vgic_dist *dist =3D &d->arch.vgic; - paddr_t cbase, csize; + paddr_t csize; paddr_t vbase; int ret; =20 /* - * The hardware domain gets the hardware address. - * Guests get the virtual platform layout. + * The hardware domain and direct-mapped domain both get the hardware + * address. + * We have to handle them separately because the hwdom is re-using the + * same Device-Tree as the host (see more details below). + * + * Other domains get the virtual platform layout. */ if ( is_hardware_domain(d) ) { @@ -276,10 +280,26 @@ int vgic_v2_map_resources(struct domain *d) * Note that we assume the size of the CPU interface is always * aligned to PAGE_SIZE. */ - cbase =3D gic_v2_hw_data.cbase; + d->arch.vgic.vgic_cpu_base =3D gic_v2_hw_data.cbase; csize =3D gic_v2_hw_data.csize; vbase =3D gic_v2_hw_data.vbase; } + else if ( is_domain_direct_mapped(d) ) + { + d->arch.vgic.vgic_dist_base =3D gic_v2_hw_data.dbase; + /* + * For all the direct-mapped domain other than the hardware domain, + * we only map a 8kB CPU interface but we make sure it is at a loc= ation + * occupied by the physical GIC in the host device tree. + * + * We need to add an offset to the virtual CPU interface base + * address when the GIC is aliased to get a 8kB contiguous + * region. + */ + d->arch.vgic.vgic_cpu_base =3D gic_v2_hw_data.cbase; + csize =3D GUEST_GICC_SIZE; + vbase =3D gic_v2_hw_data.vbase + gic_v2_hw_data.aliased_offset; + } else { d->arch.vgic.vgic_dist_base =3D GUEST_GICD_BASE; @@ -290,7 +310,7 @@ int vgic_v2_map_resources(struct domain *d) * region. */ BUILD_BUG_ON(GUEST_GICC_SIZE !=3D SZ_8K); - cbase =3D GUEST_GICC_BASE; + d->arch.vgic.vgic_cpu_base =3D GUEST_GICC_BASE; csize =3D GUEST_GICC_SIZE; vbase =3D gic_v2_hw_data.vbase + gic_v2_hw_data.aliased_offset; } @@ -308,8 +328,8 @@ int vgic_v2_map_resources(struct domain *d) * Map the gic virtual cpu interface in the gic cpu interface * region of the guest. */ - ret =3D map_mmio_regions(d, gaddr_to_gfn(cbase), csize / PAGE_SIZE, - maddr_to_mfn(vbase)); + ret =3D map_mmio_regions(d, gaddr_to_gfn(d->arch.vgic.vgic_cpu_base), + csize / PAGE_SIZE, maddr_to_mfn(vbase)); if ( ret ) { gdprintk(XENLOG_ERR, "Unable to remap VGIC CPU to VCPU\n"); --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=2; a=rsa-sha256; t=1639977766; cv=pass; d=zohomail.com; s=zohoarc; b=PAWaYO2Yzq4XFRD1X1wvD4Sppm8sX/Uc7yrXLeqi33SdOoGa4YXtWzcyu3YuUp7w0RN9++IJSopHrnbF+rBwpQCMOXqdqZ8gtwAYmVnAe++j0A6d58Nba0r7u6ntl7JIPtVTunsOjrWILxgh6Mjuzd6ei7p/eM/YL3qXyDShyys= ARC-Message-Signature: i=2; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:22:05.3607 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffe050a7-054a-49d9-d009-08d9c378a957 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT064.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR08MB5845 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639978668835100001 Content-Type: text/plain; charset="utf-8" This commit gates function make_gicv3_domU_node with CONFIG_GICV3. Signed-off-by: Penny Zheng Acked-by: Stefano Stabellini --- v4 changes: - remove ASSERT_UNREACHABLE() to avoid breaking compilation on prod build w= ith CONFIG_GICV3=3Dn --- xen/arch/arm/domain_build.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 4788b03d8b..139d428524 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2322,6 +2322,7 @@ static int __init make_gicv2_domU_node(struct kernel_= info *kinfo) return res; } =20 +#ifdef CONFIG_GICV3 static int __init make_gicv3_domU_node(struct kernel_info *kinfo) { void *fdt =3D kinfo->fdt; @@ -2371,13 +2372,16 @@ static int __init make_gicv3_domU_node(struct kerne= l_info *kinfo) =20 return res; } +#endif =20 static int __init make_gic_domU_node(struct kernel_info *kinfo) { switch ( kinfo->d->arch.vgic.version ) { +#ifdef CONFIG_GICV3 case GIC_V3: return make_gicv3_domU_node(kinfo); +#endif case GIC_V2: return make_gicv2_domU_node(kinfo); default: --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 09/11] xen/arm: if direct-map domain use native addresses for GICv3 Date: Mon, 20 Dec 2021 05:21:21 +0000 Message-ID: <20211220052123.969876-10-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: fe50a42e-41a9-4512-52cd-08d9c378aacd X-MS-TrafficTypeDiagnostic: AM0PR08MB3201:EE_|DB5EUR03FT013:EE_|DBAPR08MB5831:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:6430;OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: /+9Aj73JQ4bd5Uop/CVWYPd7Gbvp0bTJM+SvUIow1pwVDQLClxnboo/d2gtdLx9IBD+vELazK0SuhgvCVwHW8I4oB8Lvwd4dssmSpFhhmxancKQiyL72n8os5hrov2BlsOa/PK0VY/nSA2O15MycEWPOR/uxPmk9VIeibSY0jGI/tPvQpxugjA/brY886GEkCdRslCiz8FITsbNi7UYxrSctJQXBxtU9FRQTwMpaIduxY8wiJguiVtEB046AyIeHpZpT+7rXw+P9zv5GLz6vwRzxueu5VEqm7apkx4Pzma6HL4239dBq3kJBVwWVYkdNSpJMQ+NYTzDt6iy0gS2VQSF0HlXLbCMVZ6rvPHUE04J74Yy8/doCQjcqaYuolpw3zpEN+QDLCqRQbeZHW/ray+reKHMm7R5acEbenqYs+WW0vdWV4rrKzW3NxXcE5PLUpnKUfwgeckzU4Dbs7uTtymWnmiTb4vwgIY0uAqeQ8Ez5pEgl4toCkrMFouEcjfJBPXJVJtJBE3XJwsRkC6FobM8cUtjKw4ctdYQpmWJLdQDo9vUWwflgh0OFAAQKFirxwazYc9uA7H8TTnQCp/HrBa1d4naPGPmeNQYq6tRiTu2GoKIjNrC2JzJZgWfsq0rRFPQz9UGstr/RFtdd7B4bfU6keyu5oh0Znlf/MlfGLLK7WdFot2h/hTtw2YaB6yHG3b9IdINsTy0rbvj1CyEnSLn4xT8KD4w36SZ53xUxtgPec5xLs5ANyQD6hMlKcS+nKz50SWq8e3vx7N1fMafVi+JkgmY04oFqv4ZszET5n30= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(336012)(426003)(6666004)(70586007)(2616005)(1076003)(70206006)(44832011)(47076005)(36756003)(4326008)(36860700001)(5660300002)(356005)(81166007)(83380400001)(54906003)(82310400004)(8676002)(8936002)(40460700001)(86362001)(2906002)(110136005)(316002)(26005)(186003)(7696005)(508600001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:22:07.8554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe50a42e-41a9-4512-52cd-08d9c378aacd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT013.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR08MB5831 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977767737100018 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini Today we use native addresses to map the GICv3 for Dom0 and fixed addresses for DomUs. This patch changes the behavior so that native addresses are used for all domain which is using the host memory layout Considering that DOM0 may not always be directly mapped in the future, this patch introduces a new helper "domain_use_host_layout()" that wraps both two check "is_domain_direct_mapped(d) || is_hardware_domain(d)" for more flexible usage. Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng --- v2 changes: - remove redistributor accessor - introduce new helper "is_domain_use_host_layout()" - comment fix --- v3 changes: - the comment on top of 'buf' to explain how 38 was found - fix res getting overwritten - drop 'cells +=3D (GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS)' - free 'reg' right way - fix comment - rename 'is_domain_use_host_layout()' to 'domain_use_host_layout()' --- v4 changes: - refine comment --- xen/arch/arm/domain_build.c | 34 +++++++++++++++++++++++-------- xen/arch/arm/include/asm/domain.h | 14 +++++++++++++ xen/arch/arm/vgic-v3.c | 26 ++++++++++++----------- 3 files changed, 54 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 139d428524..9a7145b3ee 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2327,10 +2327,16 @@ static int __init make_gicv3_domU_node(struct kerne= l_info *kinfo) { void *fdt =3D kinfo->fdt; int res =3D 0; - __be32 reg[(GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS) * 2]; - __be32 *cells; + __be32 *reg, *cells; + const struct domain *d =3D kinfo->d; + /* Placeholder for interrupt-controller@ + a 64-bit number + \0 */ + char buf[38]; + unsigned int i, len =3D 0; + + snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, + vgic_dist_base(&d->arch.vgic)); =20 - res =3D fdt_begin_node(fdt, "interrupt-controller@"__stringify(GUEST_G= ICV3_GICD_BASE)); + res =3D fdt_begin_node(fdt, buf); if ( res ) return res; =20 @@ -2350,13 +2356,25 @@ static int __init make_gicv3_domU_node(struct kerne= l_info *kinfo) if ( res ) return res; =20 - cells =3D ®[0]; - dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_C= ELLS, - GUEST_GICV3_GICD_BASE, GUEST_GICV3_GICD_SIZE); + /* reg specifies all re-distributors and Distributor. */ + len =3D (GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS) * + (d->arch.vgic.nr_regions + 1) * sizeof(__be32); + reg =3D xmalloc_bytes(len); + if ( reg =3D=3D NULL ) + return -ENOMEM; + cells =3D reg; + dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_C= ELLS, - GUEST_GICV3_GICR0_BASE, GUEST_GICV3_GICR0_SIZE); + vgic_dist_base(&d->arch.vgic), GUEST_GICV3_GICD_SIZ= E); =20 - res =3D fdt_property(fdt, "reg", reg, sizeof(reg)); + for ( i =3D 0; i < d->arch.vgic.nr_regions; i++) + dt_child_set_range(&cells, + GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_CELLS, + d->arch.vgic.rdist_regions[i].base, + d->arch.vgic.rdist_regions[i].size); + + res =3D fdt_property(fdt, "reg", reg, len); + xfree(reg); if (res) return res; =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index cb37ce89ec..848fec8a0f 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -31,6 +31,20 @@ enum domain_type { =20 #define is_domain_direct_mapped(d) (d->arch.directmap) =20 +/* + * Is the domain using the host memory layout? + * + * Direct-mapped domain will always have the RAM mapped with GFN =3D=3D MF= N. + * To avoid any trouble finding space, it is easier to force using the + * host memory layout. + * + * The hardware domain will use the host layout regardless of + * direct-mapped because some OS may rely on a specific address ranges + * for the devices. + */ +#define domain_use_host_layout(d) (is_domain_direct_mapped(d) || \ + is_hardware_domain(d)) + struct vtimer { struct vcpu *v; int irq; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 65bb7991a6..144089a7b6 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1640,14 +1640,15 @@ static inline unsigned int vgic_v3_max_rdist_count(= struct domain *d) * Normally there is only one GICv3 redistributor region. * The GICv3 DT binding provisions for multiple regions, since there a= re * platforms out there which need those (multi-socket systems). - * For Dom0 we have to live with the MMIO layout the hardware provides, - * so we have to copy the multiple regions - as the first region may n= ot - * provide enough space to hold all redistributors we need. + * For domain using the host memory layout, we have to live with the M= MIO + * layout the hardware provides, so we have to copy the multiple regio= ns + * - as the first region may not provide enough space to hold all + * redistributors we need. * However DomU get a constructed memory map, so we can go with * the architected single redistributor region. */ - return is_hardware_domain(d) ? vgic_v3_hw.nr_rdist_regions : - GUEST_GICV3_RDIST_REGIONS; + return domain_use_host_layout(d) ? vgic_v3_hw.nr_rdist_regions : + GUEST_GICV3_RDIST_REGIONS; } =20 static int vgic_v3_domain_init(struct domain *d) @@ -1669,10 +1670,11 @@ static int vgic_v3_domain_init(struct domain *d) radix_tree_init(&d->arch.vgic.pend_lpi_tree); =20 /* - * Domain 0 gets the hardware address. - * Guests get the virtual platform layout. + * For domain using the host memory layout, it gets the hardware + * address. + * Other domains get the virtual platform layout. */ - if ( is_hardware_domain(d) ) + if ( domain_use_host_layout(d) ) { unsigned int first_cpu =3D 0; =20 @@ -1695,10 +1697,10 @@ static int vgic_v3_domain_init(struct domain *d) } =20 /* - * The hardware domain may not use all the re-distributors - * regions (e.g when the number of vCPUs does not match the - * number of pCPUs). Update the number of regions to avoid - * exposing unused region as they will not get emulated. + * For domain using the host memory layout, it may not use all + * the re-distributors regions (e.g when the number of vCPUs does + * not match the number of pCPUs). Update the number of regions to + * avoid exposing unused region as they will not get emulated. */ d->arch.vgic.nr_regions =3D i + 1; =20 --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=arm.com); dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=2; a=rsa-sha256; t=1639977773; cv=pass; d=zohomail.com; s=zohoarc; b=abPNMc3gzW1BF9D3SOvu2SRlXQeA9yFsFpXI6bXm0k0yhD2TLIgOZ2bhqI+E1SXXospxSXBPLBn9cKhS6kvfcVqpTZ1SbP8SRMyiqsfrIP4MwucmhfcuUt43fJCr3IUrGtDQ2Il+xOi/o1waFQtSjj0MyyAss4kwNN3Uv8CE7u4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639977773; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 10/11] xen/arm: if direct-map domain use native UART address and IRQ number for vPL011 Date: Mon, 20 Dec 2021 05:21:22 +0000 Message-ID: <20211220052123.969876-11-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 10d9e2d1-f2f8-4703-3510-08d9c378acee X-MS-TrafficTypeDiagnostic: AM0PR08MB3697:EE_|DB5EUR03FT017:EE_|DB9PR08MB6474:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:10000;OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: ozBGj7WK7zeVxW2xL1KiKYOgd8sY9qqGmcDn8JVnd0U0gUI4HsJ01c2N+2ykgNj/tKTkv+r+T9iwDByaLD4RoFt/pCzOfXp0HZPp60BGXYrh/8PfpZKPPQ7uurZmRMStYjAMH8yh1ItvnzHkEOLvO6+F97HH0bkr+FNMcfWaZGyA4y2c8kdlC71H4fB+OgtRW8Jd5gCe/UpolnPwmoG4T5IIRWICkFfIILgs8WW3S88jtwAAas+YrZPuLoVX3lDzPnFpnndlcNSNl+fXF7TBO9hSnf2Ca9oXFGABiuORXH5b7oXJUacCHBNx1dSAjfbBCv54keHosNW2HaXimYMLfIckEQ1/8Rau2wfltzUEgz5JU7BUxiEIzGFcV4BdouiYrH8mGerFfRSzwKm0uEwIIsdWXm/G+vGb4lRhCpHmLjHIjkzevrLRO6WyVw99K0Z2QcNlk3u8r7tGoZBe8e/j0CGJYykYYyZpuX+Bgbnp6kKmvhab6AQIKKtoUV3WjIDeS17AtkmAlaDNL1OlEJE15BiowjM+FBrUV99ldn9uEx3p5eF66J61lu7mWQJuHU+2qzD1f9MAIdmPDpYxS0EwBc+UjWUKM1gxy/MVp0KNB1vqDv9nk/zp4vYJIAKlrwHNwAvPvr5ASf4tBcEgUbw7nh2FfGigNAKrnMRfO/dC+89XUXWNDoMfpplyz+Hn/o4kOn30paxiHRPliSW17phfZb0pDUbfRjC6xhAqhie8jdsXOLQGx+Ic8c4iXTM8NKNldG9Q8JtVSfd6idiD55xIoIJQ7JU8ma1HhN+62GEIcFo= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(70586007)(2906002)(110136005)(8936002)(47076005)(70206006)(7696005)(316002)(54906003)(36756003)(426003)(44832011)(6666004)(36860700001)(8676002)(26005)(81166007)(356005)(86362001)(82310400004)(336012)(83380400001)(4326008)(1076003)(2616005)(186003)(508600001)(40460700001)(5660300002)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:22:11.4263 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10d9e2d1-f2f8-4703-3510-08d9c378acee X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT017.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6474 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639977774329100001 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini We always use a fix address to map the vPL011 to domains. The address could be a problem for direct-map domains. So, for domains that are directly mapped, reuse the address of the physical UART on the platform to avoid potential clashes. Do the same for the virtual IRQ number: instead of always using GUEST_VPL011_SPI, try to reuse the physical SPI number if possible. Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng --- v2 changes: - explain why vpl011 initialization before creating its device tree node - error out if the domain is direct-mapped and the IRQ is not found - harden the code and add a check/comment when the hardware UART region is smaller than GUEST_VPL011_SIZE. --- v3 changes: - explain how the '27' was found for 'buf' - fix checking before dereferencing - refine comment message --- v4 changes: - refine comment message --- xen/arch/arm/domain_build.c | 44 +++++++++++++++++++---- xen/arch/arm/include/asm/vpl011.h | 2 ++ xen/arch/arm/vpl011.c | 60 +++++++++++++++++++++++++++---- 3 files changed, 92 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 9a7145b3ee..a3196a4545 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -30,6 +30,7 @@ =20 #include #include +#include =20 static unsigned int __initdata opt_dom0_max_vcpus; integer_param("dom0_max_vcpus", opt_dom0_max_vcpus); @@ -2415,8 +2416,12 @@ static int __init make_vpl011_uart_node(struct kerne= l_info *kinfo) gic_interrupt_t intr; __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS]; __be32 *cells; + struct domain *d =3D kinfo->d; + /* Placeholder for sbsa-uart@ + a 64-bit number + \0 */ + char buf[27]; =20 - res =3D fdt_begin_node(fdt, "sbsa-uart@"__stringify(GUEST_PL011_BASE)); + snprintf(buf, sizeof(buf), "sbsa-uart@%"PRIx64, d->arch.vpl011.base_ad= dr); + res =3D fdt_begin_node(fdt, buf); if ( res ) return res; =20 @@ -2426,14 +2431,14 @@ static int __init make_vpl011_uart_node(struct kern= el_info *kinfo) =20 cells =3D ®[0]; dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, - GUEST_ROOT_SIZE_CELLS, GUEST_PL011_BASE, + GUEST_ROOT_SIZE_CELLS, d->arch.vpl011.base_addr, GUEST_PL011_SIZE); =20 res =3D fdt_property(fdt, "reg", reg, sizeof(reg)); if ( res ) return res; =20 - set_interrupt(intr, GUEST_VPL011_SPI, 0xf, DT_IRQ_TYPE_LEVEL_HIGH); + set_interrupt(intr, d->arch.vpl011.virq, 0xf, DT_IRQ_TYPE_LEVEL_HIGH); =20 res =3D fdt_property(fdt, "interrupts", intr, sizeof (intr)); if ( res ) @@ -3145,6 +3150,14 @@ static int __init construct_domU(struct domain *d, else assign_static_memory_11(d, &kinfo, node); =20 + /* + * Base address and irq number are needed when creating vpl011 device + * tree node in prepare_dtb_domU, so initialization on related variabl= es + * shall be done first. + */ + if ( kinfo.vpl011 ) + rc =3D domain_vpl011_init(d, NULL); + rc =3D prepare_dtb_domU(d, &kinfo); if ( rc < 0 ) return rc; @@ -3153,9 +3166,6 @@ static int __init construct_domU(struct domain *d, if ( rc < 0 ) return rc; =20 - if ( kinfo.vpl011 ) - rc =3D domain_vpl011_init(d, NULL); - return rc; } =20 @@ -3200,15 +3210,35 @@ void __init create_domUs(void) =20 if ( !dt_property_read_u32(node, "nr_spis", &d_cfg.arch.nr_spis) ) { + unsigned int vpl011_virq =3D GUEST_VPL011_SPI; + d_cfg.arch.nr_spis =3D gic_number_lines() - 32; =20 + /* + * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is + * set, in which case it'll match the hardware. + * + * Since the domain is not yet created, we can't use + * d->arch.vpl011.irq. So the logic to find the vIRQ has to + * be hardcoded. + * The logic here shall be consistent with the one in + * domain_vpl011_init(). + */ + if ( flags & CDF_directmap ) + { + vpl011_virq =3D serial_irq(SERHND_DTUART); + if ( vpl011_virq < 0 ) + panic("Error getting IRQ number for this serial port %= d\n", + SERHND_DTUART); + } + /* * vpl011 uses one emulated SPI. If vpl011 is requested, make * sure that we allocate enough SPIs for it. */ if ( dt_property_read_bool(node, "vpl011") ) d_cfg.arch.nr_spis =3D MAX(d_cfg.arch.nr_spis, - GUEST_VPL011_SPI - 32 + 1); + vpl011_virq - 32 + 1); } =20 /* diff --git a/xen/arch/arm/include/asm/vpl011.h b/xen/arch/arm/include/asm/v= pl011.h index e6c7ab7381..c09abcd7a9 100644 --- a/xen/arch/arm/include/asm/vpl011.h +++ b/xen/arch/arm/include/asm/vpl011.h @@ -53,6 +53,8 @@ struct vpl011 { uint32_t uarticr; /* Interrupt clear register */ uint32_t uartris; /* Raw interrupt status register */ uint32_t shadow_uartmis; /* shadow masked interrupt register */ + paddr_t base_addr; + unsigned int virq; spinlock_t lock; evtchn_port_t evtchn; }; diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 895f436cc4..43522d48fd 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -71,11 +72,11 @@ static void vpl011_update_interrupt_status(struct domai= n *d) * status bit has been set since the last time. */ if ( uartmis & ~vpl011->shadow_uartmis ) - vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true); + vgic_inject_irq(d, NULL, vpl011->virq, true); =20 vpl011->shadow_uartmis =3D uartmis; #else - vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, uartmis); + vgic_inject_irq(d, NULL, vpl011->virq, uartmis); #endif } =20 @@ -347,7 +348,8 @@ static int vpl011_mmio_read(struct vcpu *v, void *priv) { struct hsr_dabt dabt =3D info->dabt; - uint32_t vpl011_reg =3D (uint32_t)(info->gpa - GUEST_PL011_BASE); + uint32_t vpl011_reg =3D (uint32_t)(info->gpa - + v->domain->arch.vpl011.base_addr); struct vpl011 *vpl011 =3D &v->domain->arch.vpl011; struct domain *d =3D v->domain; unsigned long flags; @@ -430,7 +432,8 @@ static int vpl011_mmio_write(struct vcpu *v, void *priv) { struct hsr_dabt dabt =3D info->dabt; - uint32_t vpl011_reg =3D (uint32_t)(info->gpa - GUEST_PL011_BASE); + uint32_t vpl011_reg =3D (uint32_t)(info->gpa - + v->domain->arch.vpl011.base_addr); struct vpl011 *vpl011 =3D &v->domain->arch.vpl011; struct domain *d =3D v->domain; unsigned long flags; @@ -626,6 +629,49 @@ int domain_vpl011_init(struct domain *d, struct vpl011= _init_info *info) if ( vpl011->backend.dom.ring_buf ) return -EINVAL; =20 + /* + * The VPL011 virq is GUEST_VPL011_SPI, except for direct-map domains + * where the hardware value shall be used. + * The logic here should stay in sync with the one in + * create_domUs(). + */ + if ( is_domain_direct_mapped(d) ) + { + const struct vuart_info *uart =3D serial_vuart_info(SERHND_DTUART); + int vpl011_irq =3D serial_irq(SERHND_DTUART); + + if ( (uart !=3D NULL) && (vpl011_irq > 0) ) + { + vpl011->base_addr =3D uart->base_addr; + vpl011->virq =3D vpl011_irq; + } + else + { + printk(XENLOG_ERR + "vpl011: Unable to re-use the Xen UART information.\n"); + return -EINVAL; + } + + /* + * Since the PL011 we emulate for the guest requires a 4KB region, + * and on some Hardware (e.g. on some sunxi SoC), the UART MMIO + * region is less than 4KB, in which case, there may exist multiple + * devices within the same 4KB region, here adds the following che= ck to + * prevent potential known pitfalls + */ + if ( uart->size < GUEST_PL011_SIZE ) + { + printk(XENLOG_ERR + "vpl011: Can't re-use the Xen UART MMIO region as it is= too small.\n"); + return -EINVAL; + } + } + else + { + vpl011->base_addr =3D GUEST_PL011_BASE; + vpl011->virq =3D GUEST_VPL011_SPI; + } + /* * info is NULL when the backend is in Xen. * info is !=3D NULL when the backend is in a domain. @@ -661,7 +707,7 @@ int domain_vpl011_init(struct domain *d, struct vpl011_= init_info *info) } } =20 - rc =3D vgic_reserve_virq(d, GUEST_VPL011_SPI); + rc =3D vgic_reserve_virq(d, vpl011->virq); if ( !rc ) { rc =3D -EINVAL; @@ -673,12 +719,12 @@ int domain_vpl011_init(struct domain *d, struct vpl01= 1_init_info *info) spin_lock_init(&vpl011->lock); =20 register_mmio_handler(d, &vpl011_mmio_handler, - GUEST_PL011_BASE, GUEST_PL011_SIZE, NULL); + vpl011->base_addr, GUEST_PL011_SIZE, NULL); =20 return 0; =20 out2: - vgic_free_virq(d, GUEST_VPL011_SPI); + vgic_free_virq(d, vpl011->virq); =20 out1: if ( vpl011->backend_in_domain ) --=20 2.25.1 From nobody Sat May 4 22:59:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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helo=nebula.arm.com; From: Penny Zheng To: , , CC: , Subject: [PATCH v4 11/11] xen/docs: Document how to do passthrough without IOMMU Date: Mon, 20 Dec 2021 05:21:23 +0000 Message-ID: <20211220052123.969876-12-penny.zheng@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211220052123.969876-1-penny.zheng@arm.com> References: <20211220052123.969876-1-penny.zheng@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 3538d98f-5961-45e6-02d8-08d9c378b2a9 X-MS-TrafficTypeDiagnostic: AM9PR08MB5892:EE_|AM5EUR03FT004:EE_|PA4PR08MB7386:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:1751;OLM:1751; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Xh8+scXtx6hjAb9d3K95WinV5/qfWhUWBtb7FK8U5NR8FV/8WEesRWcbCwUDw50wOIdi6PA+0t1vjux/ty2sS2TGPAtaI7W7qqlLk3/ZZ4NS21hq6tAturoXY4YfaG3fGj7OO4XgUcBKl2BvMViY18nw+nhKE5p+vvaRO5bheGOtZuU8J9udRSGaBOrchU1UThngfxve4JPDYAqC43in/g9KuU796PW7v5kVdMXKQlEdhlWcZPUrzT8qcKjJdMQIDDbdZTk4vKsg5zMc7zB4fGY/mub3I646swz5YxJAabn+Uz1Ajq7VuwYkpKimmK4LHxMxQSCVIhOHg431optACxeKDi/lvfwt+jrFeiTASg3yZjSlfm6uARuvMGEjcNKT0K9TL94fx0YFhLoqPRyXavZWsG8ElukluDE7f5BJ0mdi6eDaLkyoyuHAT86qbcfSyvQEbi4si3kCinLk4UN4Ks90xgVwk40dIMQ4z2KgbJl9tuDYzDD8ymYG+oh3iMoua4TvYOFKbZlYh4tiztrKbQH+TBNSFoDEXnjwPeSSu8QRAnKCtT7KrD9Pv3AAPlKyObkVm7SfLY2HLmjw+jmVbLbAtQmydHDjYLxvp0zHJf1YVzErjsa6gdTWXAU1DttezUvleEeXhPt3TeLEmfEdDhNJgfsbOXqhMUx+p3a+zo29Q5w78xNaOdo85HMQxSJC/Y3Jl9sM/pYEERS6IStEzZ4IfsmSjwjlLFPjMFp/LfqiuitGTfYHi+o0OwN+kj/ySPy0ZRH+F2IlbSita4FvvyC6I5oiQlaWE1PS6/6msUI= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(40470700001)(356005)(54906003)(81166007)(110136005)(70206006)(70586007)(36756003)(26005)(7696005)(316002)(2906002)(86362001)(1076003)(426003)(336012)(2616005)(4326008)(83380400001)(44832011)(186003)(36860700001)(508600001)(82310400004)(5660300002)(6666004)(47076005)(8936002)(8676002)(40460700001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2021 05:22:20.9923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3538d98f-5961-45e6-02d8-08d9c378b2a9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB7386 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) X-ZM-MESSAGEID: 1639978173585100003 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini This commit creates a new doc to document how to do passthrough without IOM= MU. Signed-off-by: Stefano Stabellini Signed-off-by: Penny Zheng --- docs/misc/arm/passthrough-noiommu.txt | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 docs/misc/arm/passthrough-noiommu.txt diff --git a/docs/misc/arm/passthrough-noiommu.txt b/docs/misc/arm/passthro= ugh-noiommu.txt new file mode 100644 index 0000000000..3e2ef21ad7 --- /dev/null +++ b/docs/misc/arm/passthrough-noiommu.txt @@ -0,0 +1,52 @@ +Request Device Assignment without IOMMU support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +*WARNING: +Users should be aware that it is not always secure to assign a device with= out +IOMMU protection. +When the device is not protected by the IOMMU, the administrator should ma= ke +sure that: + 1. The device is assigned to a trusted guest. + 2. Users have additional security mechanism on the platform. + +This document assumes that the IOMMU is absent from the system or it is +disabled (status =3D "disabled" in device tree). + +Add xen,force-assign-without-iommu; to the device tree snippet: + +ethernet: ethernet@ff0e0000 { + compatible =3D "cdns,zynqmp-gem"; + xen,path =3D "/amba/ethernet@ff0e0000"; + xen,reg =3D <0x0 0xff0e0000 0x1000 0x0 0xff0e0000>; + xen,force-assign-without-iommu; +}; + +Request 1:1 memory mapping for the domain on static allocation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Add a direct-map property under the appropriate /chosen/domU node which +is also statically allocated with physical memory ranges through +xen,static-mem property as its guest RAM. + +Below is an example on how to specify the 1:1 memory mapping for the domain +on static allocation in the device-tree: + +/ { + chosen { + domU1 { + compatible =3D "xen,domain"; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + cpus =3D <2>; + memory =3D <0x0 0x80000>; + #xen,static-mem-address-cells =3D <0x1>; + #xen,static-mem-size-cells =3D <0x1>; + xen,static-mem =3D <0x30000000 0x20000000>; + direct-map; + ... + }; + }; +}; + +Besides reserving a 512MB region starting at the host physical address +0x30000000 to DomU1, it also requests 1:1 memory mapping. --=20 2.25.1