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d="scan'208";a="62205277" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 4/4] x86/cpuid: Advertise SERIALIZE by default to guests Date: Wed, 15 Dec 2021 22:21:15 +0000 Message-ID: <20211215222115.6829-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20211215222115.6829-1-andrew.cooper3@citrix.com> References: <20211215222115.6829-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1639606941678100001 I've played with SERIALIZE, TSXLDTRK, MOVDIRI and MOVDIR64 on real hardware, and they all seem fine, including emulation support. SERIALIZE exists specifically to have a userspace usable serialising operat= ion without other side effects. (The only other two choices are CPUID which is= a VMExit under virt and clobbers 4 registers, and IRET-to-self which very slow and consumes content from the stack.) TSXLDTRK is a niche TSX feature, and TSX itself is niche outside of demos of speculative sidechannels. Leave the feature opt-in until a usecase is foun= d, in an effort to preempt the multiple person years of effort it has taken to mop up TSX issues impacting every processor line. MOVDIRI and MOVDIR64 are harder to judge. They're architectural building blocks towards ENQCMD{,S} without obvious usecases on their own. They're of no use to domains without PCI devices, so leave them opt-in for now. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu v2: * New --- xen/include/public/arch-x86/cpufeatureset.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 647ee9e5e277..0b399375566f 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -278,7 +278,7 @@ XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT= _CTRL and RNGDS_MITG_DIS. XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural= buffers */ XEN_CPUFEATURE(RTM_ALWAYS_ABORT, 9*32+11) /*! June 2021 TSX defeaturing in= microcode. */ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT = */ -XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */ +XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*A SERIALIZE insn */ XEN_CPUFEATURE(TSXLDTRK, 9*32+16) /*a TSX load tracking suspend/resu= me insns */ XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking= */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by= Intel) */ --=20 2.11.0