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helo=lists.xenproject.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.80.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.80.198; helo=xir-pvapexch01.xlnx.xilinx.com; From: Ayan Kumar Halder To: CC: , , , , , , , Ayan Kumar Halder Subject: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions Date: Mon, 29 Nov 2021 19:16:38 +0000 Message-ID: <20211129191638.19877-1-ayankuma@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98830770-7562-4825-2884-08d9b36cc80f X-MS-TrafficTypeDiagnostic: DM6PR02MB4794: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 46F+fYslL+Ak+hav5XKF9KrCN3EqrKckzyonLftpblYNc+kbZLAgnPDtvcyemimCFOtK7AxyXg1UUmGiY1C4d/JgA8ycT7oqbeVqhjWGDwo/Oh37X4R7/g8mdUh9T5ak+M7Jc0VFPILfdTtKfuIft3s8VgadiF8PzU0GzdUyejSDAck6yDtNzHyAdBOrC3q8muYWjAwCOpNwPTRj9HcLMAYTTu1cABDJB4jl1v1EWR0i40ZHR8lnqj2jz7LgKOTuDQdlPeiH7pJTVd4Yceg+FVHv8IQwoftAP1Acd1xRTA8lOm7s5P4+dEOO5JlMyYwYF9G1PUHVO9vowWQ0xfuxsQQZJ3aDExHmEU0ToSgo8r+yaM3lldQDU9yo7dNmDECQJZKD+1h7KNhUFnkqoDrNYWCwG1RjBLFuk13wJgDsksXW8gbHQrkGy1PREyTo2TrfNdeV1dIJzb+49T9rK6fzwCLFBTBeBbzR5RoKLuP+5KpKvK25qFp3SIyfR4HzfsOF8LcjWBWhxnLj5xsx+0rte5w9ll1krIWDKOrjh3aHpP3Kp6YIStd+hlQme0FErc8HEBiYCy7DgKzJO15ydZ+vZfB+ztHZgQmD5D1ZwIKZondJLpimJF1AsF4qBOx/QpRC9A+2E5Jaklver7m2yy8A+aV4wqg9rmi16yDHzmby4Um+tznmYQz7R1rj41+YiIyDwCuU7wLjq+l3qgbM8/IEX9nBd1a7CNiv4zUjahv+73U= X-Forefront-Antispam-Report: CIP:149.199.80.198;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:xir-pvapexch01.xlnx.xilinx.com;PTR:unknown-80-198.xilinx.com;CAT:NONE;SFS:(36840700001)(46966006)(2906002)(36860700001)(83380400001)(82310400004)(7696005)(70586007)(107886003)(4326008)(47076005)(1076003)(54906003)(70206006)(7636003)(2616005)(356005)(186003)(508600001)(5660300002)(9786002)(8936002)(426003)(6666004)(36756003)(6916009)(26005)(316002)(8676002)(336012)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2021 19:16:44.1693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98830770-7562-4825-2884-08d9b36cc80f X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.80.198];Helo=[xir-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT061.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB4794 X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) X-ZM-MESSAGEID: 1638213457285100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the moment, Xen is only handling data abort with valid syndrome (i.e. ISV=3D0). Unfortunately, this doesn't cover all the instructions a domain could use to access MMIO regions. For instance, Xilinx baremetal OS will use: volatile u32 *LocalAddr =3D (volatile u32 *)Addr; *LocalAddr =3D Value; This leave the compiler to decide which store instructions to use. This may be a post-index store instruction where the HW will not provide a valid syndrome. In order to handle post-indexing store/load instructions, Xen will need to fetch and decode the instruction. This patch only cover post-index store/load instructions from AArch64 mode. For now, this is left unimplemented for trap from AArch32 mode. Signed-off-by: Ayan Kumar Halder --- Changelog :- v2 :- 1. Updated the rn register after reading from it. (Pointed by Julien, Stefano) 2. Used a union to represent the instruction opcode (Suggestd by Bertrand) 3. Fixed coding style issues (Pointed by Julien) 4. In the previous patch, I was updating dabt->sign based on the signedness= of imm9. This was incorrect. As mentioned in ARMv8 ARM DDI 0487G.b, Page 3221, SSE indicates the signedness of the data item loaded. In our case, the data= item loaded is always unsigned. This has been tested for the following cases :- ldr x2, [x1], #4 ldr w2, [x1], #-4 str x2, [x1], #4 str w2, [x1], #-4 The reason being I am testing on 32bit MMIO registers only. I don't see a = 8bit or 16bit MMIO register. xen/arch/arm/decode.c | 68 ++++++++++++++++++++++++++++++++++++++- xen/arch/arm/decode.h | 3 +- xen/arch/arm/io.c | 40 +++++++++++++++++++---- xen/include/asm-arm/hsr.h | 26 +++++++++++++++ 4 files changed, 129 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c index 792c2e92a7..0b3e8fcbc6 100644 --- a/xen/arch/arm/decode.c +++ b/xen/arch/arm/decode.c @@ -84,6 +84,66 @@ bad_thumb2: return 1; } =20 +static int decode_32bit_loadstore_postindexing(register_t pc, + struct hsr_dabt *dabt, + union ldr_str_instr_class *= instr) +{ + if ( raw_copy_from_guest(&instr->value, (void * __user)pc, sizeof (ins= tr)) ) + return -EFAULT; + + /* First, let's check for the fixed values */ + if ( !((instr->code.fixed1 =3D=3D 1) && (instr->code.fixed2 =3D=3D 0) = && + (instr->code.fixed3 =3D=3D 0) && (instr->code.fixed4 =3D=3D 7)) ) + { + gprintk(XENLOG_ERR, "Decoding not supported for instructions other= than" + " ldr/str post indexing\n"); + goto bad_32bit_loadstore; + } + + if ( instr->code.size !=3D 2 ) + { + gprintk(XENLOG_ERR, + "ldr/str post indexing is supported for 32 bit variant only\n"= ); + goto bad_32bit_loadstore; + } + + if ( instr->code.v !=3D 0 ) + { + gprintk(XENLOG_ERR, + "ldr/str post indexing for vector types are not supported\n"); + goto bad_32bit_loadstore; + } + + /* Check for STR (immediate) - 32 bit variant */ + if ( instr->code.opc =3D=3D 0 ) + { + dabt->write =3D 1; + } + /* Check for LDR (immediate) - 32 bit variant */ + else if ( instr->code.opc =3D=3D 1 ) + { + dabt->write =3D 0; + } + else + { + gprintk(XENLOG_ERR, + "Decoding ldr/str post indexing is not supported for this vari= ant\n"); + goto bad_32bit_loadstore; + } + + gprintk(XENLOG_INFO, + "instr->code.rt =3D 0x%x, instr->code.size =3D 0x%x, instr->code.i= mm9 =3D %d\n", + instr->code.rt, instr->code.size, instr->code.imm9); + + update_dabt(dabt, instr->code.rt, instr->code.size, false); + dabt->valid =3D 1; + + return 0; +bad_32bit_loadstore: + gprintk(XENLOG_ERR, "unhandled 32bit Arm instruction 0x%x\n", instr->v= alue); + return 1; +} + static int decode_thumb(register_t pc, struct hsr_dabt *dabt) { uint16_t instr; @@ -150,11 +210,17 @@ bad_thumb: return 1; } =20 -int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt) +int decode_instruction(const struct cpu_user_regs *regs, struct hsr_dabt *= dabt, + union ldr_str_instr_class *instr) { if ( is_32bit_domain(current->domain) && regs->cpsr & PSR_THUMB ) return decode_thumb(regs->pc, dabt); =20 + if ( (is_64bit_domain(current->domain) && !psr_mode_is_32bit(regs)) ) + { + return decode_32bit_loadstore_postindexing(regs->pc, dabt, instr); + } + /* TODO: Handle ARM instruction */ gprintk(XENLOG_ERR, "unhandled ARM instruction\n"); =20 diff --git a/xen/arch/arm/decode.h b/xen/arch/arm/decode.h index 4613763bdb..d82fc4a0f6 100644 --- a/xen/arch/arm/decode.h +++ b/xen/arch/arm/decode.h @@ -35,7 +35,8 @@ */ =20 int decode_instruction(const struct cpu_user_regs *regs, - struct hsr_dabt *dabt); + struct hsr_dabt *dabt, + union ldr_str_instr_class *instr); =20 #endif /* __ARCH_ARM_DECODE_H_ */ =20 diff --git a/xen/arch/arm/io.c b/xen/arch/arm/io.c index 729287e37c..0d60754bc4 100644 --- a/xen/arch/arm/io.c +++ b/xen/arch/arm/io.c @@ -65,6 +65,16 @@ static enum io_state handle_write(const struct mmio_hand= ler *handler, return ret ? IO_HANDLED : IO_ABORT; } =20 +static void post_incremenet_register(union ldr_str_instr_class *instr) +{ + struct cpu_user_regs *regs =3D guest_cpu_user_regs(); + unsigned int val; + + val =3D get_user_reg(regs, instr->code.rn); + val +=3D instr->code.imm9; + set_user_reg(regs, instr->code.rn, val); +} + /* This function assumes that mmio regions are not overlapped */ static int cmp_mmio_handler(const void *key, const void *elem) { @@ -106,14 +116,26 @@ enum io_state try_handle_mmio(struct cpu_user_regs *r= egs, .gpa =3D gpa, .dabt =3D dabt }; + int rc; + union ldr_str_instr_class instr =3D {0}; =20 ASSERT(hsr.ec =3D=3D HSR_EC_DATA_ABORT_LOWER_EL); =20 + /* + * Armv8 processor does not provide a valid syndrome for post-indexing + * ldr/str instructions. So in order to process these instructions, + * Xen must decode them. + */ + if ( !info.dabt.valid ) + { + rc =3D decode_instruction(regs, &info.dabt, &instr); + if ( rc ) + return IO_ABORT; + } + handler =3D find_mmio_handler(v->domain, info.gpa); if ( !handler ) { - int rc; - rc =3D try_fwd_ioserv(regs, v, &info); if ( rc =3D=3D IO_HANDLED ) return handle_ioserv(regs, v); @@ -122,7 +144,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, } =20 /* All the instructions used on emulated MMIO region should be valid */ - if ( !dabt.valid ) + if ( !info.dabt.valid ) return IO_ABORT; =20 /* @@ -134,7 +156,7 @@ enum io_state try_handle_mmio(struct cpu_user_regs *reg= s, { int rc; =20 - rc =3D decode_instruction(regs, &info.dabt); + rc =3D decode_instruction(regs, &info.dabt, NULL); if ( rc ) { gprintk(XENLOG_DEBUG, "Unable to decode instruction\n"); @@ -143,9 +165,15 @@ enum io_state try_handle_mmio(struct cpu_user_regs *re= gs, } =20 if ( info.dabt.write ) - return handle_write(handler, v, &info); + rc =3D handle_write(handler, v, &info); else - return handle_read(handler, v, &info); + rc =3D handle_read(handler, v, &info); + + if ( instr.value !=3D 0 ) + { + post_incremenet_register(&instr); + } + return rc; } =20 void register_mmio_handler(struct domain *d, diff --git a/xen/include/asm-arm/hsr.h b/xen/include/asm-arm/hsr.h index 9b91b28c48..72d67d2801 100644 --- a/xen/include/asm-arm/hsr.h +++ b/xen/include/asm-arm/hsr.h @@ -15,6 +15,32 @@ enum dabt_size { DABT_DOUBLE_WORD =3D 3, }; =20 +/* + * Refer to the ARMv8 ARM (DDI 0487G.b), Section C4.1.4 Loads and Stores + * Page 318 specifies the following bit pattern for + * "load/store register (immediate post-indexed)". + * + * 31 30 29 27 26 25 23 21 20 11 9 4 0 + * ___________________________________________________________________ + * |size|1 1 1 |V |0 0 |opc |0 | imm9 |0 1 | Rn | Rt | + * |____|______|__|____|____|__|_______________|____|_________|_______| + */ +union ldr_str_instr_class { + uint32_t value; + struct ldr_str { + unsigned int rt:5; /* Rt register */ + unsigned int rn:5; /* Rn register */ + unsigned int fixed1:2; /* value =3D=3D 01b */ + int imm9:9; /* imm9 */ + unsigned int fixed2:1; /* value =3D=3D 0b */ + unsigned int opc:2; /* opc */ + unsigned int fixed3:2; /* value =3D=3D 00b */ + unsigned int v:1; /* vector */ + unsigned int fixed4:3; /* value =3D=3D 111b */ + unsigned int size:2; /* size */ + } code; +}; + union hsr { register_t bits; struct { --=20 2.17.1