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Note the legacy part of the introduced function, as long term Xen will require a proper topology setter function capable of expressing a more diverse set of topologies. No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 --- - s/xc_cpu_policy_topology/xc_cpu_policy_legacy_topology/ --- tools/include/xenguest.h | 4 + tools/libs/guest/xg_cpuid_x86.c | 186 +++++++++++++++++--------------- 2 files changed, 105 insertions(+), 85 deletions(-) diff --git a/tools/include/xenguest.h b/tools/include/xenguest.h index 281454dc60..bea02cb542 100644 --- a/tools/include/xenguest.h +++ b/tools/include/xenguest.h @@ -821,6 +821,10 @@ bool xc_cpu_policy_is_compatible(xc_interface *xch, xc= _cpu_policy_t *host, int xc_cpu_policy_make_compat_4_12(xc_interface *xch, xc_cpu_policy_t *pol= icy, bool hvm); =20 +/* Setup the legacy policy topology. */ +int xc_cpu_policy_legacy_topology(xc_interface *xch, xc_cpu_policy_t *poli= cy, + bool hvm); + int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps); int xc_get_cpu_featureset(xc_interface *xch, uint32_t index, uint32_t *nr_features, uint32_t *featureset); diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x8= 6.c index bcbf9576c4..eafc1ec7c1 100644 --- a/tools/libs/guest/xg_cpuid_x86.c +++ b/tools/libs/guest/xg_cpuid_x86.c @@ -429,13 +429,11 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t= domid, bool restore, { int rc; xc_dominfo_t di; - unsigned int i, nr_leaves, nr_msrs; + unsigned int nr_leaves, nr_msrs; xen_cpuid_leaf_t *leaves =3D NULL; struct cpuid_policy *p =3D NULL; struct xc_cpu_policy policy =3D { }; uint32_t err_leaf =3D -1, err_subleaf =3D -1, err_msr =3D -1; - uint32_t host_featureset[FEATURESET_NR_ENTRIES] =3D {}; - uint32_t len =3D ARRAY_SIZE(host_featureset); =20 if ( xc_domain_getinfo(xch, domid, 1, &di) !=3D 1 || di.domid !=3D domid ) @@ -458,22 +456,6 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t = domid, bool restore, (p =3D calloc(1, sizeof(*p))) =3D=3D NULL ) goto out; =20 - /* Get the host policy. */ - rc =3D xc_get_cpu_featureset(xch, XEN_SYSCTL_cpu_featureset_host, - &len, host_featureset); - if ( rc ) - { - /* Tolerate "buffer too small", as we've got the bits we need. */ - if ( errno =3D=3D ENOBUFS ) - rc =3D 0; - else - { - PERROR("Failed to obtain host featureset"); - rc =3D -errno; - goto out; - } - } - /* Get the domain's default policy. */ nr_msrs =3D 0; rc =3D get_system_cpu_policy(xch, di.hvm ? XEN_SYSCTL_cpu_policy_hvm_d= efault @@ -557,72 +539,11 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t= domid, bool restore, } } =20 - if ( !di.hvm ) - { - /* - * On hardware without CPUID Faulting, PV guests see real topology. - * As a consequence, they also need to see the host htt/cmp fields. - */ - p->basic.htt =3D test_bit(X86_FEATURE_HTT, host_featureset); - p->extd.cmp_legacy =3D test_bit(X86_FEATURE_CMP_LEGACY, host_featu= reset); - } - else - { - /* - * Topology for HVM guests is entirely controlled by Xen. For now= , we - * hardcode APIC_ID =3D vcpu_id * 2 to give the illusion of no SMT. - */ - p->basic.htt =3D true; - p->extd.cmp_legacy =3D false; - - /* - * Leaf 1 EBX[23:16] is Maximum Logical Processors Per Package. - * Update to reflect vLAPIC_ID =3D vCPU_ID * 2, but make sure to a= void - * overflow. - */ - if ( !p->basic.lppp ) - p->basic.lppp =3D 2; - else if ( !(p->basic.lppp & 0x80) ) - p->basic.lppp *=3D 2; - - switch ( p->x86_vendor ) - { - case X86_VENDOR_INTEL: - for ( i =3D 0; (p->cache.subleaf[i].type && - i < ARRAY_SIZE(p->cache.raw)); ++i ) - { - p->cache.subleaf[i].cores_per_package =3D - (p->cache.subleaf[i].cores_per_package << 1) | 1; - p->cache.subleaf[i].threads_per_cache =3D 0; - } - break; - - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: - /* - * Leaf 0x80000008 ECX[15:12] is ApicIdCoreSize. - * Leaf 0x80000008 ECX[7:0] is NumberOfCores (minus one). - * Update to reflect vLAPIC_ID =3D vCPU_ID * 2. But avoid - * - overflow, - * - going out of sync with leaf 1 EBX[23:16], - * - incrementing ApicIdCoreSize when it's zero (which changes= the - * meaning of bits 7:0). - * - * UPDATE: I addition to avoiding overflow, some - * proprietary operating systems have trouble with - * apic_id_size values greater than 7. Limit the value to - * 7 for now. - */ - if ( p->extd.nc < 0x7f ) - { - if ( p->extd.apic_id_size !=3D 0 && p->extd.apic_id_size <= 0x7 ) - p->extd.apic_id_size++; - - p->extd.nc =3D (p->extd.nc << 1) | 1; - } - break; - } - } + policy.cpuid =3D *p; + rc =3D xc_cpu_policy_legacy_topology(xch, &policy, di.hvm); + if ( rc ) + goto out; + *p =3D policy.cpuid; =20 rc =3D x86_cpuid_copy_to_buffer(p, leaves, &nr_leaves); if ( rc ) @@ -944,3 +865,98 @@ int xc_cpu_policy_make_compat_4_12(xc_interface *xch, = xc_cpu_policy_t *policy, xc_cpu_policy_destroy(host); return rc; } + +int xc_cpu_policy_legacy_topology(xc_interface *xch, xc_cpu_policy_t *poli= cy, + bool hvm) +{ + if ( !hvm ) + { + xc_cpu_policy_t *host; + int rc; + + host =3D xc_cpu_policy_init(); + if ( !host ) + { + errno =3D ENOMEM; + return -1; + } + + rc =3D xc_cpu_policy_get_system(xch, XEN_SYSCTL_cpu_policy_host, h= ost); + if ( rc ) + { + ERROR("Failed to get host policy"); + xc_cpu_policy_destroy(host); + return rc; + } + + + /* + * On hardware without CPUID Faulting, PV guests see real topology. + * As a consequence, they also need to see the host htt/cmp fields. + */ + policy->cpuid.basic.htt =3D host->cpuid.basic.htt; + policy->cpuid.extd.cmp_legacy =3D host->cpuid.extd.cmp_legacy; + } + else + { + unsigned int i; + + /* + * Topology for HVM guests is entirely controlled by Xen. For now= , we + * hardcode APIC_ID =3D vcpu_id * 2 to give the illusion of no SMT. + */ + policy->cpuid.basic.htt =3D true; + policy->cpuid.extd.cmp_legacy =3D false; + + /* + * Leaf 1 EBX[23:16] is Maximum Logical Processors Per Package. + * Update to reflect vLAPIC_ID =3D vCPU_ID * 2, but make sure to a= void + * overflow. + */ + if ( !policy->cpuid.basic.lppp ) + policy->cpuid.basic.lppp =3D 2; + else if ( !(policy->cpuid.basic.lppp & 0x80) ) + policy->cpuid.basic.lppp *=3D 2; + + switch ( policy->cpuid.x86_vendor ) + { + case X86_VENDOR_INTEL: + for ( i =3D 0; (policy->cpuid.cache.subleaf[i].type && + i < ARRAY_SIZE(policy->cpuid.cache.raw)); ++i ) + { + policy->cpuid.cache.subleaf[i].cores_per_package =3D + (policy->cpuid.cache.subleaf[i].cores_per_package << 1) = | 1; + policy->cpuid.cache.subleaf[i].threads_per_cache =3D 0; + } + break; + + case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: + /* + * Leaf 0x80000008 ECX[15:12] is ApicIdCoreSize. + * Leaf 0x80000008 ECX[7:0] is NumberOfCores (minus one). + * Update to reflect vLAPIC_ID =3D vCPU_ID * 2. But avoid + * - overflow, + * - going out of sync with leaf 1 EBX[23:16], + * - incrementing ApicIdCoreSize when it's zero (which changes= the + * meaning of bits 7:0). + * + * UPDATE: I addition to avoiding overflow, some + * proprietary operating systems have trouble with + * apic_id_size values greater than 7. Limit the value to + * 7 for now. + */ + if ( policy->cpuid.extd.nc < 0x7f ) + { + if ( policy->cpuid.extd.apic_id_size !=3D 0 && + policy->cpuid.extd.apic_id_size < 0x7 ) + policy->cpuid.extd.apic_id_size++; + + policy->cpuid.extd.nc =3D (policy->cpuid.extd.nc << 1) | 1; + } + break; + } + } + + return 0; +} --=20 2.33.0