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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id s15sm2202811wrb.22.2021.09.02.09.17.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Sep 2021 09:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wiJyFwIKRQWjRkbu8SvGMr1PDMKMIYamMV7C3BB8oe8=; b=qAtoFIb8zeHmLJ+DXBMGpAdnbrphpEAfuI7XHEPw8NBmRW9/+WQnP+AZelTqnIhAyE XWWklQ0ZgUaW+TjGyBKgrmT5Awe/DhMqWt5iYbHcpZayB/1OpJXxLIVgIBvvvx9tbfbe MhBhX16/hQ/XQpM8/t7IWpZx8Wn0h5lsCbsMip4ljj1E3unFy90cJy4UzhkEFnhbknkU T8DR04fw7m7nWgaHWphfTdeObgKvp0ylXJqEGEN6mGrqmeM1GzS3/abyks0gzOofcGN7 UjU06l66Hvh9mNoLvBN0ewV7GlShfdvdFlG07p47BqES4xriMHGxYVH/Zf/4POrSSA9s 8XQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wiJyFwIKRQWjRkbu8SvGMr1PDMKMIYamMV7C3BB8oe8=; b=Gs3lxVJBU4DAv12lkCVONPk+QGQ7qeDdWpnG+RrPs6+bhmsD/SFt4Yq//NHdv8EXP/ /FQFfWXzxJbvB4Vojk+UBIKSnS9UPVqM62AR0QEtgdPADwCVdSuuFrpzh/O/Q0xVb13M bw6G/fGUs43VPSQunbJwOD6LgIUjRprhAAkKCBfMMdDml+J9zUuh9A0Ns/k/o7XKxB6t syrZJOV1XcHp5wLRBUSy2ACeJ/2W7inh6fjhROjly8QnQA/Cw1c63laNMvbhhSy5lmLr jCaxDFzNQXc4ninpU4Fm8Ryb3IrgqOMkKAIjHhtW2ERCF4v9lCCUtRot6Y4RFF9ZH0Zv 8RxA== X-Gm-Message-State: AOAM531XB1I7tz6utl+EsQsm8bsW0RRMW6Iczx2cikmk8dlckKF2fkWM SALfHSCTUd0oRlVdpTQiYpY= X-Google-Smtp-Source: ABdhPJzK4QdOoxXsApVtGRumuSNyT10qkKd9QeSHbbUEQ3zItVBoCovI95FuxXm2STsnpfXGUzb9Vg== X-Received: by 2002:a5d:4ed0:: with SMTP id s16mr4776030wrv.71.1630599468354; Thu, 02 Sep 2021 09:17:48 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Eduardo Habkost , Greg Kurz , haxm-team@intel.com, Kamil Rytarowski , qemu-ppc@nongnu.org, Anthony Perard , Marcel Apfelbaum , Michael Rolnik , qemu-riscv@nongnu.org, Paolo Bonzini , Jiaxun Yang , Thomas Huth , David Hildenbrand , Chris Wulff , Laurent Vivier , Cameron Esfahani , Sunil Muthuswamy , Max Filippov , Taylor Simpson , qemu-s390x@nongnu.org, Richard Henderson , Bastian Koppelmann , Yoshinori Sato , Artyom Tarasenko , Aurelien Jarno , Paul Durrant , Peter Maydell , David Gibson , Alistair Francis , "Edgar E. Iglesias" , Roman Bolshakov , Laurent Vivier , Cornelia Huck , qemu-arm@nongnu.org, Wenchao Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , xen-devel@lists.xenproject.org, Marek Vasut , Stefano Stabellini , Aleksandar Rikalo , Mark Cave-Ayland , Colin Xu , Claudio Fontana , Palmer Dabbelt , Stafford Horne , Reinoud Zandijk , kvm@vger.kernel.org Subject: [PATCH v3 19/30] target/openrisc: Restrict has_work() handler to sysemu and TCG Date: Thu, 2 Sep 2021 18:15:32 +0200 Message-Id: <20210902161543.417092-20-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902161543.417092-1-f4bug@amsat.org> References: <20210902161543.417092-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1630599471031100001 Restrict has_work() to TCG sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27cb04152f9..6544b549f12 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -30,11 +30,13 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr val= ue) cpu->env.dflag =3D 0; } =20 +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool openrisc_cpu_has_work(CPUState *cs) { return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) { @@ -189,6 +191,7 @@ static const struct TCGCPUOps openrisc_tcg_ops =3D { .tlb_fill =3D openrisc_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY + .has_work =3D openrisc_cpu_has_work, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ @@ -205,7 +208,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_res= et); =20 cc->class_by_name =3D openrisc_cpu_class_by_name; - cc->has_work =3D openrisc_cpu_has_work; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; --=20 2.31.1