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d="scan'208";a="45958354" From: Andrew Cooper To: Xen-devel CC: Igor Druzhinin , Edwin Torok , Andrew Cooper , "Jan Beulich" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 1/5] x86/platform: Improve MSR permission handling for XENPF_resource_op Date: Fri, 11 Jun 2021 17:36:23 +0100 Message-ID: <20210611163627.4878-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210611163627.4878-1-andrew.cooper3@citrix.com> References: <20210611163627.4878-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) The logic to disallow writes to the TSC is out-of-place, and should be in check_resource_access() rather than in resource_access(). Split the existing allow_access_msr() into two - msr_{read,write}_allowed()= - and move all permissions checks here. Furthermore, guard access to MSR_IA32_CMT_{EVTSEL,CTR} to prohibit their use on hardware which is lacking the QoS Monitoring feature. Introduce cpu_has_pqe to help with the logic. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/platform_hypercall.c | 41 ++++++++++++++++++++++++++++-------= ---- xen/arch/x86/psr.c | 2 +- xen/include/asm-x86/cpufeature.h | 1 + 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 23fadbc782..41d8e59563 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -64,17 +64,33 @@ long cpu_frequency_change_helper(void *data) return cpu_frequency_change((uint64_t)data); } =20 -static bool allow_access_msr(unsigned int msr) +static bool msr_read_allowed(unsigned int msr) { switch ( msr ) { - /* MSR for CMT, refer to chapter 17.14 of Intel SDM. */ case MSR_IA32_CMT_EVTSEL: case MSR_IA32_CMT_CTR: + return cpu_has_pqe; + case MSR_IA32_TSC: return true; } =20 + if ( ppin_msr && msr =3D=3D ppin_msr ) + return true; + + return false; +} + +static bool msr_write_allowed(unsigned int msr) +{ + switch ( msr ) + { + case MSR_IA32_CMT_EVTSEL: + case MSR_IA32_CMT_CTR: + return cpu_has_pqe; + } + return false; } =20 @@ -96,15 +112,19 @@ void check_resource_access(struct resource_access *ra) switch ( entry->u.cmd ) { case XEN_RESOURCE_OP_MSR_READ: - if ( ppin_msr && entry->idx =3D=3D ppin_msr ) - break; - /* fall through */ + if ( entry->idx >> 32 ) + ret =3D -EINVAL; + else if ( !msr_read_allowed(entry->idx) ) + ret =3D -EPERM; + break; + case XEN_RESOURCE_OP_MSR_WRITE: if ( entry->idx >> 32 ) ret =3D -EINVAL; - else if ( !allow_access_msr(entry->idx) ) - ret =3D -EACCES; + else if ( !msr_write_allowed(entry->idx) ) + ret =3D -EPERM; break; + default: ret =3D -EOPNOTSUPP; break; @@ -163,12 +183,11 @@ void resource_access(void *info) } } break; + case XEN_RESOURCE_OP_MSR_WRITE: - if ( unlikely(entry->idx =3D=3D MSR_IA32_TSC) ) - ret =3D -EPERM; - else - ret =3D wrmsr_safe(entry->idx, entry->val); + ret =3D wrmsr_safe(entry->idx, entry->val); break; + default: BUG(); break; diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index d7f8864651..d805b85dc6 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -1558,7 +1558,7 @@ static void psr_cpu_init(void) struct cpuid_leaf regs; uint32_t feat_mask; =20 - if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) ) + if ( !psr_alloc_feat_enabled() || !cpu_has_pqe ) goto assoc_init; =20 if ( boot_cpu_data.cpuid_level < PSR_CPUID_LEVEL_CAT ) diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index a539a4bacd..5f6b83f71c 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -94,6 +94,7 @@ #define cpu_has_bmi2 boot_cpu_has(X86_FEATURE_BMI2) #define cpu_has_invpcid boot_cpu_has(X86_FEATURE_INVPCID) #define cpu_has_rtm boot_cpu_has(X86_FEATURE_RTM) +#define cpu_has_pqe boot_cpu_has(X86_FEATURE_PQE) #define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL)) #define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) #define cpu_has_avx512f boot_cpu_has(X86_FEATURE_AVX512F) --=20 2.11.0 From nobody Mon May 6 17:42:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) We are going to want this to write some tests with. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/platform_hypercall.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index 41d8e59563..284c2dfb9e 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -74,6 +74,12 @@ static bool msr_read_allowed(unsigned int msr) =20 case MSR_IA32_TSC: return true; + + case MSR_TSX_FORCE_ABORT: + return cpu_has_tsx_force_abort; + + case MSR_TSX_CTRL: + return cpu_has_tsx_ctrl; } =20 if ( ppin_msr && msr =3D=3D ppin_msr ) --=20 2.11.0 From nobody Mon May 6 17:42:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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d="scan'208";a="45692781" From: Andrew Cooper To: Xen-devel CC: Igor Druzhinin , Edwin Torok , Andrew Cooper , "Jan Beulich" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 3/5] x86/msr: Expose MSR_ARCH_CAPS in the raw and host policies Date: Fri, 11 Jun 2021 17:36:25 +0100 Message-ID: <20210611163627.4878-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210611163627.4878-1-andrew.cooper3@citrix.com> References: <20210611163627.4878-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) MSR_ARCH_CAPS is still not supported for guests (other than the hardware domain) yet, until the toolstack learns how to construct an MSR policy. However, we want access to the host ARCH_CAPS_TSX_CTRL value in particular = for testing purposes. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/msr.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 374f92b2c5..6dbb4744e7 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -47,8 +47,13 @@ struct msr_policy __read_mostly hvm_def_msr_policy; =20 static void __init calculate_raw_policy(void) { + struct msr_policy *mp =3D &raw_msr_policy; + /* 0x000000ce MSR_INTEL_PLATFORM_INFO */ /* Was already added by probe_cpuid_faulting() */ + + if ( cpu_has_arch_caps ) + rdmsrl(MSR_ARCH_CAPABILITIES, mp->arch_caps.raw); } =20 static void __init calculate_host_policy(void) @@ -60,6 +65,11 @@ static void __init calculate_host_policy(void) /* 0x000000ce MSR_INTEL_PLATFORM_INFO */ /* probe_cpuid_faulting() sanity checks presence of MISC_FEATURES_ENAB= LES */ mp->platform_info.cpuid_faulting =3D cpu_has_cpuid_faulting; + + mp->arch_caps.raw &=3D + (ARCH_CAPS_RDCL_NO | ARCH_CAPS_IBRS_ALL | ARCH_CAPS_RSBA | + ARCH_CAPS_SKIP_L1DFL | ARCH_CAPS_SSB_NO | ARCH_CAPS_MDS_NO | + ARCH_CAPS_IF_PSCHANGE_MC_NO | ARCH_CAPS_TSX_CTRL | ARCH_CAPS_TAA_= NO); } =20 static void __init calculate_pv_max_policy(void) @@ -67,6 +77,8 @@ static void __init calculate_pv_max_policy(void) struct msr_policy *mp =3D &pv_max_msr_policy; =20 *mp =3D host_msr_policy; + + mp->arch_caps.raw =3D 0; /* Not supported yet. */ } =20 static void __init calculate_pv_def_policy(void) @@ -84,6 +96,8 @@ static void __init calculate_hvm_max_policy(void) =20 /* It's always possible to emulate CPUID faulting for HVM guests */ mp->platform_info.cpuid_faulting =3D true; + + mp->arch_caps.raw =3D 0; /* Not supported yet. */ } =20 static void __init calculate_hvm_def_policy(void) --=20 2.11.0 From nobody Mon May 6 17:42:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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d="scan'208";a="45958359" From: Andrew Cooper To: Xen-devel CC: Igor Druzhinin , Edwin Torok , Andrew Cooper , "Jan Beulich" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 4/5] libs/guest: Move struct xc_cpu_policy into xg_private.h Date: Fri, 11 Jun 2021 17:36:26 +0100 Message-ID: <20210611163627.4878-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210611163627.4878-1-andrew.cooper3@citrix.com> References: <20210611163627.4878-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) ... so tests can peek at the internals, without the structure being general= ly available to users of the library. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- tools/libs/guest/xg_cpuid_x86.c | 11 +---------- tools/libs/guest/xg_private.h | 9 +++++++++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x8= 6.c index ec5a47fde4..e01d657e03 100644 --- a/tools/libs/guest/xg_cpuid_x86.c +++ b/tools/libs/guest/xg_cpuid_x86.c @@ -22,7 +22,7 @@ #include #include #include -#include "xc_private.h" +#include "xg_private.h" #include "xc_bitops.h" #include #include @@ -34,18 +34,9 @@ enum { =20 #include =20 -#include - #define bitmaskof(idx) (1u << ((idx) & 31)) #define featureword_of(idx) ((idx) >> 5) =20 -struct xc_cpu_policy { - struct cpuid_policy cpuid; - struct msr_policy msr; - xen_cpuid_leaf_t leaves[CPUID_MAX_SERIALISED_LEAVES]; - xen_msr_entry_t entries[MSR_MAX_SERIALISED_ENTRIES]; -}; - int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps) { DECLARE_SYSCTL; diff --git a/tools/libs/guest/xg_private.h b/tools/libs/guest/xg_private.h index 03d765da21..59909d2a2c 100644 --- a/tools/libs/guest/xg_private.h +++ b/tools/libs/guest/xg_private.h @@ -33,6 +33,8 @@ #include #include =20 +#include + #ifndef ELFSIZE #include #if UINT_MAX =3D=3D ULONG_MAX @@ -168,4 +170,11 @@ int pin_table(xc_interface *xch, unsigned int type, un= signed long mfn, #define M2P_SIZE(_m) ROUNDUP(((_m) * sizeof(xen_pfn_t)), M2P_SHIFT) #define M2P_CHUNKS(_m) (M2P_SIZE((_m)) >> M2P_SHIFT) =20 +struct xc_cpu_policy { + struct cpuid_policy cpuid; + struct msr_policy msr; + xen_cpuid_leaf_t leaves[CPUID_MAX_SERIALISED_LEAVES]; + xen_msr_entry_t entries[MSR_MAX_SERIALISED_ENTRIES]; +}; + #endif /* XG_PRIVATE_H */ --=20 2.11.0 From nobody Mon May 6 17:42:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Authentication-Results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: MdZ0hv6Rnx6nFYzpWf79xr1ooGPl9paJq9x07BdZ32fjjTBGHYCgCMvE4CCdlrh4fYLoWjB+ue 9BzEbHUDpmcwVv+oTt5psYGh8ElbhM8GL9Md1Vvrh+bR+DOloM+A6w93DOH7NeKz1eF+tArmRl 7PYxtCEVyLsKx3sUbjoAkNPZBvp12nc7BGfo6RvuiWNA/bXMoctHmhhFRyLH8X+I0XbMoyqx8Z biISeW4nAITWTjTfoB9IjKxC5A+9uSSkCzZmB+X+zDa2yRkjo3YMRcAUtpBAqGs0IX2r1lTTkt DgE= X-SBRS: 5.1 X-MesageID: 45958357 X-Ironport-Server: esa3.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED IronPort-HdrOrdr: A9a23:B1fo8KzIEkVSU3WJsJIUKrPwFr1zdoMgy1knxilNoRw8SK2lfq eV7YwmPH7P+U8ssR4b6LO90cW7Lk80sKQFhbX5Xo3SOjUO2lHYTr2KhLGKq1aLdkHDH6xmpM BdmsBFeabN5DNB7foSjjPXLz9Z+qjjzJyV X-IronPort-AV: E=Sophos;i="5.83,265,1616472000"; d="scan'208";a="45958357" From: Andrew Cooper To: Xen-devel CC: Igor Druzhinin , Edwin Torok , Andrew Cooper , "Jan Beulich" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 5/5] tests: Introduce a TSX test Date: Fri, 11 Jun 2021 17:36:27 +0100 Message-ID: <20210611163627.4878-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210611163627.4878-1-andrew.cooper3@citrix.com> References: <20210611163627.4878-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) See the comment at the top of test-tsx.c for details. This covers various complexities encountered while trying to address the recent TSX deprecation on client parts. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- tools/tests/Makefile | 1 + tools/tests/tsx/.gitignore | 1 + tools/tests/tsx/Makefile | 43 ++++ tools/tests/tsx/test-tsx.c | 474 +++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 519 insertions(+) create mode 100644 tools/tests/tsx/.gitignore create mode 100644 tools/tests/tsx/Makefile create mode 100644 tools/tests/tsx/test-tsx.c diff --git a/tools/tests/Makefile b/tools/tests/Makefile index 8746aabe6b..25531a984a 100644 --- a/tools/tests/Makefile +++ b/tools/tests/Makefile @@ -5,6 +5,7 @@ SUBDIRS-y :=3D SUBDIRS-y +=3D resource SUBDIRS-$(CONFIG_X86) +=3D cpu-policy SUBDIRS-$(CONFIG_X86) +=3D mce-test +SUBDIRS-$(CONFIG_X86) +=3D tsx ifneq ($(clang),y) SUBDIRS-$(CONFIG_X86) +=3D x86_emulator endif diff --git a/tools/tests/tsx/.gitignore b/tools/tests/tsx/.gitignore new file mode 100644 index 0000000000..97ec4db7ff --- /dev/null +++ b/tools/tests/tsx/.gitignore @@ -0,0 +1 @@ +test-tsx diff --git a/tools/tests/tsx/Makefile b/tools/tests/tsx/Makefile new file mode 100644 index 0000000000..7381a4f5a4 --- /dev/null +++ b/tools/tests/tsx/Makefile @@ -0,0 +1,43 @@ +XEN_ROOT =3D $(CURDIR)/../../.. +include $(XEN_ROOT)/tools/Rules.mk + +TARGET :=3D test-tsx + +.PHONY: all +all: $(TARGET) + +.PHONY: run +run: $(TARGET) + ./$(TARGET) + +.PHONY: clean +clean: + $(RM) -f -- *.o $(TARGET) $(DEPS_RM) + +.PHONY: distclean +distclean: clean + $(RM) -f -- *~ + +.PHONY: install +install: all + +.PHONY: uninstall +uninstall: + +CFLAGS +=3D -Werror -std=3Dgnu11 +CFLAGS +=3D $(CFLAGS_xeninclude) +CFLAGS +=3D $(CFLAGS_libxenctrl) +CFLAGS +=3D $(CFLAGS_libxenguest) +CFLAGS +=3D -I$(XEN_ROOT)/tools/libs/ctrl -I$(XEN_ROOT)/tools/libs/guest +CFLAGS +=3D $(APPEND_CFLAGS) + +LDFLAGS +=3D $(LDLIBS_libxenctrl) +LDFLAGS +=3D $(LDLIBS_libxenguest) +LDFLAGS +=3D $(APPEND_LDFLAGS) + +test-tsx.o: Makefile + +test-tsx: test-tsx.o + $(CC) -o $@ $< $(LDFLAGS) + +-include $(DEPS_INCLUDE) diff --git a/tools/tests/tsx/test-tsx.c b/tools/tests/tsx/test-tsx.c new file mode 100644 index 0000000000..2bf22cea81 --- /dev/null +++ b/tools/tests/tsx/test-tsx.c @@ -0,0 +1,474 @@ +/* + * TSX settings and consistency tests + * + * This tests various behaviours and invariants with regards to TSX. It + * ideally wants running for several microcode versions, and all applicable + * tsx=3D commandline settings, on a single CPU, including after an S3 + * suspend/resume event. + * + * It tests specifically: + * - The consistency of MSR_TSX_CTRL/MSR_TSX_FORCE_ABORT values across the + * system, and their accessibility WRT data in the host CPU policy. + * - The actual behaviour of RTM on the system. + * + * -=20 + */ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "xg_private.h" + +enum { +#define XEN_CPUFEATURE(name, value) X86_FEATURE_##name =3D value, +#include +}; +#define bitmaskof(idx) (1u << ((idx) & 31)) + +#define MSR_ARCH_CAPABILITIES 0x0000010a +#define ARCH_CAPS_TSX_CTRL (1 << 7) +#define MSR_TSX_FORCE_ABORT 0x0000010f +#define MSR_TSX_CTRL 0x00000122 + +static unsigned int nr_failures; +#define fail(fmt, ...) \ +({ \ + nr_failures++; \ + (void)printf(fmt, ##__VA_ARGS__); \ +}) + +static xc_interface *xch; + +/* + * Policies, arranged as an array for easy collection of all of them. We + * don't care about the raw policy (index 0) so reuse that for the guest + * policy. + */ +static struct xc_cpu_policy policies[6]; +#define guest_policy policies[0] +#define host policies[XEN_SYSCTL_cpu_policy_host] +#define pv_max policies[XEN_SYSCTL_cpu_policy_pv_max] +#define hvm_max policies[XEN_SYSCTL_cpu_policy_hvm_max] +#define pv_default policies[XEN_SYSCTL_cpu_policy_pv_default] +#define hvm_default policies[XEN_SYSCTL_cpu_policy_hvm_default] + +static bool xen_has_pv =3D true, xen_has_hvm =3D true; + +static unsigned int nr_cpus; +static enum rtm_behaviour { + RTM_UD, + RTM_OK, + RTM_ABORT, +} rtm_behaviour; + +/* + * Test a specific TSX MSR for consistency across the system, taking into + * account whether it ought to be accessable or not. + * + * We can't query offline CPUs, so skip those if encountered. We don't ca= re + * particularly for the exact MSR value, but we do care that it is the same + * everywhere. + */ +static void test_tsx_msr_consistency(unsigned int msr, bool accessable) +{ + uint64_t cpu0_val =3D ~0; + + for ( unsigned int cpu =3D 0; cpu < nr_cpus; ++cpu ) + { + xc_resource_entry_t ent =3D { + .u.cmd =3D XEN_RESOURCE_OP_MSR_READ, + .idx =3D msr, + }; + xc_resource_op_t op =3D { + .cpu =3D cpu, + .entries =3D &ent, + .nr_entries =3D 1, + }; + int rc =3D xc_resource_op(xch, 1, &op); + + if ( rc < 0 ) + { + /* Don't emit a message for offline CPUs */ + if ( errno !=3D ENODEV ) + fail(" xc_resource_op() for CPU%u failed: rc %d, errno %d= - %s\n", + cpu, rc, errno, strerror(errno)); + continue; + } + + if ( accessable ) + { + if ( rc !=3D 1 ) + { + fail(" Expected 1 result, got %u\n", rc); + continue; + } + if ( ent.u.ret !=3D 0 ) + { + fail(" Expected ok, got %d\n", ent.u.ret); + continue; + } + } + else + { + if ( rc !=3D 0 ) + fail(" Expected 0 results, got %u\n", rc); + else if ( ent.u.ret !=3D -EPERM ) + fail(" Expected -EPERM, got %d\n", ent.u.ret); + continue; + } + + if ( cpu =3D=3D 0 ) + { + cpu0_val =3D ent.val; + printf(" CPU0 val %#"PRIx64"\n", cpu0_val); + } + else if ( ent.val !=3D cpu0_val ) + fail(" CPU%u val %#"PRIx64" differes from CPU0 %#"PRIx64"\n", + cpu, ent.val, cpu0_val); + } +} + +/* + * Check all TSX MSRs, and in particular that their accessibility matches = what + * is expressed in the host CPU policy. + */ +static void test_tsx_msrs(void) +{ + printf("Testing MSR_TSX_FORCE_ABORT consistency\n"); + test_tsx_msr_consistency( + MSR_TSX_FORCE_ABORT, host.cpuid.feat.tsx_force_abort); + + printf("Testing MSR_TSX_CTRL consistency\n"); + test_tsx_msr_consistency( + MSR_TSX_CTRL, host.msr.arch_caps.tsx_ctrl); +} + +/* + * Probe for how RTM behaves, deliberately not inspecting CPUID. + * Distinguishes between "no support at all" (i.e. XBEGIN suffers #UD), + * working ok, and appearing to always abort. + */ +static enum rtm_behaviour probe_rtm_behaviour(void) +{ + for ( int i =3D 0; i < 1000; ++i ) + { + /* + * Opencoding the RTM infrastructure from immintrin.h, because we + * still support older versions of GCC. ALso so we can include #UD + * detection logic. + */ +#define XBEGIN_STARTED -1 +#define XBEGIN_UD -2 + unsigned int status =3D XBEGIN_STARTED; + + asm volatile (".Lxbegin: .byte 0xc7,0xf8,0,0,0,0" /* XBEGIN 1f; 1:= */ + : "+a" (status) :: "memory"); + if ( status =3D=3D XBEGIN_STARTED ) + { + asm volatile (".byte 0x0f,0x01,0xd5" ::: "memory"); /* XEND */ + return RTM_OK; + } + else if ( status =3D=3D XBEGIN_UD ) + return RTM_UD; + } + + return RTM_ABORT; +} + +static struct sigaction old_sigill; + +static void sigill_handler(int signo, siginfo_t *info, void *extra) +{ + extern char xbegin_label[] asm(".Lxbegin"); + + if ( info->si_addr =3D=3D xbegin_label || + memcmp(info->si_addr, "\xc7\xf8\x00\x00\x00\x00", 6) =3D=3D 0 ) + { + ucontext_t *context =3D extra; + + /* + * Found the XBEGIN instruction. Step over it, and update `status= ` to + * signal #UD. + */ +#ifdef __x86_64__ + context->uc_mcontext.gregs[REG_RIP] +=3D 6; + context->uc_mcontext.gregs[REG_RAX] =3D XBEGIN_UD; +#else + context->uc_mcontext.gregs[REG_EIP] +=3D 6; + context->uc_mcontext.gregs[REG_EAX] =3D XBEGIN_UD; +#endif + } + else + { + /* + * Not the SIGILL we're looking for... Restore the old handler and + * try again. Will likely coredump as a result. + */ + sigaction(SIGILL, &old_sigill, NULL); + } +} + +static void test_rtm_behaviour(void) +{ + struct sigaction new_sigill =3D { + .sa_flags =3D SA_SIGINFO, + .sa_sigaction =3D sigill_handler, + }; + const char *str; + + printf("Testing RTM behaviour\n"); + + /* + * Install a custom SIGILL handler while probing for RTM behaviour, as= the + * XBEGIN instruction might suffer #UD. + */ + sigaction(SIGILL, &new_sigill, &old_sigill); + rtm_behaviour =3D probe_rtm_behaviour(); + sigaction(SIGILL, &old_sigill, NULL); + + switch ( rtm_behaviour ) + { + case RTM_UD: str =3D "#UD"; break; + case RTM_OK: str =3D "OK"; break; + case RTM_ABORT: str =3D "Abort"; break; + default: str =3D NULL; break; + } + + if ( str ) + printf(" Got %s\n", str); + else + return fail(" Got unexpected behaviour %d\n", rtm_behaviour); + + if ( host.cpuid.feat.rtm ) + { + if ( rtm_behaviour =3D=3D RTM_UD ) + fail(" Host reports RTM, but appears unavailable\n"); + } + else + { + if ( rtm_behaviour !=3D RTM_UD ) + fail(" Host reports no RTM, but appears available\n"); + } +} + +static void dump_tsx_details(const struct xc_cpu_policy *p, const char *pr= ef) +{ + printf(" %s RTM %u, HLE %u, TSX_FORCE_ABORT %u, RTM_ALWAYS_ABORT %u, = TSX_CTRL %u\n", + pref, + p->cpuid.feat.rtm, + p->cpuid.feat.hle, + p->cpuid.feat.tsx_force_abort, + p->cpuid.feat.rtm_always_abort, + p->msr.arch_caps.tsx_ctrl + ); +} + +/* + * Sanity test various invariants we expect in the default/max policies. + */ +static void test_guest_policies(const struct xc_cpu_policy *max, + const struct xc_cpu_policy *def) +{ + const struct cpuid_policy *cm =3D &max->cpuid; + const struct cpuid_policy *cd =3D &def->cpuid; + const struct msr_policy *mm =3D &max->msr; + const struct msr_policy *md =3D &def->msr; + + dump_tsx_details(max, "Max:"); + dump_tsx_details(def, "Def:"); + + if ( ((cm->feat.raw[0].d | cd->feat.raw[0].d) & + (bitmaskof(X86_FEATURE_TSX_FORCE_ABORT) | + bitmaskof(X86_FEATURE_RTM_ALWAYS_ABORT))) || + ((mm->arch_caps.raw | md->arch_caps.raw) & ARCH_CAPS_TSX_CTRL) ) + fail(" Xen-only TSX controls offered to guest\n"); + + switch ( rtm_behaviour ) + { + case RTM_UD: + if ( (cm->feat.raw[0].b | cd->feat.raw[0].b) & + (bitmaskof(X86_FEATURE_HLE) | bitmaskof(X86_FEATURE_RTM)) ) + fail(" HLE/RTM offered to guests despite not being available= \n"); + break; + + case RTM_ABORT: + if ( cd->feat.raw[0].b & + (bitmaskof(X86_FEATURE_HLE) | bitmaskof(X86_FEATURE_RTM)) ) + fail(" HLE/RTM offered to guests by default despite not bein= g usable\n"); + break; + + case RTM_OK: + if ( !cm->feat.rtm || !cd->feat.rtm ) + fail(" RTM not offered to guests despite being available\n"); + break; + } + + if ( cd->feat.hle ) + fail(" Fail: HLE offered in default policy\n"); +} + +static void test_def_max_policies(void) +{ + if ( xen_has_pv ) + { + printf("Testing PV default/max policies\n"); + test_guest_policies(&pv_max, &pv_default); + } + + if ( xen_has_hvm ) + { + printf("Testing HVM default/max policies\n"); + test_guest_policies(&hvm_max, &hvm_default); + } +} + +static void test_guest(struct xen_domctl_createdomain *c) +{ + uint32_t domid =3D 0; + int rc; + + rc =3D xc_domain_create(xch, &domid, c); + if ( rc ) + return fail(" Domain create failure: %d - %s\n", + errno, strerror(errno)); + + printf(" Created d%u\n", domid); + + rc =3D xc_cpu_policy_get_domain(xch, domid, &guest_policy); + if ( rc ) + { + fail(" Failed to obtain domain policy: %d - %s\n", + errno, strerror(errno)); + goto out; + } + + dump_tsx_details(&guest_policy, "Cur:"); + + /* + * Check defaults given to the guest. + */ + if ( guest_policy.cpuid.feat.rtm !=3D (rtm_behaviour =3D=3D RTM_OK) ) + fail(" RTM %u in guest, despite rtm behaviour\n", + guest_policy.cpuid.feat.rtm); + + if ( guest_policy.cpuid.feat.hle || + guest_policy.cpuid.feat.tsx_force_abort || + guest_policy.cpuid.feat.rtm_always_abort || + guest_policy.msr.arch_caps.tsx_ctrl ) + fail(" Unexpected features advertised\n"); + + out: + rc =3D xc_domain_destroy(xch, domid); + if ( rc ) + fail(" Failed to destroy domain: %d - %s\n", + errno, strerror(errno)); +} + +static void test_guests(void) +{ + if ( xen_has_pv ) + { + struct xen_domctl_createdomain c =3D { + .max_vcpus =3D 1, + .max_grant_frames =3D 1, + }; + + printf("Testing PV guest\n"); + test_guest(&c); + } + + if ( xen_has_hvm ) + { + struct xen_domctl_createdomain c =3D { + .flags =3D XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap, + .max_vcpus =3D 1, + .max_grant_frames =3D 1, + .arch =3D { + .emulation_flags =3D XEN_X86_EMU_LAPIC, + }, + }; + + printf("Testing HVM guest\n"); + test_guest(&c); + } +} + +/* Obtain some general data, then run the tests. */ +static void test_tsx(void) +{ + int rc; + xc_physinfo_t info =3D {}; + + /* Read all policies except raw. */ + for ( int i =3D XEN_SYSCTL_cpu_policy_host; + i <=3D XEN_SYSCTL_cpu_policy_hvm_default; ++i ) + { + rc =3D xc_cpu_policy_get_system(xch, i, &policies[i]); + + if ( rc =3D=3D -1 && errno =3D=3D EOPNOTSUPP ) + { + /* + * Use EOPNOTSUPP to spot Xen missing CONFIG_{PV,HVM}, and adj= ust + * later testing accordingly. + */ + switch ( i ) + { + case XEN_SYSCTL_cpu_policy_pv_max: + case XEN_SYSCTL_cpu_policy_pv_default: + if ( xen_has_pv ) + printf(" Xen doesn't support PV\n"); + xen_has_pv =3D false; + continue; + + case XEN_SYSCTL_cpu_policy_hvm_max: + case XEN_SYSCTL_cpu_policy_hvm_default: + if ( xen_has_hvm ) + printf(" Xen doesn't support HVM\n"); + xen_has_hvm =3D false; + continue; + } + } + if ( rc ) + return fail("Failed to obtain policy[%u]: %d - %s\n", + i, errno, strerror(errno)); + } + + rc =3D xc_physinfo(xch, &info); + if ( rc ) + return fail("Failed to obtain physinfo: %d - %s\n", + errno, strerror(errno)); + + nr_cpus =3D info.max_cpu_id + 1; + printf(" Got %u CPUs\n", nr_cpus); + + test_tsx_msrs(); + test_rtm_behaviour(); + test_def_max_policies(); + test_guests(); +} + +int main(int argc, char **argv) +{ + printf("TSX tests\n"); + + xch =3D xc_interface_open(NULL, NULL, 0); + + if ( !xch ) + err(1, "xc_interface_open"); + + test_tsx(); + + return !!nr_failures; +} --=20 2.11.0