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d="scan'208";a="44745595" From: Andrew Cooper To: Xen-devel CC: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [PATCH 2/3] x86/tsx: Minor cleanup and improvements Date: Thu, 27 May 2021 14:25:18 +0100 Message-ID: <20210527132519.21730-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210527132519.21730-1-andrew.cooper3@citrix.com> References: <20210527132519.21730-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) * Introduce cpu_has_arch_caps and replace boot_cpu_has(X86_FEATURE_ARCH_CA= PS) * Read CPUID data into the appropriate boot_cpu_data.x86_capability[] element, as subsequent changes are going to need more cpu_has_* logic. * Use the hi/lo MSR helpers, which substantially improves code generation. No practical change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/cpuid.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/msr.c | 2 +- xen/arch/x86/spec_ctrl.c | 2 +- xen/arch/x86/tsx.c | 21 ++++++++++++--------- xen/include/asm-x86/cpufeature.h | 1 + 6 files changed, 17 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 55a7b16342..f3c8950aa3 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -747,7 +747,7 @@ int init_domain_cpuid_policy(struct domain *d) * so dom0 can turn off workarounds as appropriate. Temporary, until = the * domain policy logic gains a better understanding of MSRs. */ - if ( is_hardware_domain(d) && boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) + if ( is_hardware_domain(d) && cpu_has_arch_caps ) p->feat.arch_caps =3D true; =20 d->arch.cpuid =3D p; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 1450fd1991..7e3e67fdc3 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2566,7 +2566,7 @@ static bool __init has_if_pschange_mc(void) if ( cpu_has_hypervisor ) return false; =20 - if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) + if ( cpu_has_arch_caps ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); =20 if ( caps & ARCH_CAPS_IF_PSCHANGE_MC_NO ) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index c3a988bd11..374f92b2c5 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -136,7 +136,7 @@ int init_domain_msr_policy(struct domain *d) * so dom0 can turn off workarounds as appropriate. Temporary, until = the * domain policy logic gains a better understanding of MSRs. */ - if ( is_hardware_domain(d) && boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) + if ( is_hardware_domain(d) && cpu_has_arch_caps ) { uint64_t val; =20 diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index f2782b2d55..739b7913ff 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -885,7 +885,7 @@ void __init init_speculation_mitigations(void) bool cpu_has_bug_taa; uint64_t caps =3D 0; =20 - if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) ) + if ( cpu_has_arch_caps ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); =20 hw_smt_enabled =3D check_smt_enabled(); diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index e09e819dce..98ecb71a4a 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -34,15 +34,18 @@ void tsx_init(void) { /* * This function is first called between microcode being loaded, and C= PUID - * being scanned generally. Calculate from raw data whether MSR_TSX_C= TRL - * is available. + * being scanned generally. Read into boot_cpu_data.x86_capability[] = for + * the cpu_has_* bits we care about using here. */ if ( unlikely(cpu_has_tsx_ctrl < 0) ) { uint64_t caps =3D 0; =20 - if ( boot_cpu_data.cpuid_level >=3D 7 && - (cpuid_count_edx(7, 0) & cpufeat_mask(X86_FEATURE_ARCH_CAPS))= ) + if ( boot_cpu_data.cpuid_level >=3D 7 ) + boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_ARCH_CAP= S)] + =3D cpuid_count_edx(7, 0); + + if ( cpu_has_arch_caps ) rdmsrl(MSR_ARCH_CAPABILITIES, caps); =20 cpu_has_tsx_ctrl =3D !!(caps & ARCH_CAPS_TSX_CTRL); @@ -74,18 +77,18 @@ void tsx_init(void) =20 if ( cpu_has_tsx_ctrl ) { - uint64_t val; + uint32_t hi, lo; =20 - rdmsrl(MSR_TSX_CTRL, val); + rdmsr(MSR_TSX_CTRL, lo, hi); =20 /* Check bottom bit only. Higher bits are various sentinels. */ rtm_disabled =3D !(opt_tsx & 1); =20 - val &=3D ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR); + lo &=3D ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR); if ( rtm_disabled ) - val |=3D TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR; + lo |=3D TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR; =20 - wrmsrl(MSR_TSX_CTRL, val); + wrmsr(MSR_TSX_CTRL, lo, hi); } else if ( opt_tsx >=3D 0 ) printk_once(XENLOG_WARNING diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index 33b2257888..9f5ae3aa0d 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -133,6 +133,7 @@ #define cpu_has_avx512_vp2intersect boot_cpu_has(X86_FEATURE_AVX512_VP2INT= ERSECT) #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) #define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE) +#define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS) =20 /* CPUID level 0x00000007:1.eax */ #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) --=20 2.11.0