From nobody Tue Feb 10 00:22:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1620200642; cv=none; d=zohomail.com; s=zohoarc; b=A4HGbGcGrhAoA3aoSeX4U6T/fX/pVvjnN1BYjGtAxPvkQSkT53YJoRPGCsu5wbU4BXbsiKSkwtCZyLfF6yZGNVL0y8ZO039bb++TYUUAMPaFODxJjwi09/TXQhuqIs+ExLb2mO7kA9D1DeYaZLUsPzBcB84DlfprhQNBYMZCZLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620200642; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d4W4yZFsi2Cmw5GaAJJVsuVncwqk2o0D4F77iK+XU2o=; b=hKQYKdACrAonSgCLbTtK7X3egH25w6Ab11CwdyaHZm2AcOgiCwRAB+6lFeFb4WFQsNHC2oGQMUHsIja10VNHuBXNqNdcP49XTBV267H4u8Qk4e7PiW0QqCdOYIcR+8c7CuthhnbveKkAN3PAV7BNxDr63zJW7dgfdS8q0o72E0I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1620200642978922.7120919481787; Wed, 5 May 2021 00:44:02 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.122833.231782 (Exim 4.92) (envelope-from ) id 1leCCE-0008Kk-OQ; Wed, 05 May 2021 07:43:50 +0000 Received: by outflank-mailman (output) from mailman id 122833.231782; Wed, 05 May 2021 07:43:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leCCE-0008KP-JF; Wed, 05 May 2021 07:43:50 +0000 Received: by outflank-mailman (input) for mailman id 122833; Wed, 05 May 2021 07:43:49 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leCCD-00044r-Pv for xen-devel@lists.xenproject.org; Wed, 05 May 2021 07:43:49 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 545043b5-8bdc-44a9-b255-5356f035047e; Wed, 05 May 2021 07:43:31 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AD831063; Wed, 5 May 2021 00:43:31 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.0.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC22B3F718; Wed, 5 May 2021 00:43:29 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 545043b5-8bdc-44a9-b255-5356f035047e From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, wei.chen@arm.com, Julien Grall Subject: [PATCH v3 08/10] arm/page: Get rid of READ/WRITE_SYSREG32 Date: Wed, 5 May 2021 09:43:06 +0200 Message-Id: <20210505074308.11016-9-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210505074308.11016-1-michal.orzel@arm.com> References: <20210505074308.11016-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify accesses to CTR_EL0 to use READ/WRITE_SYSREG. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/include/asm-arm/page.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 131507a517..c6f9fb0d4e 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -137,10 +137,10 @@ extern size_t dcache_line_bytes; =20 static inline size_t read_dcache_line_bytes(void) { - uint32_t ctr; + register_t ctr; =20 /* Read CTR */ - ctr =3D READ_SYSREG32(CTR_EL0); + ctr =3D READ_SYSREG(CTR_EL0); =20 /* Bits 16-19 are the log2 number of words in the cacheline. */ return (size_t) (4 << ((ctr >> 16) & 0xf)); --=20 2.29.0