From nobody Tue Feb 10 04:15:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1620200621; cv=none; d=zohomail.com; s=zohoarc; b=fKjksC8sxLD46qkeyk5dLlyHAjH51N7haR2vnrdhqoRhSZS8OVsx6fCjkXcfynz38BdOr4eRvVcBN0iLbdVQ5keZdLjR1I3oyfy6O+FF4kx5t6QNYi4l8+Zv4mftV+UrHXbC8BrDBnt0AiC8YX8iAq69osV+wOnB+bizKAoWamE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1620200621; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SAtXMo3wi0fGZztmqgUUS5RxOCSSy3Zni8y42NWA6JM=; b=h67QXER+NciwtRLOsj29W0eV8Vr37vKFpmH4ii3RVz5z2+r+0epBr/QYdRKB133crJmdqjOugKkRD/hRSfWW0ZsIxYNMGKs03jb+iAv2Zpm3r85josoiAYV6fVi2H7sMQjSfc+jOPv5vB7+5CVvYJKxXXGwhHOPGPSr1Q8mxqVk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1620200621637688.3768511589653; Wed, 5 May 2021 00:43:41 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.122823.231714 (Exim 4.92) (envelope-from ) id 1leCBu-00055e-Ex; Wed, 05 May 2021 07:43:30 +0000 Received: by outflank-mailman (output) from mailman id 122823.231714; Wed, 05 May 2021 07:43:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leCBu-00054e-7B; Wed, 05 May 2021 07:43:30 +0000 Received: by outflank-mailman (input) for mailman id 122823; Wed, 05 May 2021 07:43:29 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leCBt-00044r-PI for xen-devel@lists.xenproject.org; Wed, 05 May 2021 07:43:29 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 821e5e6c-2cea-4e11-87c1-7ae54060627c; Wed, 05 May 2021 07:43:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B1A5D11FB; Wed, 5 May 2021 00:43:20 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.0.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CECB3F718; Wed, 5 May 2021 00:43:19 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 821e5e6c-2cea-4e11-87c1-7ae54060627c From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, wei.chen@arm.com Subject: [PATCH v3 02/10] arm/domain: Get rid of READ/WRITE_SYSREG32 Date: Wed, 5 May 2021 09:43:00 +0200 Message-Id: <20210505074308.11016-3-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210505074308.11016-1-michal.orzel@arm.com> References: <20210505074308.11016-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of register cntkctl to register_t. Modify accesses to thumbee registers to use READ/WRITE_SYSREG. Thumbee registers are only usable by a 32bit domain and in fact should be only accessed on ARMv7 as they were retrospectively dropped on ARMv8. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- Changes since v2: -Modify the commit message Changes since v1: -Move modification of ACTLR into seperate patch --- xen/arch/arm/domain.c | 18 +++++++++--------- xen/include/asm-arm/domain.h | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index bdd3d3e5b5..621f518b83 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -113,13 +113,13 @@ static void ctxt_switch_from(struct vcpu *p) p->arch.tpidr_el1 =3D READ_SYSREG(TPIDR_EL1); =20 /* Arch timer */ - p->arch.cntkctl =3D READ_SYSREG32(CNTKCTL_EL1); + p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1); virt_timer_save(p); =20 if ( is_32bit_domain(p->domain) && cpu_has_thumbee ) { - p->arch.teecr =3D READ_SYSREG32(TEECR32_EL1); - p->arch.teehbr =3D READ_SYSREG32(TEEHBR32_EL1); + p->arch.teecr =3D READ_SYSREG(TEECR32_EL1); + p->arch.teehbr =3D READ_SYSREG(TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -175,7 +175,7 @@ static void ctxt_switch_from(struct vcpu *p) =20 static void ctxt_switch_to(struct vcpu *n) { - uint32_t vpidr; + register_t vpidr; =20 /* When the idle VCPU is running, Xen will always stay in hypervisor * mode. Therefore we don't need to restore the context of an idle VCP= U. @@ -183,8 +183,8 @@ static void ctxt_switch_to(struct vcpu *n) if ( is_idle_vcpu(n) ) return; =20 - vpidr =3D READ_SYSREG32(MIDR_EL1); - WRITE_SYSREG32(vpidr, VPIDR_EL2); + vpidr =3D READ_SYSREG(MIDR_EL1); + WRITE_SYSREG(vpidr, VPIDR_EL2); WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); =20 /* VGIC */ @@ -257,8 +257,8 @@ static void ctxt_switch_to(struct vcpu *n) =20 if ( is_32bit_domain(n->domain) && cpu_has_thumbee ) { - WRITE_SYSREG32(n->arch.teecr, TEECR32_EL1); - WRITE_SYSREG32(n->arch.teehbr, TEEHBR32_EL1); + WRITE_SYSREG(n->arch.teecr, TEECR32_EL1); + WRITE_SYSREG(n->arch.teehbr, TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -274,7 +274,7 @@ static void ctxt_switch_to(struct vcpu *n) =20 /* This is could trigger an hardware interrupt from the virtual * timer. The interrupt needs to be injected into the guest. */ - WRITE_SYSREG32(n->arch.cntkctl, CNTKCTL_EL1); + WRITE_SYSREG(n->arch.cntkctl, CNTKCTL_EL1); virt_timer_restore(n); } =20 diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 0a74df9931..c6b59ee755 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -190,7 +190,7 @@ struct arch_vcpu struct vgic_cpu vgic; =20 /* Timer registers */ - uint32_t cntkctl; + register_t cntkctl; =20 struct vtimer phys_timer; struct vtimer virt_timer; --=20 2.29.0