From nobody Thu Apr 25 02:30:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516202; cv=none; d=zohomail.com; s=zohoarc; b=O618q0ai4rag5VauFNX9UHuv9I1pwm20Chwrx4eZk1vPbVZ061oLg+OCGj+yfaLAoPyG3fQVv6hUX2TLpJ5a1ZZVkrDtlFunDoIcjw0ANwjff+cJfpLcUEpzzRpIEDAeKj1qsWqp8soonuMJe+O7wydWJ0xAlm3kcb2F5OmbnM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516202; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W0/2g/r/g5CyYMlJANe7B6KYUDgl4ejTBvL2PRvQ8x8=; b=HxkneIU5cJs0zKHK0CY/o2sfSCaK8qVlpB4VMcllvPTZdJ82iEoKi2DSGQy67oITXNRDGGMUV8V9RNwxBTqiwMz2PoOn6XCD5WOaBaMKbqcY3+zSF+2JejMO1/alegNuwAjKuHeOp/9Qf7e7Qt1LxCxPRI3M5cuI4EX1MIP4sjo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 161951620221765.30522614169433; Tue, 27 Apr 2021 02:36:42 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118155.224191 (Exim 4.92) (envelope-from ) id 1lbK8p-000764-9S; Tue, 27 Apr 2021 09:36:27 +0000 Received: by outflank-mailman (output) from mailman id 118155.224191; Tue, 27 Apr 2021 09:36:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8p-00075w-4r; Tue, 27 Apr 2021 09:36:27 +0000 Received: by outflank-mailman (input) for mailman id 118155; Tue, 27 Apr 2021 09:36:25 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8n-0006jJ-Av for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:25 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 936cbc0e-97a9-4437-bdb8-34e6d9e003d6; Tue, 27 Apr 2021 09:36:08 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4243DED1; Tue, 27 Apr 2021 02:36:08 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A000A3F694; Tue, 27 Apr 2021 02:36:06 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 936cbc0e-97a9-4437-bdb8-34e6d9e003d6 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, Julien Grall Subject: [PATCH v2 06/10] arm/p2m: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:42 +0200 Message-Id: <20210427093546.30703-7-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of vtcr to register_t. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/p2m.c | 8 ++++---- xen/arch/arm/traps.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index ac50312620..d414c4feb9 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1973,11 +1973,11 @@ void __init p2m_restrict_ipa_bits(unsigned int ipa_= bits) } =20 /* VTCR value to be configured by all CPUs. Set only once by the boot CPU = */ -static uint32_t __read_mostly vtcr; +static register_t __read_mostly vtcr; =20 static void setup_virt_paging_one(void *data) { - WRITE_SYSREG32(vtcr, VTCR_EL2); + WRITE_SYSREG(vtcr, VTCR_EL2); =20 /* * ARM64_WORKAROUND_AT_SPECULATE: We want to keep the TLBs free from @@ -2000,7 +2000,7 @@ static void setup_virt_paging_one(void *data) void __init setup_virt_paging(void) { /* Setup Stage 2 address translation */ - unsigned long val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0= _WBWA; + register_t val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WB= WA; =20 #ifdef CONFIG_ARM_32 if ( p2m_ipa_bits < 40 ) @@ -2089,7 +2089,7 @@ void __init setup_virt_paging(void) pa_range_info[pa_range].pabits, ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); #endif - printk("P2M: %d levels with order-%d root, VTCR 0x%lx\n", + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); =20 p2m_vmid_allocator_init(); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ccc0827107..c7acdb2087 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -911,7 +911,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, show_registers_32(regs, ctxt, guest_mode, v); #endif } - printk(" VTCR_EL2: %08"PRIx32"\n", READ_SYSREG32(VTCR_EL2)); + printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); printk("\n"); =20 --=20 2.29.0