From nobody Wed Apr 24 13:38:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516202; cv=none; d=zohomail.com; s=zohoarc; b=OFHe+5xmLO9F5+pC3udTFs4jorEa6c3T8JW+XIZZ2bqNvJZS87XhHG0ghhrrT2KP+mDm1/rif26eSTJvBpkh7m8ekD8QXVodXeAab31TkHbLS/PxPsGxK20/qlXqLHgWlmzPrayIWXA1PkcqiUlXF7SCFbx46WO2OloHIVslncQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516202; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DKzd24RTMARCCvwknY4FO596USyLgQMrJKd+dTJjXYA=; b=nBBuS3ZFMD1BTh/RGhjIC2vBp6vSwscrX78r8Jt1hyFZgRgyGNwrbMfeuonsErrNRLPTh8cOPXXwJafXjogTedeVcutDsMeGtbQgJgnKO1DVPdOjf/N9eKOSFuu9HNJS3ZqL8u63od1QtjUKRaPnnQOBkg50/GX20VQ55rM666w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516202200804.8712256116486; Tue, 27 Apr 2021 02:36:42 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118150.224155 (Exim 4.92) (envelope-from ) id 1lbK8a-0006qR-3n; Tue, 27 Apr 2021 09:36:12 +0000 Received: by outflank-mailman (output) from mailman id 118150.224155; Tue, 27 Apr 2021 09:36:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8a-0006qK-0j; Tue, 27 Apr 2021 09:36:12 +0000 Received: by outflank-mailman (input) for mailman id 118150; Tue, 27 Apr 2021 09:36:10 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8Y-0006jJ-AT for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:10 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e7887ec5-a427-4c04-9f58-01a7c570b171; Tue, 27 Apr 2021 09:36:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20B63106F; Tue, 27 Apr 2021 02:36:02 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D37C63F694; Tue, 27 Apr 2021 02:36:00 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e7887ec5-a427-4c04-9f58-01a7c570b171 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 03/10] arm: Modify type of actlr to register_t Date: Tue, 27 Apr 2021 11:35:39 +0200 Message-Id: <20210427093546.30703-4-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Signed-off-by: Michal Orzel --- xen/arch/arm/domain.c | 2 +- xen/include/asm-arm/domain.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 621f518b83..c021a03c61 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -330,7 +330,7 @@ static void schedule_tail(struct vcpu *prev) =20 static void continue_new_vcpu(struct vcpu *prev) { - current->arch.actlr =3D READ_SYSREG32(ACTLR_EL1); + current->arch.actlr =3D READ_SYSREG(ACTLR_EL1); processor_vcpu_initialise(current); =20 schedule_tail(prev); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index c6b59ee755..2d4f38c669 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -156,7 +156,7 @@ struct arch_vcpu =20 /* Control Registers */ register_t sctlr; - uint32_t actlr; + register_t actlr; uint32_t cpacr; =20 uint32_t contextidr; --=20 2.29.0