From nobody Thu Apr 18 22:21:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516199; cv=none; d=zohomail.com; s=zohoarc; b=INrkHu9nIl6GbBgAuptAJ4f18u+FZPvk3VVOGEPSnPWu6vqjEL11v/5I4+sdA9oJK/uDSP2yjGmYVOwZxSKnk0wIAt2sWeJyMrrn54jSS8+8HaUqTnKofqQbaB2IEaLB2uebcfXFPnrjaZeyrFds0C0HQOfe0uBBWbxt41fO2to= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516199; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NqRRZCnr04dSGaGYQojyhuIJUNbgtIqw5UteDramjg8=; b=DStQ25eQK5389cUHvhVSNIdGY6dUIc1scGBNVp8if3IgIdJoOEuvqfmo2b74ze2ubNoi/b5mdbgml5ffzeeMMO49aANblBw8kJqB1Efwqcu4ivIoh/SBeufoRhx1j9PNakv235GrDnVM/phX5erartUkLrLSZC/l4V9d2aMg0qE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516199303216.58577938141195; Tue, 27 Apr 2021 02:36:39 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118149.224143 (Exim 4.92) (envelope-from ) id 1lbK8U-0006mU-QW; Tue, 27 Apr 2021 09:36:06 +0000 Received: by outflank-mailman (output) from mailman id 118149.224143; Tue, 27 Apr 2021 09:36:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8U-0006mN-NG; Tue, 27 Apr 2021 09:36:06 +0000 Received: by outflank-mailman (input) for mailman id 118149; Tue, 27 Apr 2021 09:36:05 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8T-0006jJ-AQ for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:05 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 5a263592-b28c-4e82-bdce-c7fba4e098b1; Tue, 27 Apr 2021 09:36:01 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85BFF101E; Tue, 27 Apr 2021 02:36:00 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A6B53F694; Tue, 27 Apr 2021 02:35:59 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5a263592-b28c-4e82-bdce-c7fba4e098b1 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 02/10] arm/domain: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:38 +0200 Message-Id: <20210427093546.30703-3-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of register cntkctl to register_t. Modify accesses to thumbee registers to use READ/WRITE_SYSREG. No need to change type of thumbee registers to register_t as they only exist on arm32. Signed-off-by: Michal Orzel --- Changes since v1: -Move modification of ACTLR into seperate patch --- xen/arch/arm/domain.c | 18 +++++++++--------- xen/include/asm-arm/domain.h | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index bdd3d3e5b5..621f518b83 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -113,13 +113,13 @@ static void ctxt_switch_from(struct vcpu *p) p->arch.tpidr_el1 =3D READ_SYSREG(TPIDR_EL1); =20 /* Arch timer */ - p->arch.cntkctl =3D READ_SYSREG32(CNTKCTL_EL1); + p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1); virt_timer_save(p); =20 if ( is_32bit_domain(p->domain) && cpu_has_thumbee ) { - p->arch.teecr =3D READ_SYSREG32(TEECR32_EL1); - p->arch.teehbr =3D READ_SYSREG32(TEEHBR32_EL1); + p->arch.teecr =3D READ_SYSREG(TEECR32_EL1); + p->arch.teehbr =3D READ_SYSREG(TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -175,7 +175,7 @@ static void ctxt_switch_from(struct vcpu *p) =20 static void ctxt_switch_to(struct vcpu *n) { - uint32_t vpidr; + register_t vpidr; =20 /* When the idle VCPU is running, Xen will always stay in hypervisor * mode. Therefore we don't need to restore the context of an idle VCP= U. @@ -183,8 +183,8 @@ static void ctxt_switch_to(struct vcpu *n) if ( is_idle_vcpu(n) ) return; =20 - vpidr =3D READ_SYSREG32(MIDR_EL1); - WRITE_SYSREG32(vpidr, VPIDR_EL2); + vpidr =3D READ_SYSREG(MIDR_EL1); + WRITE_SYSREG(vpidr, VPIDR_EL2); WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); =20 /* VGIC */ @@ -257,8 +257,8 @@ static void ctxt_switch_to(struct vcpu *n) =20 if ( is_32bit_domain(n->domain) && cpu_has_thumbee ) { - WRITE_SYSREG32(n->arch.teecr, TEECR32_EL1); - WRITE_SYSREG32(n->arch.teehbr, TEEHBR32_EL1); + WRITE_SYSREG(n->arch.teecr, TEECR32_EL1); + WRITE_SYSREG(n->arch.teehbr, TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -274,7 +274,7 @@ static void ctxt_switch_to(struct vcpu *n) =20 /* This is could trigger an hardware interrupt from the virtual * timer. The interrupt needs to be injected into the guest. */ - WRITE_SYSREG32(n->arch.cntkctl, CNTKCTL_EL1); + WRITE_SYSREG(n->arch.cntkctl, CNTKCTL_EL1); virt_timer_restore(n); } =20 diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 0a74df9931..c6b59ee755 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -190,7 +190,7 @@ struct arch_vcpu struct vgic_cpu vgic; =20 /* Timer registers */ - uint32_t cntkctl; + register_t cntkctl; =20 struct vtimer phys_timer; struct vtimer virt_timer; --=20 2.29.0