From nobody Fri Apr 19 07:13:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516196; cv=none; d=zohomail.com; s=zohoarc; b=OyfCr3BMv8k+99SFM1TtAgDpbAOER0Ewodd54EJAyVpT6/psJgS6zEyEI5B/i3TdwQklOkn7kPBryDYWXBCk2lPu7JcTmQ+6wuYr+eAIEh8T9ZM/GoxhoWPa7dmxjFW/7D8zeLdLoO5BQbanjNTn2tvis5/eIpa+aryOSolvs5o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516196; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=G51CzS8X3xMXBF8zM6lVsLPN5WGrMu2B9RaXKHu/bd8=; b=V6hEnEqYzlM2K0JwEyFkPBlW9ZLFDNKktrSfwQwajhCaj7TlfIMbHS5ixg+yPhp/aqjffOkyCpfCn7MV8cHAUtFF/gX/y5rYcO65cN7tHoZ3js7oPSPffLeC4KdRJTqmO+MpBxQTR7708++A9JPLsAx8wBTHQRiRms9i6Yg0Es8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516196753984.9124778648724; Tue, 27 Apr 2021 02:36:36 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118148.224126 (Exim 4.92) (envelope-from ) id 1lbK8Q-0006k4-Lp; Tue, 27 Apr 2021 09:36:02 +0000 Received: by outflank-mailman (output) from mailman id 118148.224126; Tue, 27 Apr 2021 09:36:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8Q-0006ju-F4; Tue, 27 Apr 2021 09:36:02 +0000 Received: by outflank-mailman (input) for mailman id 118148; Tue, 27 Apr 2021 09:36:01 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8P-0006jO-J7 for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:01 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 4891b552-7a6d-4c71-a791-3c7fd5c57315; Tue, 27 Apr 2021 09:35:59 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2C88ED1; Tue, 27 Apr 2021 02:35:58 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60BEA3F694; Tue, 27 Apr 2021 02:35:57 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4891b552-7a6d-4c71-a791-3c7fd5c57315 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, Julien Grall Subject: [PATCH v2 01/10] arm64/vfp: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:37 +0200 Message-Id: <20210427093546.30703-2-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of FPCR, FPSR, FPEXC32_EL2 to register_t. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/arm64/vfp.c | 12 ++++++------ xen/include/asm-arm/arm64/vfp.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c index 999a0d58a5..47885e76ba 100644 --- a/xen/arch/arm/arm64/vfp.c +++ b/xen/arch/arm/arm64/vfp.c @@ -26,10 +26,10 @@ void vfp_save_state(struct vcpu *v) "stp q30, q31, [%1, #16 * 30]\n\t" : "=3DQ" (*v->arch.vfp.fpregs) : "r" (v->arch.vfp.fpregs)= ); =20 - v->arch.vfp.fpsr =3D READ_SYSREG32(FPSR); - v->arch.vfp.fpcr =3D READ_SYSREG32(FPCR); + v->arch.vfp.fpsr =3D READ_SYSREG(FPSR); + v->arch.vfp.fpcr =3D READ_SYSREG(FPCR); if ( is_32bit_domain(v->domain) ) - v->arch.vfp.fpexc32_el2 =3D READ_SYSREG32(FPEXC32_EL2); + v->arch.vfp.fpexc32_el2 =3D READ_SYSREG(FPEXC32_EL2); } =20 void vfp_restore_state(struct vcpu *v) @@ -55,8 +55,8 @@ void vfp_restore_state(struct vcpu *v) "ldp q30, q31, [%1, #16 * 30]\n\t" : : "Q" (*v->arch.vfp.fpregs), "r" (v->arch.vfp.fpregs)); =20 - WRITE_SYSREG32(v->arch.vfp.fpsr, FPSR); - WRITE_SYSREG32(v->arch.vfp.fpcr, FPCR); + WRITE_SYSREG(v->arch.vfp.fpsr, FPSR); + WRITE_SYSREG(v->arch.vfp.fpcr, FPCR); if ( is_32bit_domain(v->domain) ) - WRITE_SYSREG32(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); + WRITE_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); } diff --git a/xen/include/asm-arm/arm64/vfp.h b/xen/include/asm-arm/arm64/vf= p.h index 6ab5d36c6c..e6e8c363bc 100644 --- a/xen/include/asm-arm/arm64/vfp.h +++ b/xen/include/asm-arm/arm64/vfp.h @@ -7,9 +7,9 @@ struct vfp_state { uint64_t fpregs[64] __vfp_aligned; - uint32_t fpcr; - uint32_t fpexc32_el2; - uint32_t fpsr; + register_t fpcr; + register_t fpexc32_el2; + register_t fpsr; }; =20 #endif /* _ARM_ARM64_VFP_H */ --=20 2.29.0