From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516196; cv=none; d=zohomail.com; s=zohoarc; b=OyfCr3BMv8k+99SFM1TtAgDpbAOER0Ewodd54EJAyVpT6/psJgS6zEyEI5B/i3TdwQklOkn7kPBryDYWXBCk2lPu7JcTmQ+6wuYr+eAIEh8T9ZM/GoxhoWPa7dmxjFW/7D8zeLdLoO5BQbanjNTn2tvis5/eIpa+aryOSolvs5o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516196; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=G51CzS8X3xMXBF8zM6lVsLPN5WGrMu2B9RaXKHu/bd8=; b=V6hEnEqYzlM2K0JwEyFkPBlW9ZLFDNKktrSfwQwajhCaj7TlfIMbHS5ixg+yPhp/aqjffOkyCpfCn7MV8cHAUtFF/gX/y5rYcO65cN7tHoZ3js7oPSPffLeC4KdRJTqmO+MpBxQTR7708++A9JPLsAx8wBTHQRiRms9i6Yg0Es8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516196753984.9124778648724; Tue, 27 Apr 2021 02:36:36 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118148.224126 (Exim 4.92) (envelope-from ) id 1lbK8Q-0006k4-Lp; Tue, 27 Apr 2021 09:36:02 +0000 Received: by outflank-mailman (output) from mailman id 118148.224126; Tue, 27 Apr 2021 09:36:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8Q-0006ju-F4; Tue, 27 Apr 2021 09:36:02 +0000 Received: by outflank-mailman (input) for mailman id 118148; Tue, 27 Apr 2021 09:36:01 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8P-0006jO-J7 for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:01 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 4891b552-7a6d-4c71-a791-3c7fd5c57315; Tue, 27 Apr 2021 09:35:59 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2C88ED1; Tue, 27 Apr 2021 02:35:58 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 60BEA3F694; Tue, 27 Apr 2021 02:35:57 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4891b552-7a6d-4c71-a791-3c7fd5c57315 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, Julien Grall Subject: [PATCH v2 01/10] arm64/vfp: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:37 +0200 Message-Id: <20210427093546.30703-2-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of FPCR, FPSR, FPEXC32_EL2 to register_t. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/arm64/vfp.c | 12 ++++++------ xen/include/asm-arm/arm64/vfp.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c index 999a0d58a5..47885e76ba 100644 --- a/xen/arch/arm/arm64/vfp.c +++ b/xen/arch/arm/arm64/vfp.c @@ -26,10 +26,10 @@ void vfp_save_state(struct vcpu *v) "stp q30, q31, [%1, #16 * 30]\n\t" : "=3DQ" (*v->arch.vfp.fpregs) : "r" (v->arch.vfp.fpregs)= ); =20 - v->arch.vfp.fpsr =3D READ_SYSREG32(FPSR); - v->arch.vfp.fpcr =3D READ_SYSREG32(FPCR); + v->arch.vfp.fpsr =3D READ_SYSREG(FPSR); + v->arch.vfp.fpcr =3D READ_SYSREG(FPCR); if ( is_32bit_domain(v->domain) ) - v->arch.vfp.fpexc32_el2 =3D READ_SYSREG32(FPEXC32_EL2); + v->arch.vfp.fpexc32_el2 =3D READ_SYSREG(FPEXC32_EL2); } =20 void vfp_restore_state(struct vcpu *v) @@ -55,8 +55,8 @@ void vfp_restore_state(struct vcpu *v) "ldp q30, q31, [%1, #16 * 30]\n\t" : : "Q" (*v->arch.vfp.fpregs), "r" (v->arch.vfp.fpregs)); =20 - WRITE_SYSREG32(v->arch.vfp.fpsr, FPSR); - WRITE_SYSREG32(v->arch.vfp.fpcr, FPCR); + WRITE_SYSREG(v->arch.vfp.fpsr, FPSR); + WRITE_SYSREG(v->arch.vfp.fpcr, FPCR); if ( is_32bit_domain(v->domain) ) - WRITE_SYSREG32(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); + WRITE_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); } diff --git a/xen/include/asm-arm/arm64/vfp.h b/xen/include/asm-arm/arm64/vf= p.h index 6ab5d36c6c..e6e8c363bc 100644 --- a/xen/include/asm-arm/arm64/vfp.h +++ b/xen/include/asm-arm/arm64/vfp.h @@ -7,9 +7,9 @@ struct vfp_state { uint64_t fpregs[64] __vfp_aligned; - uint32_t fpcr; - uint32_t fpexc32_el2; - uint32_t fpsr; + register_t fpcr; + register_t fpexc32_el2; + register_t fpsr; }; =20 #endif /* _ARM_ARM64_VFP_H */ --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Tue, 27 Apr 2021 09:36:05 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 5a263592-b28c-4e82-bdce-c7fba4e098b1; Tue, 27 Apr 2021 09:36:01 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85BFF101E; Tue, 27 Apr 2021 02:36:00 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A6B53F694; Tue, 27 Apr 2021 02:35:59 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5a263592-b28c-4e82-bdce-c7fba4e098b1 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 02/10] arm/domain: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:38 +0200 Message-Id: <20210427093546.30703-3-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of register cntkctl to register_t. Modify accesses to thumbee registers to use READ/WRITE_SYSREG. No need to change type of thumbee registers to register_t as they only exist on arm32. Signed-off-by: Michal Orzel --- Changes since v1: -Move modification of ACTLR into seperate patch --- xen/arch/arm/domain.c | 18 +++++++++--------- xen/include/asm-arm/domain.h | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index bdd3d3e5b5..621f518b83 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -113,13 +113,13 @@ static void ctxt_switch_from(struct vcpu *p) p->arch.tpidr_el1 =3D READ_SYSREG(TPIDR_EL1); =20 /* Arch timer */ - p->arch.cntkctl =3D READ_SYSREG32(CNTKCTL_EL1); + p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1); virt_timer_save(p); =20 if ( is_32bit_domain(p->domain) && cpu_has_thumbee ) { - p->arch.teecr =3D READ_SYSREG32(TEECR32_EL1); - p->arch.teehbr =3D READ_SYSREG32(TEEHBR32_EL1); + p->arch.teecr =3D READ_SYSREG(TEECR32_EL1); + p->arch.teehbr =3D READ_SYSREG(TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -175,7 +175,7 @@ static void ctxt_switch_from(struct vcpu *p) =20 static void ctxt_switch_to(struct vcpu *n) { - uint32_t vpidr; + register_t vpidr; =20 /* When the idle VCPU is running, Xen will always stay in hypervisor * mode. Therefore we don't need to restore the context of an idle VCP= U. @@ -183,8 +183,8 @@ static void ctxt_switch_to(struct vcpu *n) if ( is_idle_vcpu(n) ) return; =20 - vpidr =3D READ_SYSREG32(MIDR_EL1); - WRITE_SYSREG32(vpidr, VPIDR_EL2); + vpidr =3D READ_SYSREG(MIDR_EL1); + WRITE_SYSREG(vpidr, VPIDR_EL2); WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); =20 /* VGIC */ @@ -257,8 +257,8 @@ static void ctxt_switch_to(struct vcpu *n) =20 if ( is_32bit_domain(n->domain) && cpu_has_thumbee ) { - WRITE_SYSREG32(n->arch.teecr, TEECR32_EL1); - WRITE_SYSREG32(n->arch.teehbr, TEEHBR32_EL1); + WRITE_SYSREG(n->arch.teecr, TEECR32_EL1); + WRITE_SYSREG(n->arch.teehbr, TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -274,7 +274,7 @@ static void ctxt_switch_to(struct vcpu *n) =20 /* This is could trigger an hardware interrupt from the virtual * timer. The interrupt needs to be injected into the guest. */ - WRITE_SYSREG32(n->arch.cntkctl, CNTKCTL_EL1); + WRITE_SYSREG(n->arch.cntkctl, CNTKCTL_EL1); virt_timer_restore(n); } =20 diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 0a74df9931..c6b59ee755 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -190,7 +190,7 @@ struct arch_vcpu struct vgic_cpu vgic; =20 /* Timer registers */ - uint32_t cntkctl; + register_t cntkctl; =20 struct vtimer phys_timer; struct vtimer virt_timer; --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516202; cv=none; d=zohomail.com; s=zohoarc; b=OFHe+5xmLO9F5+pC3udTFs4jorEa6c3T8JW+XIZZ2bqNvJZS87XhHG0ghhrrT2KP+mDm1/rif26eSTJvBpkh7m8ekD8QXVodXeAab31TkHbLS/PxPsGxK20/qlXqLHgWlmzPrayIWXA1PkcqiUlXF7SCFbx46WO2OloHIVslncQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516202; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DKzd24RTMARCCvwknY4FO596USyLgQMrJKd+dTJjXYA=; b=nBBuS3ZFMD1BTh/RGhjIC2vBp6vSwscrX78r8Jt1hyFZgRgyGNwrbMfeuonsErrNRLPTh8cOPXXwJafXjogTedeVcutDsMeGtbQgJgnKO1DVPdOjf/N9eKOSFuu9HNJS3ZqL8u63od1QtjUKRaPnnQOBkg50/GX20VQ55rM666w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516202200804.8712256116486; Tue, 27 Apr 2021 02:36:42 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118150.224155 (Exim 4.92) (envelope-from ) id 1lbK8a-0006qR-3n; Tue, 27 Apr 2021 09:36:12 +0000 Received: by outflank-mailman (output) from mailman id 118150.224155; Tue, 27 Apr 2021 09:36:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8a-0006qK-0j; Tue, 27 Apr 2021 09:36:12 +0000 Received: by outflank-mailman (input) for mailman id 118150; Tue, 27 Apr 2021 09:36:10 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8Y-0006jJ-AT for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:10 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e7887ec5-a427-4c04-9f58-01a7c570b171; Tue, 27 Apr 2021 09:36:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20B63106F; Tue, 27 Apr 2021 02:36:02 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D37C63F694; Tue, 27 Apr 2021 02:36:00 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e7887ec5-a427-4c04-9f58-01a7c570b171 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 03/10] arm: Modify type of actlr to register_t Date: Tue, 27 Apr 2021 11:35:39 +0200 Message-Id: <20210427093546.30703-4-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Signed-off-by: Michal Orzel --- xen/arch/arm/domain.c | 2 +- xen/include/asm-arm/domain.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 621f518b83..c021a03c61 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -330,7 +330,7 @@ static void schedule_tail(struct vcpu *prev) =20 static void continue_new_vcpu(struct vcpu *prev) { - current->arch.actlr =3D READ_SYSREG32(ACTLR_EL1); + current->arch.actlr =3D READ_SYSREG(ACTLR_EL1); processor_vcpu_initialise(current); =20 schedule_tail(prev); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index c6b59ee755..2d4f38c669 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -156,7 +156,7 @@ struct arch_vcpu =20 /* Control Registers */ register_t sctlr; - uint32_t actlr; + register_t actlr; uint32_t cpacr; =20 uint32_t contextidr; --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516198; cv=none; d=zohomail.com; s=zohoarc; b=UmjjviyikhpnMXBcZiLcHojH801CvPRIEEqyPS0xOvW57M5WxRh8p4KZrm2Fz4Siw/FPgmmbcdFDTzBvxyfH4EYKFVYnKLkYsYp4414iv9kw3mN3sqOkhDJVOeJt1Lelmdq0DhWM2HFrPuySFbxwPxeWRNUXgQprx7Lz1CkY6rc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516198; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KsU2Vm66zzTGmcUWCaPLsswaGMxQY1wE3ViNtVg244w=; b=lOQZUUYYgawoFidWvU26ZSC53zT/69OoorNoVfGXjc6/S5+g/ctPA0EgBBByiY/1Or7HDPo1AtHULBa38YM2cdp+X2bXWIgS6uKmhxa9pNZ37Y8tXm2dQOmqhjZ/2qEa3NMXFy0jjqrTvfXU4offQpWwqA4aRiYGhoVrC0qyTCk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516198404295.0994477419332; Tue, 27 Apr 2021 02:36:38 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118151.224167 (Exim 4.92) (envelope-from ) id 1lbK8f-0006vk-EI; Tue, 27 Apr 2021 09:36:17 +0000 Received: by outflank-mailman (output) from mailman id 118151.224167; Tue, 27 Apr 2021 09:36:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8f-0006vd-AU; Tue, 27 Apr 2021 09:36:17 +0000 Received: by outflank-mailman (input) for mailman id 118151; Tue, 27 Apr 2021 09:36:15 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8d-0006jJ-Ae for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:15 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 101a5026-5b11-48f9-9d27-0185aa048d18; Tue, 27 Apr 2021 09:36:04 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2AE0101E; Tue, 27 Apr 2021 02:36:03 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6CAC33F694; Tue, 27 Apr 2021 02:36:02 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 101a5026-5b11-48f9-9d27-0185aa048d18 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 04/10] arm/gic: Remove member hcr of structure gic_v3 Date: Tue, 27 Apr 2021 11:35:40 +0200 Message-Id: <20210427093546.30703-5-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ... as it is never used even in the patch introducing it. Signed-off-by: Michal Orzel Acked-by: Julien Grall --- xen/include/asm-arm/gic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index ad0f7452d0..5069ab4aac 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -171,7 +171,7 @@ * GICv3 registers that needs to be saved/restored */ struct gic_v3 { - uint32_t hcr, vmcr, sre_el1; + uint32_t vmcr, sre_el1; uint32_t apr0[4]; uint32_t apr1[4]; uint64_t lr[16]; --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516202; cv=none; d=zohomail.com; s=zohoarc; b=dsCZu1JnNU7BkRJF3pSzufWc0P0UMK2JNi6xAfd7fj03epW2/5wRweh9npRPIGQ4lRjCd/p8apg8Id3J9FyCeniY6Fa9zsJg0uAwwd5inUNnnLJmHm2u/LH3TOxq8Avo+p0DXo4GQXz6DpOrCdcJ+zK2vEWsuBid8L/d8G0dtLE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516202; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1ZIWlPTu0dWNKIQKI9fzu1Ug3awYyfy9PJwouFzVRhs=; b=L+AfcoyScvjROi0iACq1K+Mj3Irh9Uqs0AiIRRbru1g1RWZpxjXS8aiufDiEytkGasZeayTNGQ0VomXXWS3yNrWDVw/jjeuuJ+lis8ECDSnPlx4/KsZyhK9SjuzoovQhct4ZKIC+31NY+/Uo4KjyWDZqcbkqkgvvURrnWZsnJyw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516202995530.7252492011963; Tue, 27 Apr 2021 02:36:42 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118152.224179 (Exim 4.92) (envelope-from ) id 1lbK8j-000708-Nt; Tue, 27 Apr 2021 09:36:21 +0000 Received: by outflank-mailman (output) from mailman id 118152.224179; Tue, 27 Apr 2021 09:36:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8j-0006zz-KX; Tue, 27 Apr 2021 09:36:21 +0000 Received: by outflank-mailman (input) for mailman id 118152; Tue, 27 Apr 2021 09:36:20 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8i-0006jJ-Aq for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:20 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id c325b09f-43b8-4fb6-bdbc-016a89d43e5d; Tue, 27 Apr 2021 09:36:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16075101E; Tue, 27 Apr 2021 02:36:06 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F6BD3F694; Tue, 27 Apr 2021 02:36:03 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c325b09f-43b8-4fb6-bdbc-016a89d43e5d From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 05/10] arm/gic: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:41 +0200 Message-Id: <20210427093546.30703-6-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify types of following members of struct gic_v3 to register_t: -vmcr -sre_el1 -apr0 -apr1 Add new macro GICC_IAR_INTID_MASK containing the mask for INTID field of ICC_IAR0/1_EL1 register. Signed-off-by: Michal Orzel --- Changes since v1: -Remove hcr member of gic_v3 in a seperate patch -Add macro GICC_IAR_INTID_MASK -Remove explicit cast in favor of implicit cast --- xen/arch/arm/gic-v3-lpi.c | 2 +- xen/arch/arm/gic-v3.c | 98 ++++++++++++++++--------------- xen/include/asm-arm/gic.h | 6 +- xen/include/asm-arm/gic_v3_defs.h | 2 + 4 files changed, 58 insertions(+), 50 deletions(-) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 869bc97fa1..e1594dd20e 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -178,7 +178,7 @@ void gicv3_do_LPI(unsigned int lpi) irq_enter(); =20 /* EOI the LPI already. */ - WRITE_SYSREG32(lpi, ICC_EOIR1_EL1); + WRITE_SYSREG(lpi, ICC_EOIR1_EL1); =20 /* Find out if a guest mapped something to this physical LPI. */ hlpip =3D gic_get_host_lpi(lpi); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index ac28013c19..b86f040589 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -246,12 +246,12 @@ static void gicv3_ich_write_lr(int lr, uint64_t val) */ static void gicv3_enable_sre(void) { - uint32_t val; + register_t val; =20 - val =3D READ_SYSREG32(ICC_SRE_EL2); + val =3D READ_SYSREG(ICC_SRE_EL2); val |=3D GICC_SRE_EL2_SRE; =20 - WRITE_SYSREG32(val, ICC_SRE_EL2); + WRITE_SYSREG(val, ICC_SRE_EL2); isb(); } =20 @@ -315,16 +315,16 @@ static void restore_aprn_regs(const union gic_state_d= ata *d) switch ( gicv3.nr_priorities ) { case 7: - WRITE_SYSREG32(d->v3.apr0[2], ICH_AP0R2_EL2); - WRITE_SYSREG32(d->v3.apr1[2], ICH_AP1R2_EL2); + WRITE_SYSREG(d->v3.apr0[2], ICH_AP0R2_EL2); + WRITE_SYSREG(d->v3.apr1[2], ICH_AP1R2_EL2); /* Fall through */ case 6: - WRITE_SYSREG32(d->v3.apr0[1], ICH_AP0R1_EL2); - WRITE_SYSREG32(d->v3.apr1[1], ICH_AP1R1_EL2); + WRITE_SYSREG(d->v3.apr0[1], ICH_AP0R1_EL2); + WRITE_SYSREG(d->v3.apr1[1], ICH_AP1R1_EL2); /* Fall through */ case 5: - WRITE_SYSREG32(d->v3.apr0[0], ICH_AP0R0_EL2); - WRITE_SYSREG32(d->v3.apr1[0], ICH_AP1R0_EL2); + WRITE_SYSREG(d->v3.apr0[0], ICH_AP0R0_EL2); + WRITE_SYSREG(d->v3.apr1[0], ICH_AP1R0_EL2); break; default: BUG(); @@ -338,16 +338,16 @@ static void save_aprn_regs(union gic_state_data *d) switch ( gicv3.nr_priorities ) { case 7: - d->v3.apr0[2] =3D READ_SYSREG32(ICH_AP0R2_EL2); - d->v3.apr1[2] =3D READ_SYSREG32(ICH_AP1R2_EL2); + d->v3.apr0[2] =3D READ_SYSREG(ICH_AP0R2_EL2); + d->v3.apr1[2] =3D READ_SYSREG(ICH_AP1R2_EL2); /* Fall through */ case 6: - d->v3.apr0[1] =3D READ_SYSREG32(ICH_AP0R1_EL2); - d->v3.apr1[1] =3D READ_SYSREG32(ICH_AP1R1_EL2); + d->v3.apr0[1] =3D READ_SYSREG(ICH_AP0R1_EL2); + d->v3.apr1[1] =3D READ_SYSREG(ICH_AP1R1_EL2); /* Fall through */ case 5: - d->v3.apr0[0] =3D READ_SYSREG32(ICH_AP0R0_EL2); - d->v3.apr1[0] =3D READ_SYSREG32(ICH_AP1R0_EL2); + d->v3.apr0[0] =3D READ_SYSREG(ICH_AP0R0_EL2); + d->v3.apr1[0] =3D READ_SYSREG(ICH_AP1R0_EL2); break; default: BUG(); @@ -371,15 +371,15 @@ static void gicv3_save_state(struct vcpu *v) dsb(sy); gicv3_save_lrs(v); save_aprn_regs(&v->arch.gic); - v->arch.gic.v3.vmcr =3D READ_SYSREG32(ICH_VMCR_EL2); - v->arch.gic.v3.sre_el1 =3D READ_SYSREG32(ICC_SRE_EL1); + v->arch.gic.v3.vmcr =3D READ_SYSREG(ICH_VMCR_EL2); + v->arch.gic.v3.sre_el1 =3D READ_SYSREG(ICC_SRE_EL1); } =20 static void gicv3_restore_state(const struct vcpu *v) { - uint32_t val; + register_t val; =20 - val =3D READ_SYSREG32(ICC_SRE_EL2); + val =3D READ_SYSREG(ICC_SRE_EL2); /* * Don't give access to system registers when the guest is using * GICv2 @@ -388,7 +388,7 @@ static void gicv3_restore_state(const struct vcpu *v) val &=3D ~GICC_SRE_EL2_ENEL1; else val |=3D GICC_SRE_EL2_ENEL1; - WRITE_SYSREG32(val, ICC_SRE_EL2); + WRITE_SYSREG(val, ICC_SRE_EL2); =20 /* * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a Group0 @@ -398,9 +398,9 @@ static void gicv3_restore_state(const struct vcpu *v) * want before starting to mess with the rest of the GIC, and * VMCR_EL1 in particular. */ - WRITE_SYSREG32(v->arch.gic.v3.sre_el1, ICC_SRE_EL1); + WRITE_SYSREG(v->arch.gic.v3.sre_el1, ICC_SRE_EL1); isb(); - WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); + WRITE_SYSREG(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); restore_aprn_regs(&v->arch.gic); gicv3_restore_lrs(v); =20 @@ -468,24 +468,25 @@ static void gicv3_mask_irq(struct irq_desc *irqd) static void gicv3_eoi_irq(struct irq_desc *irqd) { /* Lower the priority */ - WRITE_SYSREG32(irqd->irq, ICC_EOIR1_EL1); + WRITE_SYSREG(irqd->irq, ICC_EOIR1_EL1); isb(); } =20 static void gicv3_dir_irq(struct irq_desc *irqd) { /* Deactivate */ - WRITE_SYSREG32(irqd->irq, ICC_DIR_EL1); + WRITE_SYSREG(irqd->irq, ICC_DIR_EL1); isb(); } =20 static unsigned int gicv3_read_irq(void) { - unsigned int irq =3D READ_SYSREG32(ICC_IAR1_EL1); + register_t irq =3D READ_SYSREG(ICC_IAR1_EL1); =20 dsb(sy); =20 - return irq; + /* IRQs are encoded using 23bit. */ + return (irq & GICC_IAR_INTID_MASK); } =20 /* @@ -857,16 +858,16 @@ static int gicv3_cpu_init(void) gicv3_enable_sre(); =20 /* No priority grouping */ - WRITE_SYSREG32(0, ICC_BPR1_EL1); + WRITE_SYSREG(0, ICC_BPR1_EL1); =20 /* Set priority mask register */ - WRITE_SYSREG32(DEFAULT_PMR_VALUE, ICC_PMR_EL1); + WRITE_SYSREG(DEFAULT_PMR_VALUE, ICC_PMR_EL1); =20 /* EOI drops priority, DIR deactivates the interrupt (mode 1) */ - WRITE_SYSREG32(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1); + WRITE_SYSREG(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1); =20 /* Enable Group1 interrupts */ - WRITE_SYSREG32(1, ICC_IGRPEN1_EL1); + WRITE_SYSREG(1, ICC_IGRPEN1_EL1); =20 /* Sync at once at the end of cpu interface configuration */ isb(); @@ -876,15 +877,15 @@ static int gicv3_cpu_init(void) =20 static void gicv3_cpu_disable(void) { - WRITE_SYSREG32(0, ICC_CTLR_EL1); + WRITE_SYSREG(0, ICC_CTLR_EL1); isb(); } =20 static void gicv3_hyp_init(void) { - uint32_t vtr; + register_t vtr; =20 - vtr =3D READ_SYSREG32(ICH_VTR_EL2); + vtr =3D READ_SYSREG(ICH_VTR_EL2); gicv3_info.nr_lrs =3D (vtr & ICH_VTR_NRLRGS) + 1; gicv3.nr_priorities =3D ((vtr >> ICH_VTR_PRIBITS_SHIFT) & ICH_VTR_PRIBITS_MASK) + 1; @@ -892,8 +893,8 @@ static void gicv3_hyp_init(void) if ( !((gicv3.nr_priorities > 4) && (gicv3.nr_priorities < 8)) ) panic("GICv3: Invalid number of priority bits\n"); =20 - WRITE_SYSREG32(ICH_VMCR_EOI | ICH_VMCR_VENG1, ICH_VMCR_EL2); - WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2); + WRITE_SYSREG(ICH_VMCR_EOI | ICH_VMCR_VENG1, ICH_VMCR_EL2); + WRITE_SYSREG(GICH_HCR_EN, ICH_HCR_EL2); } =20 /* Set up the per-CPU parts of the GIC for a secondary CPU */ @@ -917,11 +918,11 @@ out: =20 static void gicv3_hyp_disable(void) { - uint32_t hcr; + register_t hcr; =20 - hcr =3D READ_SYSREG32(ICH_HCR_EL2); + hcr =3D READ_SYSREG(ICH_HCR_EL2); hcr &=3D ~GICH_HCR_EN; - WRITE_SYSREG32(hcr, ICH_HCR_EL2); + WRITE_SYSREG(hcr, ICH_HCR_EL2); isb(); } =20 @@ -1140,39 +1141,44 @@ static void gicv3_write_lr(int lr_reg, const struct= gic_lr *lr) =20 static void gicv3_hcr_status(uint32_t flag, bool status) { - uint32_t hcr; + register_t hcr; =20 - hcr =3D READ_SYSREG32(ICH_HCR_EL2); + hcr =3D READ_SYSREG(ICH_HCR_EL2); if ( status ) - WRITE_SYSREG32(hcr | flag, ICH_HCR_EL2); + WRITE_SYSREG(hcr | flag, ICH_HCR_EL2); else - WRITE_SYSREG32(hcr & (~flag), ICH_HCR_EL2); + WRITE_SYSREG(hcr & (~flag), ICH_HCR_EL2); isb(); } =20 static unsigned int gicv3_read_vmcr_priority(void) { - return ((READ_SYSREG32(ICH_VMCR_EL2) >> ICH_VMCR_PRIORITY_SHIFT) & + return ((READ_SYSREG(ICH_VMCR_EL2) >> ICH_VMCR_PRIORITY_SHIFT) & ICH_VMCR_PRIORITY_MASK); } =20 /* Only support reading GRP1 APRn registers */ static unsigned int gicv3_read_apr(int apr_reg) { + register_t apr; + switch ( apr_reg ) { case 0: ASSERT(gicv3.nr_priorities > 4 && gicv3.nr_priorities < 8); - return READ_SYSREG32(ICH_AP1R0_EL2); + apr =3D READ_SYSREG(ICH_AP1R0_EL2); case 1: ASSERT(gicv3.nr_priorities > 5 && gicv3.nr_priorities < 8); - return READ_SYSREG32(ICH_AP1R1_EL2); + apr =3D READ_SYSREG(ICH_AP1R1_EL2); case 2: ASSERT(gicv3.nr_priorities > 6 && gicv3.nr_priorities < 8); - return READ_SYSREG32(ICH_AP1R2_EL2); + apr =3D READ_SYSREG(ICH_AP1R2_EL2); default: BUG(); } + + /* Number of priority levels do not exceed 32bit. */ + return apr; } =20 static bool gicv3_read_pending_state(struct irq_desc *irqd) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 5069ab4aac..c7f0c343d1 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -171,9 +171,9 @@ * GICv3 registers that needs to be saved/restored */ struct gic_v3 { - uint32_t vmcr, sre_el1; - uint32_t apr0[4]; - uint32_t apr1[4]; + register_t vmcr, sre_el1; + register_t apr0[4]; + register_t apr1[4]; uint64_t lr[16]; }; #endif diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3= _defs.h index 5a578e7c11..34ed5f857d 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -45,6 +45,8 @@ #define GICC_SRE_EL2_DIB (1UL << 2) #define GICC_SRE_EL2_ENEL1 (1UL << 3) =20 +#define GICC_IAR_INTID_MASK (0xFFFFFF) + /* Additional bits in GICD_TYPER defined by GICv3 */ #define GICD_TYPE_ID_BITS_SHIFT 19 #define GICD_TYPE_ID_BITS(r) ((((r) >> GICD_TYPE_ID_BITS_SHIFT) & 0x1f)= + 1) --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tue, 27 Apr 2021 09:36:25 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 936cbc0e-97a9-4437-bdb8-34e6d9e003d6; Tue, 27 Apr 2021 09:36:08 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4243DED1; Tue, 27 Apr 2021 02:36:08 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A000A3F694; Tue, 27 Apr 2021 02:36:06 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 936cbc0e-97a9-4437-bdb8-34e6d9e003d6 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, Julien Grall Subject: [PATCH v2 06/10] arm/p2m: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:42 +0200 Message-Id: <20210427093546.30703-7-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of vtcr to register_t. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/p2m.c | 8 ++++---- xen/arch/arm/traps.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index ac50312620..d414c4feb9 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1973,11 +1973,11 @@ void __init p2m_restrict_ipa_bits(unsigned int ipa_= bits) } =20 /* VTCR value to be configured by all CPUs. Set only once by the boot CPU = */ -static uint32_t __read_mostly vtcr; +static register_t __read_mostly vtcr; =20 static void setup_virt_paging_one(void *data) { - WRITE_SYSREG32(vtcr, VTCR_EL2); + WRITE_SYSREG(vtcr, VTCR_EL2); =20 /* * ARM64_WORKAROUND_AT_SPECULATE: We want to keep the TLBs free from @@ -2000,7 +2000,7 @@ static void setup_virt_paging_one(void *data) void __init setup_virt_paging(void) { /* Setup Stage 2 address translation */ - unsigned long val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0= _WBWA; + register_t val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WB= WA; =20 #ifdef CONFIG_ARM_32 if ( p2m_ipa_bits < 40 ) @@ -2089,7 +2089,7 @@ void __init setup_virt_paging(void) pa_range_info[pa_range].pabits, ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); #endif - printk("P2M: %d levels with order-%d root, VTCR 0x%lx\n", + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); =20 p2m_vmid_allocator_init(); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ccc0827107..c7acdb2087 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -911,7 +911,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, show_registers_32(regs, ctxt, guest_mode, v); #endif } - printk(" VTCR_EL2: %08"PRIx32"\n", READ_SYSREG32(VTCR_EL2)); + printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); printk("\n"); =20 --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; 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Tue, 27 Apr 2021 02:36:52 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118161.224215 (Exim 4.92) (envelope-from ) id 1lbK8t-0007CP-Ta; Tue, 27 Apr 2021 09:36:31 +0000 Received: by outflank-mailman (output) from mailman id 118161.224215; Tue, 27 Apr 2021 09:36:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8t-0007CF-PW; Tue, 27 Apr 2021 09:36:31 +0000 Received: by outflank-mailman (input) for mailman id 118161; Tue, 27 Apr 2021 09:36:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8s-0006jJ-BB for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:30 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id eb4f75da-ec1a-4229-9c12-0fb90e007502; Tue, 27 Apr 2021 09:36:18 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F4EF101E; Tue, 27 Apr 2021 02:36:18 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9FDCB3F694; Tue, 27 Apr 2021 02:36:08 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: eb4f75da-ec1a-4229-9c12-0fb90e007502 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 07/10] arm/mm: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:43 +0200 Message-Id: <20210427093546.30703-8-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify SCTLR_EL2 accesses to use READ/WRITE_SYSREG. SCTLR_EL2 already has bits defined in the range [32:63]. The ARM ARM defines them as unknown if implemented. By writing in head.S SCTLR_EL2_SET we are zeroing the upper 32bit half which is correct but referring to this sysreg as 32bit is a latent bug because the top 32bit was not used by Xen. Signed-off-by: Michal Orzel --- Changes since v1: -Update commit message with SCTLR_EL2 analysis --- xen/arch/arm/mm.c | 2 +- xen/arch/arm/traps.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 59f8a3f15f..0e07335291 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -613,7 +613,7 @@ void __init remove_early_mappings(void) */ static void xen_pt_enforce_wnx(void) { - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_Axx_ELx_WXN, SCTLR_EL2= ); + WRITE_SYSREG(READ_SYSREG(SCTLR_EL2) | SCTLR_Axx_ELx_WXN, SCTLR_EL2); /* * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized * before flushing the TLBs. diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index c7acdb2087..e7384381cc 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -915,7 +915,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); printk("\n"); =20 - printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2)); + printk(" SCTLR_EL2: %"PRIregister"\n", READ_SYSREG(SCTLR_EL2)); printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516203; cv=none; d=zohomail.com; s=zohoarc; b=agpOpsr7nWyl03eY9BeY64qtg6uJFdrGjS+coU6yHsk8IuNiUo/63AoDADP7XJWuO3kvdLbz3U3LMdFKBmVd4zp/93/Oj8IFJoTP9SyO7pNCrcsDVQl3Z6pmFHuo9rvX2oHaseRa8s9nhBZbAvxBtkXzyozMt4YtYb5YRFo5nbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516203; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d4W4yZFsi2Cmw5GaAJJVsuVncwqk2o0D4F77iK+XU2o=; b=eTl83LXR0kCHsgzH9Y7tM81AQWC1VQaIjXFOz6xSWuN9Br2MWkr9BmIcI+sfwpdHZ+hd92hE6a73ssPiIM5qkBU3zwGtyMWJfOogokcws8YhlyzyNimTAgU3WBdsF1EfNeepX3xdHZ37iXyD+cltrWzqUZFCbL7yuceSEQMBdjI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516203678908.6007813274018; Tue, 27 Apr 2021 02:36:43 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118158.224203 (Exim 4.92) (envelope-from ) id 1lbK8s-0007AA-Jf; Tue, 27 Apr 2021 09:36:30 +0000 Received: by outflank-mailman (output) from mailman id 118158.224203; Tue, 27 Apr 2021 09:36:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8s-0007A2-FG; Tue, 27 Apr 2021 09:36:30 +0000 Received: by outflank-mailman (input) for mailman id 118158; Tue, 27 Apr 2021 09:36:29 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK8q-00078W-Th for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:28 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id a2e6f0ca-dac9-499f-b95e-afb98979a864; Tue, 27 Apr 2021 09:36:27 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84C9BD6E; Tue, 27 Apr 2021 02:36:27 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A03933F694; Tue, 27 Apr 2021 02:36:18 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a2e6f0ca-dac9-499f-b95e-afb98979a864 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com, Julien Grall Subject: [PATCH v2 08/10] arm/page: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:44 +0200 Message-Id: <20210427093546.30703-9-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify accesses to CTR_EL0 to use READ/WRITE_SYSREG. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/include/asm-arm/page.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 131507a517..c6f9fb0d4e 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -137,10 +137,10 @@ extern size_t dcache_line_bytes; =20 static inline size_t read_dcache_line_bytes(void) { - uint32_t ctr; + register_t ctr; =20 /* Read CTR */ - ctr =3D READ_SYSREG32(CTR_EL0); + ctr =3D READ_SYSREG(CTR_EL0); =20 /* Bits 16-19 are the log2 number of words in the cacheline. */ return (size_t) (4 << ((ctr >> 16) & 0xf)); --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516225; cv=none; d=zohomail.com; s=zohoarc; b=Q1+3eZ/mvirYJRJnDpkH1iGhUz08c339mpejDrrOstkGJ3Jvv1/17Bw9UaJ465zA4E0027IlijbLJ23NULMbUxbpYKUHyi1Ox7YF/e8F5qHQOrDml3TWfWVkBpzNA38+Q+sCsSCiySbqutZsproC9BAkaGT5O32JC4+404YtPcs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516225; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=drpGrE4QQ+AvD7GPCQj+2JYr5Ztr38oPWnfAv8W2mfU=; b=OzUs5gReU8DWOfvrc1eIDhm6FSK/A6xHLy7GUyP3Uim16XWUO6lYFLYTP82q5jKfDHGVY0RBOkRRuZ8EZCIOTskb2lEaJ0YdWpILCXQafXnJs/iphvEsz1gneZ1iECmN2UqQwOylvY+yRhxaIb5is8iEgwjI90R5tLUIPMpKdO8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516225779808.128867599986; Tue, 27 Apr 2021 02:37:05 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118172.224226 (Exim 4.92) (envelope-from ) id 1lbK96-0007Qw-9W; Tue, 27 Apr 2021 09:36:44 +0000 Received: by outflank-mailman (output) from mailman id 118172.224226; Tue, 27 Apr 2021 09:36:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK96-0007Qp-63; Tue, 27 Apr 2021 09:36:44 +0000 Received: by outflank-mailman (input) for mailman id 118172; Tue, 27 Apr 2021 09:36:42 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK94-00078W-Oz for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:42 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 120e5367-5bcb-46fe-b6dc-58acf6d94cd0; Tue, 27 Apr 2021 09:36:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1237ED1; Tue, 27 Apr 2021 02:36:29 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF6FF3F694; Tue, 27 Apr 2021 02:36:27 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 120e5367-5bcb-46fe-b6dc-58acf6d94cd0 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH v2 09/10] arm/time,vtimer: Get rid of READ/WRITE_SYSREG32 Date: Tue, 27 Apr 2021 11:35:45 +0200 Message-Id: <20210427093546.30703-10-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of vtimer structure's member: ctl to register_t. Add macro CNTFRQ_MASK containing mask for timer clock frequency field of CNTFRQ_EL0 register. Modify CNTx_CTL_MASK to return unsigned long instead of unsigned int as ctl is now of type register_t. Signed-off-by: Michal Orzel Acked-by: Julien Grall --- Changes since v1: -Add macro CNTFRQ_MASK -Modify CNTx_CTL_MASK, CNTx_CTL_ENABLE, CNTx_CTL_PENDING to return ul --- xen/arch/arm/time.c | 28 ++++++++++++++-------------- xen/arch/arm/vtimer.c | 10 +++++----- xen/include/asm-arm/domain.h | 2 +- xen/include/asm-arm/processor.h | 9 ++++++--- 4 files changed, 26 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index b0021c2c69..7dbd363537 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -145,7 +145,7 @@ void __init preinit_xen_time(void) preinit_acpi_xen_time(); =20 if ( !cpu_khz ) - cpu_khz =3D READ_SYSREG32(CNTFRQ_EL0) / 1000; + cpu_khz =3D (READ_SYSREG(CNTFRQ_EL0) & CNTFRQ_MASK) / 1000; =20 res =3D platform_init_time(); if ( res ) @@ -205,13 +205,13 @@ int reprogram_timer(s_time_t timeout) =20 if ( timeout =3D=3D 0 ) { - WRITE_SYSREG32(0, CNTHP_CTL_EL2); + WRITE_SYSREG(0, CNTHP_CTL_EL2); return 1; } =20 deadline =3D ns_to_ticks(timeout) + boot_count; WRITE_SYSREG64(deadline, CNTHP_CVAL_EL2); - WRITE_SYSREG32(CNTx_CTL_ENABLE, CNTHP_CTL_EL2); + WRITE_SYSREG(CNTx_CTL_ENABLE, CNTHP_CTL_EL2); isb(); =20 /* No need to check for timers in the past; the Generic Timer fires @@ -223,23 +223,23 @@ int reprogram_timer(s_time_t timeout) static void timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *r= egs) { if ( irq =3D=3D (timer_irq[TIMER_HYP_PPI]) && - READ_SYSREG32(CNTHP_CTL_EL2) & CNTx_CTL_PENDING ) + READ_SYSREG(CNTHP_CTL_EL2) & CNTx_CTL_PENDING ) { perfc_incr(hyp_timer_irqs); /* Signal the generic timer code to do its work */ raise_softirq(TIMER_SOFTIRQ); /* Disable the timer to avoid more interrupts */ - WRITE_SYSREG32(0, CNTHP_CTL_EL2); + WRITE_SYSREG(0, CNTHP_CTL_EL2); } =20 if ( irq =3D=3D (timer_irq[TIMER_PHYS_NONSECURE_PPI]) && - READ_SYSREG32(CNTP_CTL_EL0) & CNTx_CTL_PENDING ) + READ_SYSREG(CNTP_CTL_EL0) & CNTx_CTL_PENDING ) { perfc_incr(phys_timer_irqs); /* Signal the generic timer code to do its work */ raise_softirq(TIMER_SOFTIRQ); /* Disable the timer to avoid more interrupts */ - WRITE_SYSREG32(0, CNTP_CTL_EL0); + WRITE_SYSREG(0, CNTP_CTL_EL0); } } =20 @@ -260,8 +260,8 @@ static void vtimer_interrupt(int irq, void *dev_id, str= uct cpu_user_regs *regs) =20 perfc_incr(virt_timer_irqs); =20 - current->arch.virt_timer.ctl =3D READ_SYSREG32(CNTV_CTL_EL0); - WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_= EL0); + current->arch.virt_timer.ctl =3D READ_SYSREG(CNTV_CTL_EL0); + WRITE_SYSREG(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL= 0); vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq= , true); } =20 @@ -297,9 +297,9 @@ void init_timer_interrupt(void) /* Sensible defaults */ WRITE_SYSREG64(0, CNTVOFF_EL2); /* No VM-specific offset */ /* Do not let the VMs program the physical timer, only read the physic= al counter */ - WRITE_SYSREG32(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2); - WRITE_SYSREG32(0, CNTP_CTL_EL0); /* Physical timer disabled */ - WRITE_SYSREG32(0, CNTHP_CTL_EL2); /* Hypervisor's timer disabled */ + WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2); + WRITE_SYSREG(0, CNTP_CTL_EL0); /* Physical timer disabled */ + WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Hypervisor's timer disabled */ isb(); =20 request_irq(timer_irq[TIMER_HYP_PPI], 0, timer_interrupt, @@ -320,8 +320,8 @@ void init_timer_interrupt(void) */ static void deinit_timer_interrupt(void) { - WRITE_SYSREG32(0, CNTP_CTL_EL0); /* Disable physical timer */ - WRITE_SYSREG32(0, CNTHP_CTL_EL2); /* Disable hypervisor's timer */ + WRITE_SYSREG(0, CNTP_CTL_EL0); /* Disable physical timer */ + WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Disable hypervisor's timer */ isb(); =20 release_irq(timer_irq[TIMER_HYP_PPI], NULL); diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index c2b27915c6..167fc6127a 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -138,8 +138,8 @@ void virt_timer_save(struct vcpu *v) { ASSERT(!is_idle_vcpu(v)); =20 - v->arch.virt_timer.ctl =3D READ_SYSREG32(CNTV_CTL_EL0); - WRITE_SYSREG32(v->arch.virt_timer.ctl & ~CNTx_CTL_ENABLE, CNTV_CTL_EL0= ); + v->arch.virt_timer.ctl =3D READ_SYSREG(CNTV_CTL_EL0); + WRITE_SYSREG(v->arch.virt_timer.ctl & ~CNTx_CTL_ENABLE, CNTV_CTL_EL0); v->arch.virt_timer.cval =3D READ_SYSREG64(CNTV_CVAL_EL0); if ( (v->arch.virt_timer.ctl & CNTx_CTL_ENABLE) && !(v->arch.virt_timer.ctl & CNTx_CTL_MASK)) @@ -159,7 +159,7 @@ void virt_timer_restore(struct vcpu *v) =20 WRITE_SYSREG64(v->domain->arch.virt_timer_base.offset, CNTVOFF_EL2); WRITE_SYSREG64(v->arch.virt_timer.cval, CNTV_CVAL_EL0); - WRITE_SYSREG32(v->arch.virt_timer.ctl, CNTV_CTL_EL0); + WRITE_SYSREG(v->arch.virt_timer.ctl, CNTV_CTL_EL0); } =20 static bool vtimer_cntp_ctl(struct cpu_user_regs *regs, uint32_t *r, bool = read) @@ -347,7 +347,7 @@ bool vtimer_emulate(struct cpu_user_regs *regs, union h= sr hsr) } =20 static void vtimer_update_irq(struct vcpu *v, struct vtimer *vtimer, - uint32_t vtimer_ctl) + register_t vtimer_ctl) { bool level; =20 @@ -389,7 +389,7 @@ void vtimer_update_irqs(struct vcpu *v) * but this requires reworking the arch timer to implement this. */ vtimer_update_irq(v, &v->arch.virt_timer, - READ_SYSREG32(CNTV_CTL_EL0) & ~CNTx_CTL_MASK); + READ_SYSREG(CNTV_CTL_EL0) & ~CNTx_CTL_MASK); =20 /* For the physical timer we rely on our emulated state. */ vtimer_update_irq(v, &v->arch.phys_timer, v->arch.phys_timer.ctl); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 2d4f38c669..c9277b5c6d 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -36,7 +36,7 @@ struct vtimer { struct vcpu *v; int irq; struct timer timer; - uint32_t ctl; + register_t ctl; uint64_t cval; }; =20 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processo= r.h index 5c1768cdec..2058b69447 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -484,9 +484,12 @@ extern register_t __cpu_logical_map[]; #define CNTKCTL_EL1_EL0PTEN (1u<<9) /* Expose phys timer registers to EL0= */ =20 /* Timer control registers */ -#define CNTx_CTL_ENABLE (1u<<0) /* Enable timer */ -#define CNTx_CTL_MASK (1u<<1) /* Mask IRQ */ -#define CNTx_CTL_PENDING (1u<<2) /* IRQ pending */ +#define CNTx_CTL_ENABLE (1ul<<0) /* Enable timer */ +#define CNTx_CTL_MASK (1ul<<1) /* Mask IRQ */ +#define CNTx_CTL_PENDING (1ul<<2) /* IRQ pending */ + +/* Timer frequency mask */ +#define CNTFRQ_MASK GENMASK(31, 0) =20 /* Exception Vector offsets */ /* ... ARM32 */ --=20 2.29.0 From nobody Fri Apr 26 17:39:44 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1619516230; cv=none; d=zohomail.com; s=zohoarc; b=OosPQqA10pSHG95UGa2bi1qKP5ecnxGq/ZwRZpSJPSkHvymJqfziCkCrt4KY926rf5uU5Yrr6vxUXdCuwV7Fc1VkBg7bhO6VIW3NZLorbYkOIMxvxmgQ6QVshM53ANOLiFkxz6kfLqbiBSnOHuemvIqUK2TaBd0vuEvQ57Ed2PE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619516230; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k4lNHuvoMaMrKeTh74FCM5ijbhN+IQC+SN/KipzSoaw=; b=ITnSUx9+Pt8v/BuHUh+iYSX3rasmik+756oXzCdaTFoTjjkfIFWsE3z7RTbIV5/B+sgFZsu/sVwXsB9EC2cdqEpKjB6g7LItIPlq8ku2cONUzsHCbaqck7o4ImKS14cxfPBd/VIRQ/RTof+oojaoyzGoun9k+myonTkUCOR8xA8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619516230451573.8711632952361; Tue, 27 Apr 2021 02:37:10 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.118177.224239 (Exim 4.92) (envelope-from ) id 1lbK9B-0007WN-KY; Tue, 27 Apr 2021 09:36:49 +0000 Received: by outflank-mailman (output) from mailman id 118177.224239; Tue, 27 Apr 2021 09:36:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK9B-0007WE-GN; Tue, 27 Apr 2021 09:36:49 +0000 Received: by outflank-mailman (input) for mailman id 118177; Tue, 27 Apr 2021 09:36:47 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lbK99-00078W-Ox for xen-devel@lists.xenproject.org; Tue, 27 Apr 2021 09:36:47 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 96b9f535-4541-4d69-af90-8d7a9be5f886; Tue, 27 Apr 2021 09:36:35 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 598EDD6E; Tue, 27 Apr 2021 02:36:35 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.27.22]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 93FD03F7B4; Tue, 27 Apr 2021 02:36:32 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 96b9f535-4541-4d69-af90-8d7a9be5f886 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , bertrand.marquis@arm.com Subject: [PATCH v2 10/10] arm64: Change type of hsr, cpsr, spsr_el1 to uint64_t Date: Tue, 27 Apr 2021 11:35:46 +0200 Message-Id: <20210427093546.30703-11-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210427093546.30703-1-michal.orzel@arm.com> References: <20210427093546.30703-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 registers are 64bit whereas AArch32 registers are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 registers have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of hsr, cpsr, spsr_el1 to uint64_t. Add 32bit RES0 members to structures inside hsr union. Remove 32bit padding in cpu_user_regs before spsr_fiq as it is no longer needed due to upper union being 64bit now. Add 64bit padding in cpu_user_regs before spsr_el1 because offset of spsr_el1 must be a multiple of 8. Signed-off-by: Michal Orzel --- Changes since v1: -Modify type of cpsr, spsr_el1 -Remove ifdefery in hsr union protecting _res0 members -Fix formatting of printk calls --- xen/arch/arm/arm64/entry.S | 4 ++-- xen/arch/arm/arm64/traps.c | 2 +- xen/arch/arm/arm64/vsysreg.c | 3 ++- xen/arch/arm/domain.c | 2 +- xen/arch/arm/traps.c | 30 +++++++++++++++------------ xen/arch/arm/vcpreg.c | 13 ++++++------ xen/include/asm-arm/arm64/processor.h | 11 +++++----- xen/include/asm-arm/hsr.h | 14 ++++++++++++- xen/include/public/arch-arm.h | 4 ++-- xen/include/public/vm_event.h | 4 ++++ 10 files changed, 55 insertions(+), 32 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index ab9a65fc14..fc3811ad0a 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -155,7 +155,7 @@ add x21, sp, #UREGS_CPSR mrs x22, spsr_el2 mrs x23, esr_el2 - stp w22, w23, [x21] + stp x22, x23, [x21] =20 .endm =20 @@ -432,7 +432,7 @@ return_from_trap: msr daifset, #IFLAGS___I_ /* Mask interrupts */ =20 ldr x21, [sp, #UREGS_PC] /* load ELR */ - ldr w22, [sp, #UREGS_CPSR] /* load SPSR */ + ldr x22, [sp, #UREGS_CPSR] /* load SPSR */ =20 pop x0, x1 pop x2, x3 diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c index babfc1d884..9113a15c7a 100644 --- a/xen/arch/arm/arm64/traps.c +++ b/xen/arch/arm/arm64/traps.c @@ -36,7 +36,7 @@ void do_bad_mode(struct cpu_user_regs *regs, int reason) union hsr hsr =3D { .bits =3D regs->hsr }; =20 printk("Bad mode in %s handler detected\n", handler[reason]); - printk("ESR=3D0x%08"PRIx32": EC=3D%"PRIx32", IL=3D%"PRIx32", ISS=3D%"= PRIx32"\n", + printk("ESR=3D%#"PRIregister": EC=3D%"PRIx32", IL=3D%"PRIx32", ISS=3D= %"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); =20 local_irq_disable(); diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 41f18612c6..caf17174b8 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -368,7 +368,8 @@ void do_sysreg(struct cpu_user_regs *regs, sysreg.op2, sysreg.read ? "=3D>" : "<=3D", sysreg.reg, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", + gdprintk(XENLOG_ERR, + "unhandled 64-bit sysreg access %#"PRIregister"\n", hsr.bits & HSR_SYSREG_REGS_MASK); inject_undef_exception(regs, hsr); return; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index c021a03c61..74bdbb9082 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -845,7 +845,7 @@ static int is_guest_pv32_psr(uint32_t psr) =20 =20 #ifdef CONFIG_ARM_64 -static int is_guest_pv64_psr(uint32_t psr) +static int is_guest_pv64_psr(uint64_t psr) { if ( psr & PSR_MODE_BIT ) return 0; diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index e7384381cc..c8f9773566 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -546,7 +546,7 @@ void inject_undef64_exception(struct cpu_user_regs *reg= s, int instr_len) PSR_IRQ_MASK | PSR_DBG_MASK; regs->pc =3D handler; =20 - WRITE_SYSREG32(esr.bits, ESR_EL1); + WRITE_SYSREG(esr.bits, ESR_EL1); } =20 /* Inject an abort exception into a 64 bit guest */ @@ -580,7 +580,7 @@ static void inject_abt64_exception(struct cpu_user_regs= *regs, regs->pc =3D handler; =20 WRITE_SYSREG(addr, FAR_EL1); - WRITE_SYSREG32(esr.bits, ESR_EL1); + WRITE_SYSREG(esr.bits, ESR_EL1); } =20 static void inject_dabt64_exception(struct cpu_user_regs *regs, @@ -717,7 +717,7 @@ struct reg_ctxt { uint64_t vttbr_el2; }; =20 -static const char *mode_string(uint32_t cpsr) +static const char *mode_string(register_t cpsr) { uint32_t mode; static const char *mode_strings[] =3D { @@ -756,14 +756,16 @@ static void show_registers_32(const struct cpu_user_r= egs *regs, #ifdef CONFIG_ARM_64 BUG_ON( ! (regs->cpsr & PSR_MODE_BIT) ); printk("PC: %08"PRIx32"\n", regs->pc32); + printk("CPSR: %016"PRIx64" MODE:%s\n", regs->cpsr, + mode_string(regs->cpsr)); #else printk("PC: %08"PRIx32, regs->pc); if ( !guest_mode ) printk(" %pS", _p(regs->pc)); printk("\n"); -#endif printk("CPSR: %08"PRIx32" MODE:%s\n", regs->cpsr, mode_string(regs->cpsr)); +#endif printk(" R0: %08"PRIx32" R1: %08"PRIx32" R2: %08"PRIx32" R3: %08"P= RIx32"\n", regs->r0, regs->r1, regs->r2, regs->r3); printk(" R4: %08"PRIx32" R5: %08"PRIx32" R6: %08"PRIx32" R7: %08"P= RIx32"\n", @@ -846,7 +848,7 @@ static void show_registers_64(const struct cpu_user_reg= s *regs, { printk("SP: %016"PRIx64"\n", regs->sp); } - printk("CPSR: %08"PRIx32" MODE:%s\n", regs->cpsr, + printk("CPSR: %016"PRIx64" MODE:%s\n", regs->cpsr, mode_string(regs->cpsr)); printk(" X0: %016"PRIx64" X1: %016"PRIx64" X2: %016"PRIx64"\n", regs->x0, regs->x1, regs->x2); @@ -919,7 +921,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); - printk(" ESR_EL2: %08"PRIx32"\n", regs->hsr); + printk(" ESR_EL2: %"PRIregister"\n", regs->hsr); printk(" HPFAR_EL2: %"PRIregister"\n", READ_SYSREG(HPFAR_EL2)); =20 #ifdef CONFIG_ARM_32 @@ -1599,7 +1601,7 @@ static const unsigned short cc_map[16] =3D { =20 int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hs= r) { - unsigned long cpsr, cpsr_cond; + register_t cpsr, cpsr_cond; int cond; =20 /* @@ -1661,7 +1663,7 @@ int check_conditional_instr(struct cpu_user_regs *reg= s, const union hsr hsr) =20 void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) { - unsigned long itbits, cond, cpsr =3D regs->cpsr; + register_t itbits, cond, cpsr =3D regs->cpsr; bool is_thumb =3D psr_mode_is_32bit(regs) && (cpsr & PSR_THUMB); =20 if ( is_thumb && (cpsr & PSR_IT_MASK) ) @@ -2004,13 +2006,15 @@ static void do_trap_stage2_abort_guest(struct cpu_u= ser_regs *regs, =20 break; default: - gprintk(XENLOG_WARNING, "Unsupported FSC: HSR=3D%#x DFSC=3D%#x\n", + gprintk(XENLOG_WARNING, + "Unsupported FSC: HSR=3D%#"PRIregister" DFSC=3D%#x\n", hsr.bits, xabt.fsc); } =20 inject_abt: - gdprintk(XENLOG_DEBUG, "HSR=3D0x%x pc=3D%#"PRIregister" gva=3D%#"PRIva= ddr - " gpa=3D%#"PRIpaddr"\n", hsr.bits, regs->pc, gva, gpa); + gdprintk(XENLOG_DEBUG, + "HSR=3D%#"PRIregister" pc=3D%#"PRIregister" gva=3D%#"PRIvaddr= " gpa=3D%#"PRIpaddr"\n", + hsr.bits, regs->pc, gva, gpa); if ( is_data ) inject_dabt_exception(regs, gva, hsr.len); else @@ -2204,7 +2208,7 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) =20 default: gprintk(XENLOG_WARNING, - "Unknown Guest Trap. HSR=3D0x%x EC=3D0x%x IL=3D%x Syndrome= =3D0x%"PRIx32"\n", + "Unknown Guest Trap. HSR=3D%#"PRIregister" EC=3D0x%x IL=3D= %x Syndrome=3D0x%"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); inject_undef_exception(regs, hsr); } @@ -2242,7 +2246,7 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs) break; } default: - printk("Hypervisor Trap. HSR=3D0x%x EC=3D0x%x IL=3D%x Syndrome=3D0= x%"PRIx32"\n", + printk("Hypervisor Trap. HSR=3D%#"PRIregister" EC=3D0x%x IL=3D%x S= yndrome=3D0x%"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); do_unexpected_trap("Hypervisor", regs); } diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 55351fc087..f0cdcc8a54 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -385,7 +385,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union= hsr hsr) "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); inject_undef_exception(regs, hsr); return; @@ -454,7 +454,8 @@ void do_cp15_64(struct cpu_user_regs *regs, const union= hsr hsr) "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", cp64.read ? "mrrc" : "mcrr", cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", + gdprintk(XENLOG_ERR, + "unhandled 64-bit CP15 access %#"PRIregister"\n", hsr.bits & HSR_CP64_REGS_MASK); inject_undef_exception(regs, hsr); return; @@ -585,7 +586,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union= hsr hsr) "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->= pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); inject_undef_exception(regs, hsr); return; @@ -627,7 +628,7 @@ void do_cp14_64(struct cpu_user_regs *regs, const union= hsr hsr) "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", cp64.read ? "mrrc" : "mcrr", cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#"PRIregister"\n", hsr.bits & HSR_CP64_REGS_MASK); inject_undef_exception(regs, hsr); } @@ -658,7 +659,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const unio= n hsr hsr) "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", cp64.read ? "mrrc" : "mcrr", cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#"PRIregister"= \n", hsr.bits & HSR_CP64_REGS_MASK); =20 inject_undef_exception(regs, hsr); @@ -692,7 +693,7 @@ void do_cp10(struct cpu_user_regs *regs, const union hs= r hsr) "%s p10, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); inject_undef_exception(regs, hsr); return; diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/ar= m64/processor.h index 81dfc5e615..0e86079cbb 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -63,18 +63,19 @@ struct cpu_user_regs =20 /* Return address and mode */ __DECL_REG(pc, pc32); /* ELR_EL2 */ - uint32_t cpsr; /* SPSR_EL2 */ - uint32_t hsr; /* ESR_EL2 */ + uint64_t cpsr; /* SPSR_EL2 */ + uint64_t hsr; /* ESR_EL2 */ + + /* Offset of spsr_el1 must be a multiple of 8 */ + uint64_t pad0; =20 /* Outer guest frame only from here on... */ =20 union { - uint32_t spsr_el1; /* AArch64 */ + uint64_t spsr_el1; /* AArch64 */ uint32_t spsr_svc; /* AArch32 */ }; =20 - uint32_t pad1; /* Doubleword-align the user half of the frame */ - /* AArch32 guests only */ uint32_t spsr_fiq, spsr_irq, spsr_und, spsr_abt; =20 diff --git a/xen/include/asm-arm/hsr.h b/xen/include/asm-arm/hsr.h index 29d4531f40..fb4a3b1274 100644 --- a/xen/include/asm-arm/hsr.h +++ b/xen/include/asm-arm/hsr.h @@ -16,11 +16,12 @@ enum dabt_size { }; =20 union hsr { - uint32_t bits; + register_t bits; struct { unsigned long iss:25; /* Instruction Specific Syndrome */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; }; =20 /* Common to all conditional exception classes (0x0N, except 0x00). */ @@ -30,6 +31,7 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } cond; =20 struct hsr_wfi_wfe { @@ -39,6 +41,7 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } wfi_wfe; =20 /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */ @@ -53,6 +56,7 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */ =20 struct hsr_cp64 { @@ -66,6 +70,7 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ =20 struct hsr_cp { @@ -77,6 +82,7 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } cp; /* HSR_EC_CP */ =20 /* @@ -94,6 +100,7 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } smc32; /* HSR_EC_SMC32 */ =20 #ifdef CONFIG_ARM_64 @@ -108,6 +115,7 @@ union hsr { unsigned long res0:3; unsigned long len:1; /* Instruction length */ unsigned long ec:6; + unsigned long _res0:32; } sysreg; /* HSR_EC_SYSREG */ #endif =20 @@ -121,6 +129,7 @@ union hsr { unsigned long res2:14; unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } iabt; /* HSR_EC_INSTR_ABORT_* */ =20 struct hsr_dabt { @@ -143,6 +152,7 @@ union hsr { unsigned long valid:1; /* Syndrome Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } dabt; /* HSR_EC_DATA_ABORT_* */ =20 /* Contain the common bits between DABT and IABT */ @@ -156,6 +166,7 @@ union hsr { unsigned long pad3:14; /* Not common */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } xabt; =20 #ifdef CONFIG_ARM_64 @@ -164,6 +175,7 @@ union hsr { unsigned long res0:9; unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } brk; #endif }; diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 713fd65317..c49bce2983 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -267,10 +267,10 @@ struct vcpu_guest_core_regs =20 /* Return address and mode */ __DECL_REG(pc64, pc32); /* ELR_EL2 */ - uint32_t cpsr; /* SPSR_EL2 */ + register_t cpsr; /* SPSR_EL2 */ =20 union { - uint32_t spsr_el1; /* AArch64 */ + uint64_t spsr_el1; /* AArch64 */ uint32_t spsr_svc; /* AArch32 */ }; =20 diff --git a/xen/include/public/vm_event.h b/xen/include/public/vm_event.h index 36135ba4f1..ad3d141fe8 100644 --- a/xen/include/public/vm_event.h +++ b/xen/include/public/vm_event.h @@ -266,8 +266,12 @@ struct vm_event_regs_arm { uint64_t ttbr1; uint64_t ttbcr; uint64_t pc; +#ifdef CONFIG_ARM_32 uint32_t cpsr; uint32_t _pad; +#else + uint64_t cpsr; +#endif }; =20 /* --=20 2.29.0