From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1618902566; cv=none; d=zohomail.com; s=zohoarc; b=ZBLCY+dalsNVSGCRCQIiG3za+WGs6LD6/yxlHJckN6dk6g8DomQhq8LbmAgtHzp59hXpLZftegoUgSMKws5hcWEQ+ZF91ailchGvFcxRz8afG9xsKsmqHHUgWOEE2JU45RHzrdsd+WZwIiWdm09epxoY+i5JlQ5UrVgrj5EiDeE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618902566; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Wv9lK9jlVPFLeG3ZvCVPEzD5A8xdbOOdqKAyBSvzbKc=; b=eQnX4nRcZ01ASlT8dneKYiAw35hXRU7DkSomrPOm9QX5a0YOs9bQRjHGRWbcPS4gcE58StdexliYyEI9AauwkKIh0h3FC7B3goRRjgjvxP844I/N/QNx9/lJJZ4Cgg3LX5+uFCLhT6zFZwU9Ubuy5sIkzKfs8txWrYX5hbYeQJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1618902566459275.03205711506746; Tue, 20 Apr 2021 00:09:26 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.113306.215882 (Exim 4.92) (envelope-from ) id 1lYkVR-0006Jq-SI; Tue, 20 Apr 2021 07:09:09 +0000 Received: by outflank-mailman (output) from mailman id 113306.215882; Tue, 20 Apr 2021 07:09:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVR-0006Jj-P4; Tue, 20 Apr 2021 07:09:09 +0000 Received: by outflank-mailman (input) for mailman id 113306; Tue, 20 Apr 2021 07:09:08 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVQ-0006JZ-O2 for xen-devel@lists.xenproject.org; Tue, 20 Apr 2021 07:09:08 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id ddd762a6-cff2-4cb9-bc60-b9d5982ce356; Tue, 20 Apr 2021 07:09:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6AEB21474; Tue, 20 Apr 2021 00:09:06 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 512883F85F; Tue, 20 Apr 2021 00:09:05 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ddd762a6-cff2-4cb9-bc60-b9d5982ce356 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 1/9] arm64/vfp: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:45 +0200 Message-Id: <20210420070853.8918-2-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of FPCR, FPSR, FPEXC32_EL2 to register_t. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/arm64/vfp.c | 12 ++++++------ xen/include/asm-arm/arm64/vfp.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c index 999a0d58a5..47885e76ba 100644 --- a/xen/arch/arm/arm64/vfp.c +++ b/xen/arch/arm/arm64/vfp.c @@ -26,10 +26,10 @@ void vfp_save_state(struct vcpu *v) "stp q30, q31, [%1, #16 * 30]\n\t" : "=3DQ" (*v->arch.vfp.fpregs) : "r" (v->arch.vfp.fpregs)= ); =20 - v->arch.vfp.fpsr =3D READ_SYSREG32(FPSR); - v->arch.vfp.fpcr =3D READ_SYSREG32(FPCR); + v->arch.vfp.fpsr =3D READ_SYSREG(FPSR); + v->arch.vfp.fpcr =3D READ_SYSREG(FPCR); if ( is_32bit_domain(v->domain) ) - v->arch.vfp.fpexc32_el2 =3D READ_SYSREG32(FPEXC32_EL2); + v->arch.vfp.fpexc32_el2 =3D READ_SYSREG(FPEXC32_EL2); } =20 void vfp_restore_state(struct vcpu *v) @@ -55,8 +55,8 @@ void vfp_restore_state(struct vcpu *v) "ldp q30, q31, [%1, #16 * 30]\n\t" : : "Q" (*v->arch.vfp.fpregs), "r" (v->arch.vfp.fpregs)); =20 - WRITE_SYSREG32(v->arch.vfp.fpsr, FPSR); - WRITE_SYSREG32(v->arch.vfp.fpcr, FPCR); + WRITE_SYSREG(v->arch.vfp.fpsr, FPSR); + WRITE_SYSREG(v->arch.vfp.fpcr, FPCR); if ( is_32bit_domain(v->domain) ) - WRITE_SYSREG32(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); + WRITE_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); } diff --git a/xen/include/asm-arm/arm64/vfp.h b/xen/include/asm-arm/arm64/vf= p.h index 6ab5d36c6c..e6e8c363bc 100644 --- a/xen/include/asm-arm/arm64/vfp.h +++ b/xen/include/asm-arm/arm64/vfp.h @@ -7,9 +7,9 @@ struct vfp_state { uint64_t fpregs[64] __vfp_aligned; - uint32_t fpcr; - uint32_t fpexc32_el2; - uint32_t fpsr; + register_t fpcr; + register_t fpexc32_el2; + register_t fpsr; }; =20 #endif /* _ARM_ARM64_VFP_H */ --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Tue, 20 Apr 2021 07:09:13 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id aa01ec39-8aab-4e59-b44c-5e2fe6ec18a6; Tue, 20 Apr 2021 07:09:08 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA30814BF; Tue, 20 Apr 2021 00:09:07 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B348E3F85F; Tue, 20 Apr 2021 00:09:06 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: aa01ec39-8aab-4e59-b44c-5e2fe6ec18a6 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 2/9] arm/domain: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:46 +0200 Message-Id: <20210420070853.8918-3-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of registers: actlr, cntkctl to register_t. Signed-off-by: Michal Orzel --- xen/arch/arm/domain.c | 20 ++++++++++---------- xen/include/asm-arm/domain.h | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index bdd3d3e5b5..c021a03c61 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -113,13 +113,13 @@ static void ctxt_switch_from(struct vcpu *p) p->arch.tpidr_el1 =3D READ_SYSREG(TPIDR_EL1); =20 /* Arch timer */ - p->arch.cntkctl =3D READ_SYSREG32(CNTKCTL_EL1); + p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1); virt_timer_save(p); =20 if ( is_32bit_domain(p->domain) && cpu_has_thumbee ) { - p->arch.teecr =3D READ_SYSREG32(TEECR32_EL1); - p->arch.teehbr =3D READ_SYSREG32(TEEHBR32_EL1); + p->arch.teecr =3D READ_SYSREG(TEECR32_EL1); + p->arch.teehbr =3D READ_SYSREG(TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -175,7 +175,7 @@ static void ctxt_switch_from(struct vcpu *p) =20 static void ctxt_switch_to(struct vcpu *n) { - uint32_t vpidr; + register_t vpidr; =20 /* When the idle VCPU is running, Xen will always stay in hypervisor * mode. Therefore we don't need to restore the context of an idle VCP= U. @@ -183,8 +183,8 @@ static void ctxt_switch_to(struct vcpu *n) if ( is_idle_vcpu(n) ) return; =20 - vpidr =3D READ_SYSREG32(MIDR_EL1); - WRITE_SYSREG32(vpidr, VPIDR_EL2); + vpidr =3D READ_SYSREG(MIDR_EL1); + WRITE_SYSREG(vpidr, VPIDR_EL2); WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); =20 /* VGIC */ @@ -257,8 +257,8 @@ static void ctxt_switch_to(struct vcpu *n) =20 if ( is_32bit_domain(n->domain) && cpu_has_thumbee ) { - WRITE_SYSREG32(n->arch.teecr, TEECR32_EL1); - WRITE_SYSREG32(n->arch.teehbr, TEEHBR32_EL1); + WRITE_SYSREG(n->arch.teecr, TEECR32_EL1); + WRITE_SYSREG(n->arch.teehbr, TEEHBR32_EL1); } =20 #ifdef CONFIG_ARM_32 @@ -274,7 +274,7 @@ static void ctxt_switch_to(struct vcpu *n) =20 /* This is could trigger an hardware interrupt from the virtual * timer. The interrupt needs to be injected into the guest. */ - WRITE_SYSREG32(n->arch.cntkctl, CNTKCTL_EL1); + WRITE_SYSREG(n->arch.cntkctl, CNTKCTL_EL1); virt_timer_restore(n); } =20 @@ -330,7 +330,7 @@ static void schedule_tail(struct vcpu *prev) =20 static void continue_new_vcpu(struct vcpu *prev) { - current->arch.actlr =3D READ_SYSREG32(ACTLR_EL1); + current->arch.actlr =3D READ_SYSREG(ACTLR_EL1); processor_vcpu_initialise(current); =20 schedule_tail(prev); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 0a74df9931..2d4f38c669 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -156,7 +156,7 @@ struct arch_vcpu =20 /* Control Registers */ register_t sctlr; - uint32_t actlr; + register_t actlr; uint32_t cpacr; =20 uint32_t contextidr; @@ -190,7 +190,7 @@ struct arch_vcpu struct vgic_cpu vgic; =20 /* Timer registers */ - uint32_t cntkctl; + register_t cntkctl; =20 struct vtimer phys_timer; struct vtimer virt_timer; --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tue, 20 Apr 2021 07:09:18 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 96ea6986-5d1d-4ec3-a367-d26f9eb199db; Tue, 20 Apr 2021 07:09:09 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5695C1435; Tue, 20 Apr 2021 00:09:09 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1D0B13F85F; Tue, 20 Apr 2021 00:09:07 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 96ea6986-5d1d-4ec3-a367-d26f9eb199db From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 3/9] arm/gic: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:47 +0200 Message-Id: <20210420070853.8918-4-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify types of following members of struct gic_v3 to register_t: -hcr(not used at all in Xen) -vmcr -sre_el1 -apr0 -apr1 Signed-off-by: Michal Orzel --- xen/arch/arm/gic-v3-lpi.c | 2 +- xen/arch/arm/gic-v3.c | 96 ++++++++++++++++++++------------------- xen/include/asm-arm/gic.h | 6 +-- 3 files changed, 54 insertions(+), 50 deletions(-) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 869bc97fa1..e1594dd20e 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -178,7 +178,7 @@ void gicv3_do_LPI(unsigned int lpi) irq_enter(); =20 /* EOI the LPI already. */ - WRITE_SYSREG32(lpi, ICC_EOIR1_EL1); + WRITE_SYSREG(lpi, ICC_EOIR1_EL1); =20 /* Find out if a guest mapped something to this physical LPI. */ hlpip =3D gic_get_host_lpi(lpi); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index ac28013c19..0634013a67 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -246,12 +246,12 @@ static void gicv3_ich_write_lr(int lr, uint64_t val) */ static void gicv3_enable_sre(void) { - uint32_t val; + register_t val; =20 - val =3D READ_SYSREG32(ICC_SRE_EL2); + val =3D READ_SYSREG(ICC_SRE_EL2); val |=3D GICC_SRE_EL2_SRE; =20 - WRITE_SYSREG32(val, ICC_SRE_EL2); + WRITE_SYSREG(val, ICC_SRE_EL2); isb(); } =20 @@ -315,16 +315,16 @@ static void restore_aprn_regs(const union gic_state_d= ata *d) switch ( gicv3.nr_priorities ) { case 7: - WRITE_SYSREG32(d->v3.apr0[2], ICH_AP0R2_EL2); - WRITE_SYSREG32(d->v3.apr1[2], ICH_AP1R2_EL2); + WRITE_SYSREG(d->v3.apr0[2], ICH_AP0R2_EL2); + WRITE_SYSREG(d->v3.apr1[2], ICH_AP1R2_EL2); /* Fall through */ case 6: - WRITE_SYSREG32(d->v3.apr0[1], ICH_AP0R1_EL2); - WRITE_SYSREG32(d->v3.apr1[1], ICH_AP1R1_EL2); + WRITE_SYSREG(d->v3.apr0[1], ICH_AP0R1_EL2); + WRITE_SYSREG(d->v3.apr1[1], ICH_AP1R1_EL2); /* Fall through */ case 5: - WRITE_SYSREG32(d->v3.apr0[0], ICH_AP0R0_EL2); - WRITE_SYSREG32(d->v3.apr1[0], ICH_AP1R0_EL2); + WRITE_SYSREG(d->v3.apr0[0], ICH_AP0R0_EL2); + WRITE_SYSREG(d->v3.apr1[0], ICH_AP1R0_EL2); break; default: BUG(); @@ -338,16 +338,16 @@ static void save_aprn_regs(union gic_state_data *d) switch ( gicv3.nr_priorities ) { case 7: - d->v3.apr0[2] =3D READ_SYSREG32(ICH_AP0R2_EL2); - d->v3.apr1[2] =3D READ_SYSREG32(ICH_AP1R2_EL2); + d->v3.apr0[2] =3D READ_SYSREG(ICH_AP0R2_EL2); + d->v3.apr1[2] =3D READ_SYSREG(ICH_AP1R2_EL2); /* Fall through */ case 6: - d->v3.apr0[1] =3D READ_SYSREG32(ICH_AP0R1_EL2); - d->v3.apr1[1] =3D READ_SYSREG32(ICH_AP1R1_EL2); + d->v3.apr0[1] =3D READ_SYSREG(ICH_AP0R1_EL2); + d->v3.apr1[1] =3D READ_SYSREG(ICH_AP1R1_EL2); /* Fall through */ case 5: - d->v3.apr0[0] =3D READ_SYSREG32(ICH_AP0R0_EL2); - d->v3.apr1[0] =3D READ_SYSREG32(ICH_AP1R0_EL2); + d->v3.apr0[0] =3D READ_SYSREG(ICH_AP0R0_EL2); + d->v3.apr1[0] =3D READ_SYSREG(ICH_AP1R0_EL2); break; default: BUG(); @@ -371,15 +371,15 @@ static void gicv3_save_state(struct vcpu *v) dsb(sy); gicv3_save_lrs(v); save_aprn_regs(&v->arch.gic); - v->arch.gic.v3.vmcr =3D READ_SYSREG32(ICH_VMCR_EL2); - v->arch.gic.v3.sre_el1 =3D READ_SYSREG32(ICC_SRE_EL1); + v->arch.gic.v3.vmcr =3D READ_SYSREG(ICH_VMCR_EL2); + v->arch.gic.v3.sre_el1 =3D READ_SYSREG(ICC_SRE_EL1); } =20 static void gicv3_restore_state(const struct vcpu *v) { - uint32_t val; + register_t val; =20 - val =3D READ_SYSREG32(ICC_SRE_EL2); + val =3D READ_SYSREG(ICC_SRE_EL2); /* * Don't give access to system registers when the guest is using * GICv2 @@ -388,7 +388,7 @@ static void gicv3_restore_state(const struct vcpu *v) val &=3D ~GICC_SRE_EL2_ENEL1; else val |=3D GICC_SRE_EL2_ENEL1; - WRITE_SYSREG32(val, ICC_SRE_EL2); + WRITE_SYSREG(val, ICC_SRE_EL2); =20 /* * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a Group0 @@ -398,9 +398,9 @@ static void gicv3_restore_state(const struct vcpu *v) * want before starting to mess with the rest of the GIC, and * VMCR_EL1 in particular. */ - WRITE_SYSREG32(v->arch.gic.v3.sre_el1, ICC_SRE_EL1); + WRITE_SYSREG(v->arch.gic.v3.sre_el1, ICC_SRE_EL1); isb(); - WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); + WRITE_SYSREG(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); restore_aprn_regs(&v->arch.gic); gicv3_restore_lrs(v); =20 @@ -468,24 +468,25 @@ static void gicv3_mask_irq(struct irq_desc *irqd) static void gicv3_eoi_irq(struct irq_desc *irqd) { /* Lower the priority */ - WRITE_SYSREG32(irqd->irq, ICC_EOIR1_EL1); + WRITE_SYSREG(irqd->irq, ICC_EOIR1_EL1); isb(); } =20 static void gicv3_dir_irq(struct irq_desc *irqd) { /* Deactivate */ - WRITE_SYSREG32(irqd->irq, ICC_DIR_EL1); + WRITE_SYSREG(irqd->irq, ICC_DIR_EL1); isb(); } =20 static unsigned int gicv3_read_irq(void) { - unsigned int irq =3D READ_SYSREG32(ICC_IAR1_EL1); + register_t irq =3D READ_SYSREG(ICC_IAR1_EL1); =20 dsb(sy); =20 - return irq; + /* Number of IRQs do not exceed 32bit. */ + return (unsigned int)irq; } =20 /* @@ -857,16 +858,16 @@ static int gicv3_cpu_init(void) gicv3_enable_sre(); =20 /* No priority grouping */ - WRITE_SYSREG32(0, ICC_BPR1_EL1); + WRITE_SYSREG(0, ICC_BPR1_EL1); =20 /* Set priority mask register */ - WRITE_SYSREG32(DEFAULT_PMR_VALUE, ICC_PMR_EL1); + WRITE_SYSREG(DEFAULT_PMR_VALUE, ICC_PMR_EL1); =20 /* EOI drops priority, DIR deactivates the interrupt (mode 1) */ - WRITE_SYSREG32(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1); + WRITE_SYSREG(GICC_CTLR_EL1_EOImode_drop, ICC_CTLR_EL1); =20 /* Enable Group1 interrupts */ - WRITE_SYSREG32(1, ICC_IGRPEN1_EL1); + WRITE_SYSREG(1, ICC_IGRPEN1_EL1); =20 /* Sync at once at the end of cpu interface configuration */ isb(); @@ -876,15 +877,15 @@ static int gicv3_cpu_init(void) =20 static void gicv3_cpu_disable(void) { - WRITE_SYSREG32(0, ICC_CTLR_EL1); + WRITE_SYSREG(0, ICC_CTLR_EL1); isb(); } =20 static void gicv3_hyp_init(void) { - uint32_t vtr; + register_t vtr; =20 - vtr =3D READ_SYSREG32(ICH_VTR_EL2); + vtr =3D READ_SYSREG(ICH_VTR_EL2); gicv3_info.nr_lrs =3D (vtr & ICH_VTR_NRLRGS) + 1; gicv3.nr_priorities =3D ((vtr >> ICH_VTR_PRIBITS_SHIFT) & ICH_VTR_PRIBITS_MASK) + 1; @@ -892,8 +893,8 @@ static void gicv3_hyp_init(void) if ( !((gicv3.nr_priorities > 4) && (gicv3.nr_priorities < 8)) ) panic("GICv3: Invalid number of priority bits\n"); =20 - WRITE_SYSREG32(ICH_VMCR_EOI | ICH_VMCR_VENG1, ICH_VMCR_EL2); - WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2); + WRITE_SYSREG(ICH_VMCR_EOI | ICH_VMCR_VENG1, ICH_VMCR_EL2); + WRITE_SYSREG(GICH_HCR_EN, ICH_HCR_EL2); } =20 /* Set up the per-CPU parts of the GIC for a secondary CPU */ @@ -917,11 +918,11 @@ out: =20 static void gicv3_hyp_disable(void) { - uint32_t hcr; + register_t hcr; =20 - hcr =3D READ_SYSREG32(ICH_HCR_EL2); + hcr =3D READ_SYSREG(ICH_HCR_EL2); hcr &=3D ~GICH_HCR_EN; - WRITE_SYSREG32(hcr, ICH_HCR_EL2); + WRITE_SYSREG(hcr, ICH_HCR_EL2); isb(); } =20 @@ -1140,39 +1141,42 @@ static void gicv3_write_lr(int lr_reg, const struct= gic_lr *lr) =20 static void gicv3_hcr_status(uint32_t flag, bool status) { - uint32_t hcr; + register_t hcr; =20 - hcr =3D READ_SYSREG32(ICH_HCR_EL2); + hcr =3D READ_SYSREG(ICH_HCR_EL2); if ( status ) - WRITE_SYSREG32(hcr | flag, ICH_HCR_EL2); + WRITE_SYSREG(hcr | flag, ICH_HCR_EL2); else - WRITE_SYSREG32(hcr & (~flag), ICH_HCR_EL2); + WRITE_SYSREG(hcr & (~flag), ICH_HCR_EL2); isb(); } =20 static unsigned int gicv3_read_vmcr_priority(void) { - return ((READ_SYSREG32(ICH_VMCR_EL2) >> ICH_VMCR_PRIORITY_SHIFT) & + return ((READ_SYSREG(ICH_VMCR_EL2) >> ICH_VMCR_PRIORITY_SHIFT) & ICH_VMCR_PRIORITY_MASK); } =20 /* Only support reading GRP1 APRn registers */ static unsigned int gicv3_read_apr(int apr_reg) { + register_t apr; switch ( apr_reg ) { case 0: ASSERT(gicv3.nr_priorities > 4 && gicv3.nr_priorities < 8); - return READ_SYSREG32(ICH_AP1R0_EL2); + apr =3D READ_SYSREG(ICH_AP1R0_EL2); case 1: ASSERT(gicv3.nr_priorities > 5 && gicv3.nr_priorities < 8); - return READ_SYSREG32(ICH_AP1R1_EL2); + apr =3D READ_SYSREG(ICH_AP1R1_EL2); case 2: ASSERT(gicv3.nr_priorities > 6 && gicv3.nr_priorities < 8); - return READ_SYSREG32(ICH_AP1R2_EL2); + apr =3D READ_SYSREG(ICH_AP1R2_EL2); default: BUG(); } + /* Number of priority levels do not exceed 32bit */ + return (unsigned int)apr; } =20 static bool gicv3_read_pending_state(struct irq_desc *irqd) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index ad0f7452d0..d750d070b4 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -171,9 +171,9 @@ * GICv3 registers that needs to be saved/restored */ struct gic_v3 { - uint32_t hcr, vmcr, sre_el1; - uint32_t apr0[4]; - uint32_t apr1[4]; + register_t hcr, vmcr, sre_el1; + register_t apr0[4]; + register_t apr1[4]; uint64_t lr[16]; }; #endif --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Tue, 20 Apr 2021 07:09:23 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 8d41fb0d-5c6c-4ba9-9ceb-8412447acf09; Tue, 20 Apr 2021 07:09:11 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B40481474; Tue, 20 Apr 2021 00:09:10 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9EC213F85F; Tue, 20 Apr 2021 00:09:09 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8d41fb0d-5c6c-4ba9-9ceb-8412447acf09 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 4/9] arm/p2m: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:48 +0200 Message-Id: <20210420070853.8918-5-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of vtcr to register_t. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/arch/arm/p2m.c | 8 ++++---- xen/arch/arm/traps.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index ac50312620..d414c4feb9 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -1973,11 +1973,11 @@ void __init p2m_restrict_ipa_bits(unsigned int ipa_= bits) } =20 /* VTCR value to be configured by all CPUs. Set only once by the boot CPU = */ -static uint32_t __read_mostly vtcr; +static register_t __read_mostly vtcr; =20 static void setup_virt_paging_one(void *data) { - WRITE_SYSREG32(vtcr, VTCR_EL2); + WRITE_SYSREG(vtcr, VTCR_EL2); =20 /* * ARM64_WORKAROUND_AT_SPECULATE: We want to keep the TLBs free from @@ -2000,7 +2000,7 @@ static void setup_virt_paging_one(void *data) void __init setup_virt_paging(void) { /* Setup Stage 2 address translation */ - unsigned long val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0= _WBWA; + register_t val =3D VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WB= WA; =20 #ifdef CONFIG_ARM_32 if ( p2m_ipa_bits < 40 ) @@ -2089,7 +2089,7 @@ void __init setup_virt_paging(void) pa_range_info[pa_range].pabits, ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); #endif - printk("P2M: %d levels with order-%d root, VTCR 0x%lx\n", + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); =20 p2m_vmid_allocator_init(); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ccc0827107..c7acdb2087 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -911,7 +911,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, show_registers_32(regs, ctxt, guest_mode, v); #endif } - printk(" VTCR_EL2: %08"PRIx32"\n", READ_SYSREG32(VTCR_EL2)); + printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); printk("\n"); =20 --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; 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Tue, 20 Apr 2021 00:09:12 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 05F603F85F; Tue, 20 Apr 2021 00:09:10 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c0dce763-5849-4b01-a9c2-2b35e0483262 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 5/9] arm/mm: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:49 +0200 Message-Id: <20210420070853.8918-6-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify SCTLR_EL2 accesses to use READ/WRITE_SYSREG. Signed-off-by: Michal Orzel --- xen/arch/arm/mm.c | 2 +- xen/arch/arm/traps.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 59f8a3f15f..0e07335291 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -613,7 +613,7 @@ void __init remove_early_mappings(void) */ static void xen_pt_enforce_wnx(void) { - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_Axx_ELx_WXN, SCTLR_EL2= ); + WRITE_SYSREG(READ_SYSREG(SCTLR_EL2) | SCTLR_Axx_ELx_WXN, SCTLR_EL2); /* * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized * before flushing the TLBs. diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index c7acdb2087..e7384381cc 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -915,7 +915,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); printk("\n"); =20 - printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2)); + printk(" SCTLR_EL2: %"PRIregister"\n", READ_SYSREG(SCTLR_EL2)); printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1618902586; cv=none; d=zohomail.com; s=zohoarc; b=XSKz5OJMeE2vLzfLYAl/RLxSYUYizIiuR9eDzGxCUGhx3L9e5ph/UNw2u/vRzQfjVa9C10aFydUqG8fUr+Q34HEhrfv6pXatd0zVl8pyo2QBRtB6AaZBL3VOiyY6ddirXKRUfXDXh6qTCbqXUUif1WMQcbl9M1W9a+EtShZ+zzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618902586; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7lrEReXL8VlCcqk+HxaVIHEMU8jCwwwV1oGSe8METBc=; b=lWlRVASLfpRPq3WoFBKRBeisK4N04Q2g1OO9EEODYOlu9XFtmSdZT51fKdJ+UdLl/nP7RdyCZk6OGaqJXU3sXSpExh47j/YLYX9eVQ2Jr55d5lllsBoNWc6YY1/7Xbd0n03suSE4WHdSA48a2kwlqHY3WBEr4i8Q0W3ALaBjXTA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1618902586630578.3652940321889; Tue, 20 Apr 2021 00:09:46 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.113318.215978 (Exim 4.92) (envelope-from ) id 1lYkVr-0006rs-78; Tue, 20 Apr 2021 07:09:35 +0000 Received: by outflank-mailman (output) from mailman id 113318.215978; Tue, 20 Apr 2021 07:09:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVr-0006rc-2e; Tue, 20 Apr 2021 07:09:35 +0000 Received: by outflank-mailman (input) for mailman id 113318; Tue, 20 Apr 2021 07:09:33 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVp-0006Ja-OD for xen-devel@lists.xenproject.org; Tue, 20 Apr 2021 07:09:33 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 7712d985-1e7d-4a66-9b7f-6dea885bf582; Tue, 20 Apr 2021 07:09:13 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 80A631474; Tue, 20 Apr 2021 00:09:13 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C7C13F85F; Tue, 20 Apr 2021 00:09:12 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7712d985-1e7d-4a66-9b7f-6dea885bf582 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 6/9] arm/page: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:50 +0200 Message-Id: <20210420070853.8918-7-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify accesses to CTR_EL0 to use READ/WRITE_SYSREG. Signed-off-by: Michal Orzel Reviewed-by: Julien Grall --- xen/include/asm-arm/page.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 131507a517..c6f9fb0d4e 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -137,10 +137,10 @@ extern size_t dcache_line_bytes; =20 static inline size_t read_dcache_line_bytes(void) { - uint32_t ctr; + register_t ctr; =20 /* Read CTR */ - ctr =3D READ_SYSREG32(CTR_EL0); + ctr =3D READ_SYSREG(CTR_EL0); =20 /* Bits 16-19 are the log2 number of words in the cacheline. */ return (size_t) (4 << ((ctr >> 16) & 0xf)); --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1618902596; cv=none; d=zohomail.com; s=zohoarc; b=bQwqdBukGOYQwFONskmm0hMCEncPXen9+Fjh5SlPjFTKH6MICind7nWvCu032+PoeDOrs1/elD9isfi8PZFnAo6zX0PZS2do2T1NLtwfwBnJJ14N7rPbjhK7QCai9Ps88vEmQo8Jc+A73WMJug824yno37osx2xHubWYbNE68IM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618902596; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NSOO/awPyOHf86IOB+GPky5IWENsoOLA/efNcCEaOAw=; b=Ar7N/1Aju3KbvAUJom4OIXwRp6OzwpaW9ux7SdCXHX2yEkvAngYCE4E1DSHvrHCEm/wMqWTcQLLn/4lTXv2aUkMJg1AdDHWdEE/dzuxbGmApXByCK7nqbF7DewNEfbbC7PUgwz3Shf7l/kDX5oGVXxJ5OB057w59uMyTk00lpWY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1618902596359510.85674886962533; Tue, 20 Apr 2021 00:09:56 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.113323.215989 (Exim 4.92) (envelope-from ) id 1lYkVw-0006zn-IM; Tue, 20 Apr 2021 07:09:40 +0000 Received: by outflank-mailman (output) from mailman id 113323.215989; Tue, 20 Apr 2021 07:09:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVw-0006ze-Dx; Tue, 20 Apr 2021 07:09:40 +0000 Received: by outflank-mailman (input) for mailman id 113323; Tue, 20 Apr 2021 07:09:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVu-0006Ja-On for xen-devel@lists.xenproject.org; Tue, 20 Apr 2021 07:09:38 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 688e8b74-06fa-4c04-a5ff-56709e86b728; Tue, 20 Apr 2021 07:09:15 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB8291474; Tue, 20 Apr 2021 00:09:14 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C6CD83F85F; Tue, 20 Apr 2021 00:09:13 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 688e8b74-06fa-4c04-a5ff-56709e86b728 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 7/9] arm/time,vtimer: Get rid of READ/WRITE_SYSREG32 Date: Tue, 20 Apr 2021 09:08:51 +0200 Message-Id: <20210420070853.8918-8-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of vtimer structure's member: ctl to register_t. Signed-off-by: Michal Orzel --- xen/arch/arm/time.c | 28 ++++++++++++++-------------- xen/arch/arm/vtimer.c | 10 +++++----- xen/include/asm-arm/domain.h | 2 +- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index b0021c2c69..e6c96eb90c 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -145,7 +145,7 @@ void __init preinit_xen_time(void) preinit_acpi_xen_time(); =20 if ( !cpu_khz ) - cpu_khz =3D READ_SYSREG32(CNTFRQ_EL0) / 1000; + cpu_khz =3D (unsigned long)(READ_SYSREG(CNTFRQ_EL0) / 1000); =20 res =3D platform_init_time(); if ( res ) @@ -205,13 +205,13 @@ int reprogram_timer(s_time_t timeout) =20 if ( timeout =3D=3D 0 ) { - WRITE_SYSREG32(0, CNTHP_CTL_EL2); + WRITE_SYSREG(0, CNTHP_CTL_EL2); return 1; } =20 deadline =3D ns_to_ticks(timeout) + boot_count; WRITE_SYSREG64(deadline, CNTHP_CVAL_EL2); - WRITE_SYSREG32(CNTx_CTL_ENABLE, CNTHP_CTL_EL2); + WRITE_SYSREG(CNTx_CTL_ENABLE, CNTHP_CTL_EL2); isb(); =20 /* No need to check for timers in the past; the Generic Timer fires @@ -223,23 +223,23 @@ int reprogram_timer(s_time_t timeout) static void timer_interrupt(int irq, void *dev_id, struct cpu_user_regs *r= egs) { if ( irq =3D=3D (timer_irq[TIMER_HYP_PPI]) && - READ_SYSREG32(CNTHP_CTL_EL2) & CNTx_CTL_PENDING ) + READ_SYSREG(CNTHP_CTL_EL2) & CNTx_CTL_PENDING ) { perfc_incr(hyp_timer_irqs); /* Signal the generic timer code to do its work */ raise_softirq(TIMER_SOFTIRQ); /* Disable the timer to avoid more interrupts */ - WRITE_SYSREG32(0, CNTHP_CTL_EL2); + WRITE_SYSREG(0, CNTHP_CTL_EL2); } =20 if ( irq =3D=3D (timer_irq[TIMER_PHYS_NONSECURE_PPI]) && - READ_SYSREG32(CNTP_CTL_EL0) & CNTx_CTL_PENDING ) + READ_SYSREG(CNTP_CTL_EL0) & CNTx_CTL_PENDING ) { perfc_incr(phys_timer_irqs); /* Signal the generic timer code to do its work */ raise_softirq(TIMER_SOFTIRQ); /* Disable the timer to avoid more interrupts */ - WRITE_SYSREG32(0, CNTP_CTL_EL0); + WRITE_SYSREG(0, CNTP_CTL_EL0); } } =20 @@ -260,8 +260,8 @@ static void vtimer_interrupt(int irq, void *dev_id, str= uct cpu_user_regs *regs) =20 perfc_incr(virt_timer_irqs); =20 - current->arch.virt_timer.ctl =3D READ_SYSREG32(CNTV_CTL_EL0); - WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_= EL0); + current->arch.virt_timer.ctl =3D READ_SYSREG(CNTV_CTL_EL0); + WRITE_SYSREG(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL= 0); vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq= , true); } =20 @@ -297,9 +297,9 @@ void init_timer_interrupt(void) /* Sensible defaults */ WRITE_SYSREG64(0, CNTVOFF_EL2); /* No VM-specific offset */ /* Do not let the VMs program the physical timer, only read the physic= al counter */ - WRITE_SYSREG32(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2); - WRITE_SYSREG32(0, CNTP_CTL_EL0); /* Physical timer disabled */ - WRITE_SYSREG32(0, CNTHP_CTL_EL2); /* Hypervisor's timer disabled */ + WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2); + WRITE_SYSREG(0, CNTP_CTL_EL0); /* Physical timer disabled */ + WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Hypervisor's timer disabled */ isb(); =20 request_irq(timer_irq[TIMER_HYP_PPI], 0, timer_interrupt, @@ -320,8 +320,8 @@ void init_timer_interrupt(void) */ static void deinit_timer_interrupt(void) { - WRITE_SYSREG32(0, CNTP_CTL_EL0); /* Disable physical timer */ - WRITE_SYSREG32(0, CNTHP_CTL_EL2); /* Disable hypervisor's timer */ + WRITE_SYSREG(0, CNTP_CTL_EL0); /* Disable physical timer */ + WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Disable hypervisor's timer */ isb(); =20 release_irq(timer_irq[TIMER_HYP_PPI], NULL); diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index c2b27915c6..167fc6127a 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -138,8 +138,8 @@ void virt_timer_save(struct vcpu *v) { ASSERT(!is_idle_vcpu(v)); =20 - v->arch.virt_timer.ctl =3D READ_SYSREG32(CNTV_CTL_EL0); - WRITE_SYSREG32(v->arch.virt_timer.ctl & ~CNTx_CTL_ENABLE, CNTV_CTL_EL0= ); + v->arch.virt_timer.ctl =3D READ_SYSREG(CNTV_CTL_EL0); + WRITE_SYSREG(v->arch.virt_timer.ctl & ~CNTx_CTL_ENABLE, CNTV_CTL_EL0); v->arch.virt_timer.cval =3D READ_SYSREG64(CNTV_CVAL_EL0); if ( (v->arch.virt_timer.ctl & CNTx_CTL_ENABLE) && !(v->arch.virt_timer.ctl & CNTx_CTL_MASK)) @@ -159,7 +159,7 @@ void virt_timer_restore(struct vcpu *v) =20 WRITE_SYSREG64(v->domain->arch.virt_timer_base.offset, CNTVOFF_EL2); WRITE_SYSREG64(v->arch.virt_timer.cval, CNTV_CVAL_EL0); - WRITE_SYSREG32(v->arch.virt_timer.ctl, CNTV_CTL_EL0); + WRITE_SYSREG(v->arch.virt_timer.ctl, CNTV_CTL_EL0); } =20 static bool vtimer_cntp_ctl(struct cpu_user_regs *regs, uint32_t *r, bool = read) @@ -347,7 +347,7 @@ bool vtimer_emulate(struct cpu_user_regs *regs, union h= sr hsr) } =20 static void vtimer_update_irq(struct vcpu *v, struct vtimer *vtimer, - uint32_t vtimer_ctl) + register_t vtimer_ctl) { bool level; =20 @@ -389,7 +389,7 @@ void vtimer_update_irqs(struct vcpu *v) * but this requires reworking the arch timer to implement this. */ vtimer_update_irq(v, &v->arch.virt_timer, - READ_SYSREG32(CNTV_CTL_EL0) & ~CNTx_CTL_MASK); + READ_SYSREG(CNTV_CTL_EL0) & ~CNTx_CTL_MASK); =20 /* For the physical timer we rely on our emulated state. */ vtimer_update_irq(v, &v->arch.phys_timer, v->arch.phys_timer.ctl); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 2d4f38c669..c9277b5c6d 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -36,7 +36,7 @@ struct vtimer { struct vcpu *v; int irq; struct timer timer; - uint32_t ctl; + register_t ctl; uint64_t cval; }; =20 --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1618902576; cv=none; d=zohomail.com; s=zohoarc; b=SZkFqrzaB5bxuCAy6ZbSqWRPTZk7rRQjhd/ZzhFaAzpuYQoAT1RuG4mNACFSTdB9mcVNyAl4L0JdOrjRMD7DUwErulgSSL9ZeORGoCI7EFZK2AXtLpSep6Cq6xTNIZ/b9STr2O6vK+TAWjIDstmCb7A8OIwe30E0XHyARQ9FSBc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618902576; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 20 Apr 2021 07:09:19 +0000 Received: by outflank-mailman (input) for mailman id 113309; Tue, 20 Apr 2021 07:09:18 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVa-0006RY-Ef for xen-devel@lists.xenproject.org; Tue, 20 Apr 2021 07:09:18 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 827889b3-273a-4a00-a68b-589de8dfa309; Tue, 20 Apr 2021 07:09:16 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 711D11474; Tue, 20 Apr 2021 00:09:16 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3619B3F85F; Tue, 20 Apr 2021 00:09:15 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 827889b3-273a-4a00-a68b-589de8dfa309 From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 8/9] arm: Change type of hsr to register_t Date: Tue, 20 Apr 2021 09:08:52 +0200 Message-Id: <20210420070853.8918-9-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. Modify type of hsr to register_t. When on AArch64 add 32bit RES0 members to structures inside hsr union. Signed-off-by: Michal Orzel --- xen/arch/arm/arm64/entry.S | 2 +- xen/arch/arm/arm64/traps.c | 2 +- xen/arch/arm/arm64/vsysreg.c | 3 ++- xen/arch/arm/traps.c | 20 +++++++++------- xen/arch/arm/vcpreg.c | 13 +++++----- xen/include/asm-arm/arm32/processor.h | 2 +- xen/include/asm-arm/arm64/processor.h | 5 ++-- xen/include/asm-arm/hsr.h | 34 ++++++++++++++++++++++++++- 8 files changed, 59 insertions(+), 22 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index ab9a65fc14..218b063c97 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -155,7 +155,7 @@ add x21, sp, #UREGS_CPSR mrs x22, spsr_el2 mrs x23, esr_el2 - stp w22, w23, [x21] + stp x22, x23, [x21] =20 .endm =20 diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c index babfc1d884..9113a15c7a 100644 --- a/xen/arch/arm/arm64/traps.c +++ b/xen/arch/arm/arm64/traps.c @@ -36,7 +36,7 @@ void do_bad_mode(struct cpu_user_regs *regs, int reason) union hsr hsr =3D { .bits =3D regs->hsr }; =20 printk("Bad mode in %s handler detected\n", handler[reason]); - printk("ESR=3D0x%08"PRIx32": EC=3D%"PRIx32", IL=3D%"PRIx32", ISS=3D%"= PRIx32"\n", + printk("ESR=3D%#"PRIregister": EC=3D%"PRIx32", IL=3D%"PRIx32", ISS=3D= %"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); =20 local_irq_disable(); diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 41f18612c6..3c10d464e7 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -368,7 +368,8 @@ void do_sysreg(struct cpu_user_regs *regs, sysreg.op2, sysreg.read ? "=3D>" : "<=3D", sysreg.reg, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access" + " %#"PRIregister"\n", hsr.bits & HSR_SYSREG_REGS_MASK); inject_undef_exception(regs, hsr); return; diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index e7384381cc..db15a2c647 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -546,7 +546,7 @@ void inject_undef64_exception(struct cpu_user_regs *reg= s, int instr_len) PSR_IRQ_MASK | PSR_DBG_MASK; regs->pc =3D handler; =20 - WRITE_SYSREG32(esr.bits, ESR_EL1); + WRITE_SYSREG(esr.bits, ESR_EL1); } =20 /* Inject an abort exception into a 64 bit guest */ @@ -580,7 +580,7 @@ static void inject_abt64_exception(struct cpu_user_regs= *regs, regs->pc =3D handler; =20 WRITE_SYSREG(addr, FAR_EL1); - WRITE_SYSREG32(esr.bits, ESR_EL1); + WRITE_SYSREG(esr.bits, ESR_EL1); } =20 static void inject_dabt64_exception(struct cpu_user_regs *regs, @@ -919,7 +919,7 @@ static void _show_registers(const struct cpu_user_regs = *regs, printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); - printk(" ESR_EL2: %08"PRIx32"\n", regs->hsr); + printk(" ESR_EL2: %"PRIregister"\n", regs->hsr); printk(" HPFAR_EL2: %"PRIregister"\n", READ_SYSREG(HPFAR_EL2)); =20 #ifdef CONFIG_ARM_32 @@ -2004,13 +2004,15 @@ static void do_trap_stage2_abort_guest(struct cpu_u= ser_regs *regs, =20 break; default: - gprintk(XENLOG_WARNING, "Unsupported FSC: HSR=3D%#x DFSC=3D%#x\n", + gprintk(XENLOG_WARNING, "Unsupported FSC:" + " HSR=3D%#"PRIregister" DFSC=3D%#x\n", hsr.bits, xabt.fsc); } =20 inject_abt: - gdprintk(XENLOG_DEBUG, "HSR=3D0x%x pc=3D%#"PRIregister" gva=3D%#"PRIva= ddr - " gpa=3D%#"PRIpaddr"\n", hsr.bits, regs->pc, gva, gpa); + gdprintk(XENLOG_DEBUG, "HSR=3D%#"PRIregister" pc=3D%#"PRIregister"" + " gva=3D%#"PRIvaddr" gpa=3D%#"PRIpaddr"\n", + hsr.bits, regs->pc, gva, gpa); if ( is_data ) inject_dabt_exception(regs, gva, hsr.len); else @@ -2204,7 +2206,8 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) =20 default: gprintk(XENLOG_WARNING, - "Unknown Guest Trap. HSR=3D0x%x EC=3D0x%x IL=3D%x Syndrome= =3D0x%"PRIx32"\n", + "Unknown Guest Trap. HSR=3D%#"PRIregister" EC=3D0x%x IL=3D= %x" + " Syndrome=3D0x%"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); inject_undef_exception(regs, hsr); } @@ -2242,7 +2245,8 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs) break; } default: - printk("Hypervisor Trap. HSR=3D0x%x EC=3D0x%x IL=3D%x Syndrome=3D0= x%"PRIx32"\n", + printk("Hypervisor Trap. HSR=3D%#"PRIregister" EC=3D0x%x IL=3D%x" + " Syndrome=3D0x%"PRIx32"\n", hsr.bits, hsr.ec, hsr.len, hsr.iss); do_unexpected_trap("Hypervisor", regs); } diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index 55351fc087..c7f516ee0a 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -385,7 +385,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union= hsr hsr) "%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); inject_undef_exception(regs, hsr); return; @@ -454,7 +454,8 @@ void do_cp15_64(struct cpu_user_regs *regs, const union= hsr hsr) "%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", cp64.read ? "mrrc" : "mcrr", cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access" + " %#"PRIregister"\n", hsr.bits & HSR_CP64_REGS_MASK); inject_undef_exception(regs, hsr); return; @@ -585,7 +586,7 @@ void do_cp14_32(struct cpu_user_regs *regs, const union= hsr hsr) "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->= pc); - gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); inject_undef_exception(regs, hsr); return; @@ -627,7 +628,7 @@ void do_cp14_64(struct cpu_user_regs *regs, const union= hsr hsr) "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", cp64.read ? "mrrc" : "mcrr", cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#"PRIregister"\n", hsr.bits & HSR_CP64_REGS_MASK); inject_undef_exception(regs, hsr); } @@ -658,7 +659,7 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const unio= n hsr hsr) "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", cp64.read ? "mrrc" : "mcrr", cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); - gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 DBG access %#"PRIregister"= \n", hsr.bits & HSR_CP64_REGS_MASK); =20 inject_undef_exception(regs, hsr); @@ -692,7 +693,7 @@ void do_cp10(struct cpu_user_regs *regs, const union hs= r hsr) "%s p10, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", cp32.read ? "mrc" : "mcr", cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->p= c); - gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#x\n", + gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#"PRIregister"= \n", hsr.bits & HSR_CP32_REGS_MASK); inject_undef_exception(regs, hsr); return; diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/ar= m32/processor.h index 4e679f3273..395ce10692 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -37,7 +37,7 @@ struct cpu_user_regs uint32_t pc, pc32; }; uint32_t cpsr; /* Return mode */ - uint32_t hsr; /* Exception Syndrome */ + register_t hsr; /* Exception Syndrome */ =20 /* Outer guest frame only from here on... */ =20 diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/ar= m64/processor.h index 81dfc5e615..40f628d216 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -64,8 +64,9 @@ struct cpu_user_regs /* Return address and mode */ __DECL_REG(pc, pc32); /* ELR_EL2 */ uint32_t cpsr; /* SPSR_EL2 */ - uint32_t hsr; /* ESR_EL2 */ + register_t hsr; /* ESR_EL2 */ =20 + register_t pad1; /* Doubleword-align the user half of the frame */ /* Outer guest frame only from here on... */ =20 union { @@ -73,8 +74,6 @@ struct cpu_user_regs uint32_t spsr_svc; /* AArch32 */ }; =20 - uint32_t pad1; /* Doubleword-align the user half of the frame */ - /* AArch32 guests only */ uint32_t spsr_fiq, spsr_irq, spsr_und, spsr_abt; =20 diff --git a/xen/include/asm-arm/hsr.h b/xen/include/asm-arm/hsr.h index 29d4531f40..7424402c6e 100644 --- a/xen/include/asm-arm/hsr.h +++ b/xen/include/asm-arm/hsr.h @@ -16,11 +16,14 @@ enum dabt_size { }; =20 union hsr { - uint32_t bits; + register_t bits; struct { unsigned long iss:25; /* Instruction Specific Syndrome */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif }; =20 /* Common to all conditional exception classes (0x0N, except 0x00). */ @@ -30,6 +33,9 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } cond; =20 struct hsr_wfi_wfe { @@ -39,6 +45,9 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } wfi_wfe; =20 /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */ @@ -53,6 +62,9 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */ =20 struct hsr_cp64 { @@ -66,6 +78,9 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ =20 struct hsr_cp { @@ -77,6 +92,9 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } cp; /* HSR_EC_CP */ =20 /* @@ -94,6 +112,9 @@ union hsr { unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } smc32; /* HSR_EC_SMC32 */ =20 #ifdef CONFIG_ARM_64 @@ -108,6 +129,7 @@ union hsr { unsigned long res0:3; unsigned long len:1; /* Instruction length */ unsigned long ec:6; + unsigned long _res0:32; } sysreg; /* HSR_EC_SYSREG */ #endif =20 @@ -121,6 +143,9 @@ union hsr { unsigned long res2:14; unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } iabt; /* HSR_EC_INSTR_ABORT_* */ =20 struct hsr_dabt { @@ -143,6 +168,9 @@ union hsr { unsigned long valid:1; /* Syndrome Valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } dabt; /* HSR_EC_DATA_ABORT_* */ =20 /* Contain the common bits between DABT and IABT */ @@ -156,6 +184,9 @@ union hsr { unsigned long pad3:14; /* Not common */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ +#ifdef CONFIG_ARM_64 + unsigned long _res0:32; +#endif } xabt; =20 #ifdef CONFIG_ARM_64 @@ -164,6 +195,7 @@ union hsr { unsigned long res0:9; unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ + unsigned long _res0:32; } brk; #endif }; --=20 2.29.0 From nobody Fri May 3 03:39:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 161890257468448.14134832382729; Tue, 20 Apr 2021 00:09:34 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.113311.215933 (Exim 4.92) (envelope-from ) id 1lYkVc-0006Ue-OU; Tue, 20 Apr 2021 07:09:20 +0000 Received: by outflank-mailman (output) from mailman id 113311.215933; Tue, 20 Apr 2021 07:09:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVc-0006UO-FZ; Tue, 20 Apr 2021 07:09:20 +0000 Received: by outflank-mailman (input) for mailman id 113311; Tue, 20 Apr 2021 07:09:19 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lYkVa-0006RY-VL for xen-devel@lists.xenproject.org; Tue, 20 Apr 2021 07:09:18 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id da5caf71-00df-4133-af6e-706a268879af; Tue, 20 Apr 2021 07:09:18 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF3F01435; Tue, 20 Apr 2021 00:09:17 -0700 (PDT) Received: from e123311-lin.arm.com (unknown [10.57.29.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B9E773F85F; Tue, 20 Apr 2021 00:09:16 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: da5caf71-00df-4133-af6e-706a268879af From: Michal Orzel To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk , bertrand.marquis@arm.com Subject: [PATCH 9/9] xen/arm64: Remove READ/WRITE_SYSREG32 helper macros Date: Tue, 20 Apr 2021 09:08:53 +0200 Message-Id: <20210420070853.8918-10-michal.orzel@arm.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210420070853.8918-1-michal.orzel@arm.com> References: <20210420070853.8918-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AArch64 system registers are 64bit whereas AArch32 ones are 32bit or 64bit. MSR/MRS are expecting 64bit values thus we should get rid of helpers READ/WRITE_SYSREG32 in favour of using READ/WRITE_SYSREG. We should also use register_t type when reading sysregs which can correspond to uint64_t or uint32_t. Even though many AArch64 sysregs have upper 32bit reserved it does not mean that they can't be widen in the future. As there are no other places in the code using READ/WRITE_SYSREG32, remove the helper macros. Signed-off-by: Michal Orzel --- xen/arch/arm/vcpreg.c | 16 ++++++++++++++++ xen/include/asm-arm/arm64/sysregs.h | 5 ----- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index c7f516ee0a..6cb7f3108c 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -48,6 +48,7 @@ */ =20 /* The name is passed from the upper macro to workaround macro expansion. = */ +#ifdef CONFIG_ARM_32 #define TVM_REG(sz, func, reg...) = \ static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) = \ { = \ @@ -61,6 +62,21 @@ static bool func(struct cpu_user_regs *regs, uint##sz##_= t *r, bool read) \ = \ return true; = \ } +#else /* CONFIG_ARM_64 */ +#define TVM_REG(sz, func, reg...) = \ +static bool func(struct cpu_user_regs *regs, uint##sz##_t *r, bool read) = \ +{ = \ + struct vcpu *v =3D current; = \ + bool cache_enabled =3D vcpu_has_cache_enabled(v); = \ + = \ + GUEST_BUG_ON(read); = \ + WRITE_SYSREG(*r, reg); = \ + = \ + p2m_toggle_cache(v, cache_enabled); = \ + = \ + return true; = \ +} +#endif =20 #define TVM_REG32(regname, xreg) TVM_REG(32, vreg_emulate_##regname, xreg) #define TVM_REG64(regname, xreg) TVM_REG(64, vreg_emulate_##regname, xreg) diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm6= 4/sysregs.h index 077fd95fb7..83a1157ac4 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -86,11 +86,6 @@ #endif =20 /* Access to system registers */ - -#define READ_SYSREG32(name) ((uint32_t)READ_SYSREG64(name)) - -#define WRITE_SYSREG32(v, name) WRITE_SYSREG64((uint64_t)v, name) - #define WRITE_SYSREG64(v, name) do { \ uint64_t _r =3D v; \ asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ --=20 2.29.0