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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UwyYue/XhqLfsb2rqRAARfa6x/vmze08A9OfANytI5g=; b=JwGj4kzlXyu9mS9h8m4BqHSxtisGu16lf2P4AQa+4Vf8hZ44XF2NsQ8hqxiQBsUzpgEMm3gysU2QRAbHWgjBCSBlGll+5Rra3XDZXemw0oTyPfEfu1c+4oKrENmK0SmlyGINd7msTyxKl4V6jKKzJjq9B4IGnF/L65bDfx4K3P0= From: Roger Pau Monne To: CC: Roger Pau Monne , Jan Beulich , Andrew Cooper , Wei Liu Subject: [PATCH v2 1/2] x86/amd: split LFENCE dispatch serializing setup logic into helper Date: Thu, 15 Apr 2021 16:47:30 +0200 Message-ID: <20210415144731.3356-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210415144731.3356-1-roger.pau@citrix.com> References: <20210415144731.3356-1-roger.pau@citrix.com> Content-Type: text/plain; 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No functional change intended. Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Andrew Cooper --- Changes since v1: - Fix typo in commit message. --- xen/arch/x86/cpu/amd.c | 62 ++++++++++++++++++++++------------------ xen/arch/x86/cpu/cpu.h | 1 + xen/arch/x86/cpu/hygon.c | 27 +---------------- 3 files changed, 36 insertions(+), 54 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 8bc51bec10d..9c8dcd91eef 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -642,6 +642,38 @@ void early_init_amd(struct cpuinfo_x86 *c) ctxt_switch_levelling(NULL); } =20 +void amd_init_lfence(struct cpuinfo_x86 *c) +{ + uint64_t value; + + /* + * Attempt to set lfence to be Dispatch Serialising. This MSR almost + * certainly isn't virtualised (and Xen at least will leak the real + * value in but silently discard writes), as well as being per-core + * rather than per-thread, so do a full safe read/write/readback cycle + * in the worst case. + */ + if (rdmsr_safe(MSR_AMD64_DE_CFG, value)) + /* Unable to read. Assume the safer default. */ + __clear_bit(X86_FEATURE_LFENCE_DISPATCH, + c->x86_capability); + else if (value & AMD64_DE_CFG_LFENCE_SERIALISE) + /* Already dispatch serialising. */ + __set_bit(X86_FEATURE_LFENCE_DISPATCH, + c->x86_capability); + else if (wrmsr_safe(MSR_AMD64_DE_CFG, + value | AMD64_DE_CFG_LFENCE_SERIALISE) || + rdmsr_safe(MSR_AMD64_DE_CFG, value) || + !(value & AMD64_DE_CFG_LFENCE_SERIALISE)) + /* Attempt to set failed. Assume the safer default. */ + __clear_bit(X86_FEATURE_LFENCE_DISPATCH, + c->x86_capability); + else + /* Successfully enabled! */ + __set_bit(X86_FEATURE_LFENCE_DISPATCH, + c->x86_capability); +} + static void init_amd(struct cpuinfo_x86 *c) { u32 l, h; @@ -686,37 +718,11 @@ static void init_amd(struct cpuinfo_x86 *c) if (c =3D=3D &boot_cpu_data && !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS)) setup_force_cpu_cap(X86_BUG_FPU_PTRS); =20 - /* - * Attempt to set lfence to be Dispatch Serialising. This MSR almost - * certainly isn't virtualised (and Xen at least will leak the real - * value in but silently discard writes), as well as being per-core - * rather than per-thread, so do a full safe read/write/readback cycle - * in the worst case. - */ if (c->x86 =3D=3D 0x0f || c->x86 =3D=3D 0x11) /* Always dispatch serialising on this hardare. */ __set_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability); - else /* Implicily "=3D=3D 0x10 || >=3D 0x12" by being 64bit. */ { - if (rdmsr_safe(MSR_AMD64_DE_CFG, value)) - /* Unable to read. Assume the safer default. */ - __clear_bit(X86_FEATURE_LFENCE_DISPATCH, - c->x86_capability); - else if (value & AMD64_DE_CFG_LFENCE_SERIALISE) - /* Already dispatch serialising. */ - __set_bit(X86_FEATURE_LFENCE_DISPATCH, - c->x86_capability); - else if (wrmsr_safe(MSR_AMD64_DE_CFG, - value | AMD64_DE_CFG_LFENCE_SERIALISE) || - rdmsr_safe(MSR_AMD64_DE_CFG, value) || - !(value & AMD64_DE_CFG_LFENCE_SERIALISE)) - /* Attempt to set failed. Assume the safer default. */ - __clear_bit(X86_FEATURE_LFENCE_DISPATCH, - c->x86_capability); - else - /* Successfully enabled! */ - __set_bit(X86_FEATURE_LFENCE_DISPATCH, - c->x86_capability); - } + else /* Implicily "=3D=3D 0x10 || >=3D 0x12" by being 64bit. */ + amd_init_lfence(c); =20 /* * If the user has explicitly chosen to disable Memory Disambiguation diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h index 1992596d1b2..1ac3b2867a0 100644 --- a/xen/arch/x86/cpu/cpu.h +++ b/xen/arch/x86/cpu/cpu.h @@ -20,3 +20,4 @@ extern bool detect_extended_topology(struct cpuinfo_x86 *= c); =20 void early_init_amd(struct cpuinfo_x86 *c); void amd_log_freq(const struct cpuinfo_x86 *c); +void amd_init_lfence(struct cpuinfo_x86 *c); diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index 46293f1f367..2272e1113f1 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -32,32 +32,7 @@ static void init_hygon(struct cpuinfo_x86 *c) { unsigned long long value; =20 - /* - * Attempt to set lfence to be Dispatch Serialising. This MSR almost - * certainly isn't virtualised (and Xen at least will leak the real - * value in but silently discard writes), as well as being per-core - * rather than per-thread, so do a full safe read/write/readback cycle - * in the worst case. - */ - if (rdmsr_safe(MSR_AMD64_DE_CFG, value)) - /* Unable to read. Assume the safer default. */ - __clear_bit(X86_FEATURE_LFENCE_DISPATCH, - c->x86_capability); - else if (value & AMD64_DE_CFG_LFENCE_SERIALISE) - /* Already dispatch serialising. */ - __set_bit(X86_FEATURE_LFENCE_DISPATCH, - c->x86_capability); - else if (wrmsr_safe(MSR_AMD64_DE_CFG, - value | AMD64_DE_CFG_LFENCE_SERIALISE) || - rdmsr_safe(MSR_AMD64_DE_CFG, value) || - !(value & AMD64_DE_CFG_LFENCE_SERIALISE)) - /* Attempt to set failed. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JOwBr5KtW140gDg1QrHVd6cRRXtjGL3eSjcb7YdoXo4=; b=m1CZ4Wuvv8pZfsX7eraohBhTXUZWpiBmZSCExXc2DeS2KoX7MJN2vvt716pWtUMgQrt2n2upxOQNzmt9X6GE+SHStJUV/iU7rWIJDu838oBlbGf42CslOryr4ZtYzKPJW1W6rf3C4mbqNFAVzGslVXGsebXrz97iCumzS5zM9Oo= From: Roger Pau Monne To: CC: Roger Pau Monne , Ian Jackson , Wei Liu , Anthony PERARD , Jan Beulich , Andrew Cooper Subject: [PATCH v2 2/2] x86/cpuid: support LFENCE always serializing CPUID bit Date: Thu, 15 Apr 2021 16:47:31 +0200 Message-ID: <20210415144731.3356-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210415144731.3356-1-roger.pau@citrix.com> References: <20210415144731.3356-1-roger.pau@citrix.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?B?amdxckhEV3pOUG0wU3UycG4rWWNKRWxEakNEZzBySHA4cm1aQmR6UUlKWGlm?= =?utf-8?B?RERUZUlLQ3U4TVNMQ1UxL3R4T1k4K2xaVjJPbjZ5ZjdZU3dQRHlQVXllenFr?= =?utf-8?B?VDRmR3I2M1JlSXQwdEJzQnFZRmxXZTFDYURjbExUZmlsOFl3ODYraDVpYzdL?= =?utf-8?B?eHlFaGlFQWtPU3dDQlc1c1NnWlY2TElDQUV1MmdJcWIvc0V6cmJnUDdrTTZm?= =?utf-8?B?M0ZUZDhJSFBQNXVvbmJPaTZRRTVRVmZ5Q015U0xQMXowbnRZb0ZIRkdwamNX?= =?utf-8?B?VUtVWWRKZFZGUm9YOUVNNktJaHdPdm10NUhmanU0N3pFTjBYK0RGa3NCUW9a?= =?utf-8?B?dHo3VmNCRUN2d1ZENC83eVJuV3ZKWUZPbHlIS3Fuck1WZ1l1SHN2RTN6cEdE?= =?utf-8?B?VjFRSHpNYmEwZjNXcGJ3dmRqc3BTN2QzY3ZuMUd5WHlBQnBmY3VQOG5WUFdq?= =?utf-8?B?QXJhc3lIbEtiOGZ4YUVHbGNQUitvcFh6NlUvM2RCUENOUXdLQkpQNEYxVGN6?= =?utf-8?B?N2Y4ckVmUEtwS2VmK0dTNWF3dm9RRXVLNWlMVmtTV1BTUEZsYzUwMWY1MTF5?= =?utf-8?B?WjBZblJkUklidkxOVi8wNVhnYW0xR0twT1FQaGtFZmszK1pLKytkTi9SQjBw?= =?utf-8?B?T1hZUU1OYi9QWExBb2E4MVJYR1JxVmZ2UmNxYWM1ckJZeUVSL3NkZjlickhE?= =?utf-8?B?SXZTNWFaSGNEZU0yeGJWQlQ0YXF1bzNsdytlMHZhb01vTllleVlpcnVYZEtv?= =?utf-8?B?S0VJdjVOMXVkbnpCeGhoeC9RK3l0RTRFNmJXcVNVY3B5bC9Gc2N4ZzhTZWpi?= =?utf-8?B?Tng0Q2I1cUdCR0VXWWw5VVhDZUZIdEYxVHd4bDFZcWdrRW9zOUM5bDBwMnJl?= =?utf-8?B?MlVlcjgzRVVsaWI0dU1HSWZHZTl2aWIxblQ3QVUxSU05eDZ3UVYwK3hERDJj?= =?utf-8?B?SDdNVTR4NWRuYzROWE1OWUEzQzJsQmI3ejd3L083dmlhZGliT1g2U1lpY0ZH?= =?utf-8?B?WXZvS0R0WXNlZTllWFVvT2hna3Y3NlVCTVcrU0JwUFBDTmpOc2o0Q215NnUw?= =?utf-8?B?YlJRTGJzZlJBNDBYWUY5a0haK08yU29KMDg1YVQraVd5VzAzMmpkS01Va3c0?= =?utf-8?B?bW9SVTFuMHF5cHR0NTJieUNRRVFmR0VTN1MxM1pVK0RiMEE5UHBSSS80d0Jj?= =?utf-8?B?TzBhLzBwdUYvVHNGVFJDOVk4cURWNDFkc2hNTWYwZFRHTmxVUGZmNFZBai96?= =?utf-8?B?dkhnazIyN1Noc045RjBwamx2RVNWYjJiSlc3NXFMalQwVURtUHhPZ01JN0Vl?= =?utf-8?B?anhOOEh4cmszRlBOUG9pTWozUStCOVYwdXZqbEdJNGN3VXVQcGRoM2VKM1pR?= =?utf-8?B?MFBuU1RXSkw1WGcvSmtxRWRjNTBzQVprdjRJNGJ3WkM4RTJndldKNXUxYTIw?= =?utf-8?B?N2haWFZVbVJleTJyVlp3eVFHU2t5NUI2Y2tkL25BOS9DS29Nbm9wODNuQkJh?= =?utf-8?B?bGhYVHM1MVdld0REaTZEOTNxaVg4SXVseWMvdEFvOFRGNVJUcWRzV1RFSFR6?= =?utf-8?B?OHM0Vm1iS1hTemErNDA5VjFKdFVScWhtOCtHemdoNWJ4TUlMN1FIMndSOExZ?= =?utf-8?B?ay8ra2lBVFpBZjJFdmtWUmpwUk10Tm1pZUI4V2R1YWdOWEpHL2FHRnlRZTNN?= =?utf-8?B?c28vaEtzd3BqdFBST1VXbFVXbTBnTXJvZk4zK3NZZ3hmZUxpSXZ0clpKeUVk?= =?utf-8?B?eUp3SGlXa2lLNkF0dDBjQ0tmTU95cDM2TnNac2NodG9nZy8wcWppUUpxcEN0?= =?utf-8?B?N09vV0JvTFNxa01qODB2dz09?= X-MS-Exchange-CrossTenant-Network-Message-Id: 5316dbc0-40a7-4017-02e3-08d9001d7f8d X-MS-Exchange-CrossTenant-AuthSource: DS7PR03MB5608.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2021 14:48:14.4894 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6iZpcfzhz5IGQSRCN/MXPHX0xucbqDzNUwyOs+uXxiKKb3+mBoM1ifIL92UiDJ2z/qD/74mlt7WZsrx5n9+Cvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR03MB5273 X-OriginatorOrg: citrix.com X-ZohoMail-DKIM: pass (identity @citrix.com) AMD Milan (Zen3) CPUs have an LFENCE Always Serializing CPUID bit in leaf 80000021.eax. Previous AMD versions used to have a user settable bit in DE_CFG MSR to select whether LFENCE was dispatch serializing, which Xen always attempts to set. The forcefully always on setting is due to the addition of SEV-SNP so that a VMM cannot break the confidentiality of a guest. In order to support this new CPUID bit move the LFENCE_DISPATCH synthetic CPUID bit to map the hardware bit (leaving a hole in the synthetic range) and either rely on the bit already being set by the native CPUID output, or attempt to fake it in Xen by modifying the DE_CFG MSR. This requires adding one more entry to the featureset to support leaf 80000021.eax. The bit is exposed to guests by default if the underlying hardware supports leaf 80000021, as a way to signal that LFENCE is always serializing. Hardware that doesn't have the leaf might also get the bit set because Xen has performed the necessary arrangements, but that's not yet exposed to guests. Note that Xen doesn't allow guests to change the DE_CFG value, so once set by Xen LFENCE will always be serializing. Note that the access to DE_CFG by guests is left as-is: reads will unconditionally return LFENCE_SERIALISE bit set, while writes are silently dropped. Suggested-by: Andrew Cooper Signed-off-by: Roger Pau Monn=C3=A9 Reviewed-by: Jan Beulich --- Changes since v1: - Rename to lfence+. - Add feature to libxl_cpuid.c. - Reword commit message. --- Note this doesn't yet expose the bit on hardware that doesn't support leaf 80000021. It's still TBD whether we want to hardcode this support manually, or instead rely on a more general approach like the one suggested by the shrink max CPUID leaf patch from Jan. --- tools/libs/light/libxl_cpuid.c | 2 ++ tools/misc/xen-cpuid.c | 6 ++++ xen/arch/x86/cpu/amd.c | 7 ++++ xen/arch/x86/cpu/common.c | 3 ++ xen/include/asm-x86/cpufeatures.h | 2 +- xen/include/public/arch-x86/cpufeatureset.h | 3 ++ xen/include/xen/lib/x86/cpuid.h | 37 ++++++++++++++++++++- 7 files changed, 58 insertions(+), 2 deletions(-) diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index aee28b0430d..d3ab66b9a71 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -284,6 +284,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *c= puid, const char* str) {"svm_decode", 0x8000000a, NA, CPUID_REG_EDX, 7, 1}, {"svm_pausefilt",0x8000000a, NA, CPUID_REG_EDX, 10, 1}, =20 + {"lfence+", 0x80000021, NA, CPUID_REG_EAX, 2, 1}, + {"maxhvleaf", 0x40000000, NA, CPUID_REG_EAX, 0, 8}, =20 {NULL, 0, NA, CPUID_REG_INV, 0, 0} diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 628e8f5aa25..9a47237f4a8 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -179,6 +179,11 @@ static const char *const str_7a1[32] =3D [ 4] =3D "avx-vnni", [ 5] =3D "avx512-bf16", }; =20 +static const char *const str_e21a[32] =3D +{ + [ 2] =3D "lfence+", +}; + static const struct { const char *name; const char *abbr; @@ -196,6 +201,7 @@ static const struct { { "0x80000008.ebx", "e8b", str_e8b }, { "0x00000007:0.edx", "7d0", str_7d0 }, { "0x00000007:1.eax", "7a1", str_7a1 }, + { "0x80000021.eax", "e21a", str_e21a }, }; =20 #define COL_ALIGN "18" diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 9c8dcd91eef..35f22c24762 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -646,6 +646,13 @@ void amd_init_lfence(struct cpuinfo_x86 *c) { uint64_t value; =20 + /* + * Some hardware has LFENCE dispatch serializing always enabled, + * nothing to do on that case. + */ + if (test_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability)) + return; + /* * Attempt to set lfence to be Dispatch Serialising. This MSR almost * certainly isn't virtualised (and Xen at least will leak the real diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index e5c3caf41d5..0eb364f8a65 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -412,6 +412,9 @@ static void generic_identify(struct cpuinfo_x86 *c) if (c->extended_cpuid_level >=3D 0x80000008) c->x86_capability[cpufeat_word(X86_FEATURE_CLZERO)] =3D cpuid_ebx(0x80000008); + if (c->extended_cpuid_level >=3D 0x80000021) + c->x86_capability[cpufeat_word(X86_FEATURE_LFENCE_DISPATCH)] + =3D cpuid_eax(0x80000021); =20 /* Intel-defined flags: level 0x00000007 */ if ( c->cpuid_level >=3D 0x00000007 ) { diff --git a/xen/include/asm-x86/cpufeatures.h b/xen/include/asm-x86/cpufea= tures.h index d7e42d9bb6a..6c8f432aee4 100644 --- a/xen/include/asm-x86/cpufeatures.h +++ b/xen/include/asm-x86/cpufeatures.h @@ -24,7 +24,7 @@ XEN_CPUFEATURE(APERFMPERF, X86_SYNTH( 8)) /* APERF= MPERF */ XEN_CPUFEATURE(MFENCE_RDTSC, X86_SYNTH( 9)) /* MFENCE synchronizes RD= TSC */ XEN_CPUFEATURE(XEN_SMEP, X86_SYNTH(10)) /* SMEP gets used by Xen = itself */ XEN_CPUFEATURE(XEN_SMAP, X86_SYNTH(11)) /* SMAP gets used by Xen = itself */ -XEN_CPUFEATURE(LFENCE_DISPATCH, X86_SYNTH(12)) /* lfence set as Dispatch= Serialising */ +/* Bit 12 - unused. */ XEN_CPUFEATURE(IND_THUNK_LFENCE, X86_SYNTH(13)) /* Use IND_THUNK_LFENCE */ XEN_CPUFEATURE(IND_THUNK_JMP, X86_SYNTH(14)) /* Use IND_THUNK_JMP */ XEN_CPUFEATURE(SC_BRANCH_HARDEN, X86_SYNTH(15)) /* Conditional Branch Har= dening */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 42bc8d4279d..732990f2cc0 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -278,6 +278,9 @@ XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CT= RL.SSBD available */ XEN_CPUFEATURE(AVX_VNNI, 10*32+ 4) /*A AVX-VNNI Instructions */ XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ =20 +/* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ +XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializin= g */ + #endif /* XEN_CPUFEATURE */ =20 /* Clean up from a default include. Close the enum (for C). */ diff --git a/xen/include/xen/lib/x86/cpuid.h b/xen/include/xen/lib/x86/cpui= d.h index f4ef8a9f2f0..a4d254ea96e 100644 --- a/xen/include/xen/lib/x86/cpuid.h +++ b/xen/include/xen/lib/x86/cpuid.h @@ -15,6 +15,7 @@ #define FEATURESET_e8b 8 /* 0x80000008.ebx */ #define FEATURESET_7d0 9 /* 0x00000007:0.edx */ #define FEATURESET_7a1 10 /* 0x00000007:1.eax */ +#define FEATURESET_e21a 11 /* 0x80000021.eax */ =20 struct cpuid_leaf { @@ -84,7 +85,7 @@ const char *x86_cpuid_vendor_to_str(unsigned int vendor); #define CPUID_GUEST_NR_TOPO (1u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) -#define CPUID_GUEST_NR_EXTD_AMD (0x1cu + 1) +#define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ CPUID_GUEST_NR_EXTD_AMD) =20 @@ -264,6 +265,38 @@ struct cpuid_policy }; uint32_t nc:8, :4, apic_id_size:4, :16; uint32_t /* d */:32; + + uint64_t :64, :64; /* Leaf 0x80000009. */ + uint64_t :64, :64; /* Leaf 0x8000000a - SVM rev and features. = */ + uint64_t :64, :64; /* Leaf 0x8000000b. */ + uint64_t :64, :64; /* Leaf 0x8000000c. */ + uint64_t :64, :64; /* Leaf 0x8000000d. */ + uint64_t :64, :64; /* Leaf 0x8000000e. */ + uint64_t :64, :64; /* Leaf 0x8000000f. */ + uint64_t :64, :64; /* Leaf 0x80000010. */ + uint64_t :64, :64; /* Leaf 0x80000011. */ + uint64_t :64, :64; /* Leaf 0x80000012. */ + uint64_t :64, :64; /* Leaf 0x80000013. */ + uint64_t :64, :64; /* Leaf 0x80000014. */ + uint64_t :64, :64; /* Leaf 0x80000015. */ + uint64_t :64, :64; /* Leaf 0x80000016. */ + uint64_t :64, :64; /* Leaf 0x80000017. */ + uint64_t :64, :64; /* Leaf 0x80000018. */ + uint64_t :64, :64; /* Leaf 0x80000019 - TLB 1GB Identifiers. */ + uint64_t :64, :64; /* Leaf 0x8000001a - Performance related in= fo. */ + uint64_t :64, :64; /* Leaf 0x8000001b - IBS feature informatio= n. */ + uint64_t :64, :64; /* Leaf 0x8000001c. */ + uint64_t :64, :64; /* Leaf 0x8000001d - Cache properties. */ + uint64_t :64, :64; /* Leaf 0x8000001e - Extd APIC/Core/Node ID= s. */ + uint64_t :64, :64; /* Leaf 0x8000001f - AMD Secure Encryption.= */ + uint64_t :64, :64; /* Leaf 0x80000020 - Platform QoS. */ + + /* Leaf 0x80000021 - Extended Feature 2 */ + union { + uint32_t e21a; + struct { DECL_BITFIELD(e21a); }; + }; + uint32_t /* b */:32, /* c */:32, /* d */:32; }; } extd; =20 @@ -293,6 +326,7 @@ static inline void cpuid_policy_to_featureset( fs[FEATURESET_e8b] =3D p->extd.e8b; fs[FEATURESET_7d0] =3D p->feat._7d0; fs[FEATURESET_7a1] =3D p->feat._7a1; + fs[FEATURESET_e21a] =3D p->extd.e21a; } =20 /* Fill in a CPUID policy from a featureset bitmap. */ @@ -310,6 +344,7 @@ static inline void cpuid_featureset_to_policy( p->extd.e8b =3D fs[FEATURESET_e8b]; p->feat._7d0 =3D fs[FEATURESET_7d0]; p->feat._7a1 =3D fs[FEATURESET_7a1]; + p->extd.e21a =3D fs[FEATURESET_e21a]; } =20 static inline uint64_t cpuid_policy_xcr0_max(const struct cpuid_policy *p) --=20 2.30.1