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Smith" , Rich Persaud , Christopher Clark Subject: [PATCH 1/3] x86/smpboot: Re-position the call to tboot_wake_ap() Date: Fri, 15 Jan 2021 23:10:44 +0000 Message-ID: <20210115231046.31785-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210115231046.31785-1-andrew.cooper3@citrix.com> References: <20210115231046.31785-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) So all the moving parts are in one function. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Marek Kasiewicz CC: Norbert Kami=C5=84ski CC: Michal Zygowski CC: Piotr Krol CC: Krystian Hebel CC: Daniel P. Smith CC: Rich Persaud CC: Christopher Clark --- xen/arch/x86/smpboot.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 67e727cebd..9eca452ce1 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -426,6 +426,13 @@ static int wakeup_secondary_cpu(int phys_apicid, unsig= ned long start_eip) int maxlvt, timeout, i; =20 /* + * Some versions of tboot might be able to handle the entire wake sequ= ence + * on our behalf. + */ + if ( tboot_in_measured_env() && tboot_wake_ap(phys_apicid, start_eip) ) + return 0; + + /* * Be paranoid about clearing APIC errors. */ apic_write(APIC_ESR, 0); @@ -570,8 +577,7 @@ static int do_boot_cpu(int apicid, int cpu) set_cpu_state(CPU_STATE_INIT); =20 /* Starting actual IPI sequence... */ - if ( !tboot_in_measured_env() || tboot_wake_ap(apicid, start_eip) ) - boot_error =3D wakeup_secondary_cpu(apicid, start_eip); + boot_error =3D wakeup_secondary_cpu(apicid, start_eip); =20 if ( !boot_error ) { --=20 2.11.0 From nobody Sun May 5 19:19:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1610752302; cv=none; d=zohomail.com; s=zohoarc; b=V3Yy7oevt3uDP5jLRFpZDLvj+maOh9DdJ1c+dGt6Nxkimf9RskpSEy3Jz/BRKfJ6yNjJF67kEFGmYy3Fb7DkkIXe5PB4BKuileAEixqSGBhuPAZZxrSl8ZKtYMNyaOXNQ0NsQ2xTE//d1hSjtwq65IZxhHrHtzzNsafLZAEYmWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610752302; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 15 Jan 2021 23:11:11 +0000 Received: by outflank-mailman (input) for mailman id 68829; Fri, 15 Jan 2021 23:11:10 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1l0YFK-0005vh-Gk for xen-devel@lists.xenproject.org; Fri, 15 Jan 2021 23:11:10 +0000 Received: from esa5.hc3370-68.iphmx.com (unknown [216.71.155.168]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 45cce534-f808-470b-90a9-362a30d291b2; Fri, 15 Jan 2021 23:11:09 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 45cce534-f808-470b-90a9-362a30d291b2 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1610752269; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Smith" , Rich Persaud , Christopher Clark Subject: [PATCH 2/3] x86/smpboot: Allow making an INIT IPI conditional Date: Fri, 15 Jan 2021 23:10:45 +0000 Message-ID: <20210115231046.31785-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210115231046.31785-1-andrew.cooper3@citrix.com> References: <20210115231046.31785-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) A subsequent change is going to introduce SKINIT support, wherein the APs w= ill be already be in the wait-for-SIPI state, and an INIT must not be sent. Introduce a send_INIT boolean, so we can control sending an INIT IPI separately from sending SIPIs. No functional change. Signed-off-by: Andrew Cooper Acked-by: Roger Pau Monn=C3=A9 --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Marek Kasiewicz CC: Norbert Kami=C5=84ski CC: Michal Zygowski CC: Piotr Krol CC: Krystian Hebel CC: Daniel P. Smith CC: Rich Persaud CC: Christopher Clark --- xen/arch/x86/smpboot.c | 78 ++++++++++++++++++++++++++--------------------= ---- 1 file changed, 41 insertions(+), 37 deletions(-) diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 9eca452ce1..195e3681b4 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -424,6 +424,7 @@ static int wakeup_secondary_cpu(int phys_apicid, unsign= ed long start_eip) { unsigned long send_status =3D 0, accept_status =3D 0; int maxlvt, timeout, i; + bool send_INIT =3D true; =20 /* * Some versions of tboot might be able to handle the entire wake sequ= ence @@ -438,49 +439,52 @@ static int wakeup_secondary_cpu(int phys_apicid, unsi= gned long start_eip) apic_write(APIC_ESR, 0); apic_read(APIC_ESR); =20 - Dprintk("Asserting INIT.\n"); + if ( send_INIT ) + { + Dprintk("Asserting INIT.\n"); =20 - /* - * Turn INIT on target chip via IPI - */ - apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, - phys_apicid); + /* + * Turn INIT on target chip via IPI + */ + apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, + phys_apicid); =20 - if ( !x2apic_enabled ) - { - Dprintk("Waiting for send to finish...\n"); - timeout =3D 0; - do { - Dprintk("+"); - udelay(100); - send_status =3D apic_read(APIC_ICR) & APIC_ICR_BUSY; - } while ( send_status && (timeout++ < 1000) ); + if ( !x2apic_enabled ) + { + Dprintk("Waiting for send to finish...\n"); + timeout =3D 0; + do { + Dprintk("+"); + udelay(100); + send_status =3D apic_read(APIC_ICR) & APIC_ICR_BUSY; + } while ( send_status && (timeout++ < 1000) ); =20 - mdelay(10); + mdelay(10); =20 - Dprintk("Deasserting INIT.\n"); + Dprintk("Deasserting INIT.\n"); =20 - apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); + apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); =20 - Dprintk("Waiting for send to finish...\n"); - timeout =3D 0; - do { - Dprintk("+"); - udelay(100); - send_status =3D apic_read(APIC_ICR) & APIC_ICR_BUSY; - } while ( send_status && (timeout++ < 1000) ); - } - else if ( tboot_in_measured_env() ) - { - /* - * With tboot AP is actually spinning in a mini-guest before - * receiving INIT. Upon receiving INIT ipi, AP need time to VMExit, - * update VMCS to tracking SIPIs and VMResume. - * - * While AP is in root mode handling the INIT the CPU will drop - * any SIPIs - */ - udelay(10); + Dprintk("Waiting for send to finish...\n"); + timeout =3D 0; + do { + Dprintk("+"); + udelay(100); + send_status =3D apic_read(APIC_ICR) & APIC_ICR_BUSY; + } while ( send_status && (timeout++ < 1000) ); + } + else if ( tboot_in_measured_env() ) + { + /* + * With tboot AP is actually spinning in a mini-guest before + * receiving INIT. Upon receiving INIT ipi, AP need time to VM= Exit, + * update VMCS to tracking SIPIs and VMResume. + * + * While AP is in root mode handling the INIT the CPU will drop + * any SIPIs + */ + udelay(10); + } } =20 maxlvt =3D get_maxlvt(); --=20 2.11.0 From nobody Sun May 5 19:19:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1610752304; cv=none; d=zohomail.com; s=zohoarc; b=ZYlm+kvkceNljLuZEyRjwDQEdcWLIMFsocJ6kdz78G7ZvWC/4+DHdy5ilkXlSsPXIQnB9aEaEpOI+qFq1CYP0V7GkqTsxz+RjwFd/t5nwpb8q+BjgRWH6PS300nnqgbqQqKRZRHbNwZ7mFyCBUuntDoIVMLR4rHhQcS4go9lWfo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610752304; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3u7QhkjoQJ+MJeJdrlev9yfqS011P9sBZiQfUkm59cQ=; b=Lm0v5Vo4ycx1RjYFkSMQyQnBXvDh7VtgwTT8J9ZZYlq4GNXOMVRsS6Wa1PkskgFmfV/U3kxElYahpx0BoIDA/kiABJBqUJpxsX5lH3dgJDvtmDRvQWdE7QTGtzuxssa3yNI8jrQH1MGSzIdD4THDnw4gX3PpP16jMZA0tjty2CY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1610752304000494.1040226017276; Fri, 15 Jan 2021 15:11:44 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.68832.123368 (Exim 4.92) (envelope-from ) id 1l0YFV-00063b-Se; Fri, 15 Jan 2021 23:11:21 +0000 Received: by outflank-mailman (output) from mailman id 68832.123368; Fri, 15 Jan 2021 23:11:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1l0YFV-00063T-Mt; Fri, 15 Jan 2021 23:11:21 +0000 Received: by outflank-mailman (input) for mailman id 68832; Fri, 15 Jan 2021 23:11:20 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1l0YFU-0005vh-DA for xen-devel@lists.xenproject.org; Fri, 15 Jan 2021 23:11:20 +0000 Received: from esa4.hc3370-68.iphmx.com (unknown [216.71.155.144]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ac0a538e-3bc2-4d97-8358-958fcbeebe0d; Fri, 15 Jan 2021 23:11:11 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ac0a538e-3bc2-4d97-8358-958fcbeebe0d DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1610752270; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VKbjRpGNczWYULk90MvOqyNNrgUHfZhx9ZjhjLAEyLs=; b=Rmv18cAKcK0Ywlkb7eQAu1VAAzjndgVEr+H02zytrFUKxmvAIXFgQkB8 kie97lsE76tJ5GrBr2/fkFgKggsJopqrPWddVeqo5XDgJ/FIzPxt/ScGd EnhMdnchxmijg2cp5stvSK9KSCfKONkC7Us5X3Gkib7IT6xFPiw8SL798 8=; Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: uCzw+f9s4rOBMDS813uY3+Ky8SjSrh0lPMgIJzf33qvYtIn0KVRHcXGyDpWt2hv+0CwzJxxuR0 E61YrCVrElz9OfgX3xOeSUWVv0PHjuhrtP+x0C4gkRM+3GqUHR54pfTV0MCo0W0pmIJTY9TqVc 3zhLVPRvLS+diaXaqTXexLJ+ZQrSP5eOpvwkXCo9Ubguotzn34T2xO1SAx3ZryJGVy3cTK1k/0 rJcTXioeqLawiQmzlnj4Q8/W4xdzBJ6ErC+uvZPYhc1RYk0cZsJDpO0kWGvMKH1KwOR4GieEOn UGk= X-SBRS: 5.1 X-MesageID: 36513458 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.79,350,1602561600"; d="scan'208";a="36513458" From: Andrew Cooper To: Xen-devel CC: =?UTF-8?q?Norbert=20Kami=C5=84ski?= , "Marek Kasiewicz" , Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu , Michal Zygowski , Piotr Krol , Krystian Hebel , "Daniel P . Smith" , Rich Persaud , Christopher Clark Subject: [PATCH 3/3] x86: Support booting under Secure Startup via SKINIT Date: Fri, 15 Jan 2021 23:10:46 +0000 Message-ID: <20210115231046.31785-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210115231046.31785-1-andrew.cooper3@citrix.com> References: <20210115231046.31785-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) From: Norbert Kami=C5=84ski For now, this is simply enough logic to let Xen come up after the bootloader has executed an SKINIT instruction to begin a Secure Startup. During a Secure Startup, the BSP operates with the GIF clear (blocks all external interrupts, even SMI/NMI), and INIT_REDIRECTION active (converts I= NIT IPIs to #SX exceptions, if e.g. the platform needs to scrub secrets before resetting). To afford APs the same Secure Startup protections as the BSP, = the INIT IPI must be skipped, and SIPI must be the first interrupt seen. Full details are available in AMD APM Vol2 15.27 "Secure Startup with SKINI= T" Introduce skinit_enable_intr() and call it from cpu_init(), next to the enable_nmis() which performs a related function for tboot startups. Also introduce ap_boot_method to control the sequence of actions for AP boo= t. Signed-off-by: Marek Kasiewicz Signed-off-by: Norbert Kami=C5=84ski Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Marek Kasiewicz CC: Norbert Kami=C5=84ski CC: Michal Zygowski CC: Piotr Krol CC: Krystian Hebel CC: Daniel P. Smith CC: Rich Persaud CC: Christopher Clark --- xen/arch/x86/cpu/common.c | 32 ++++++++++++++++++++++++++++++++ xen/arch/x86/smpboot.c | 12 +++++++++++- xen/include/asm-x86/cpufeature.h | 1 + xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/processor.h | 6 ++++++ 5 files changed, 51 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index a684519a20..d9a103e721 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -834,6 +834,29 @@ void load_system_tables(void) BUG_ON(system_state !=3D SYS_STATE_early_boot && (stack_bottom & 0xf)); } =20 +static void skinit_enable_intr(void) +{ + uint64_t val; + + /* + * If the platform is performing a Secure Launch via SKINIT + * INIT_REDIRECTION flag will be active. + */ + if ( !cpu_has_skinit || rdmsr_safe(MSR_K8_VM_CR, val) || + !(val & VM_CR_INIT_REDIRECTION) ) + return; + + ap_boot_method =3D AP_BOOT_SKINIT; + + /* + * We don't yet handle #SX. Disable INIT_REDIRECTION first, before + * enabling GIF, so a pending INIT resets us, rather than causing a + * panic due to an unknown exception. + */ + wrmsr_safe(MSR_K8_VM_CR, val & ~VM_CR_INIT_REDIRECTION); + asm volatile ( ".byte 0x0f,0x01,0xdc" /* STGI */ ::: "memory" ); +} + /* * cpu_init() initializes state that is per-CPU. Some data is already * initialized (naturally) in the bootstrap process, such as the GDT @@ -865,6 +888,15 @@ void cpu_init(void) write_debugreg(6, X86_DR6_DEFAULT); write_debugreg(7, X86_DR7_DEFAULT); =20 + /* + * If the platform is performing a Secure Launch via SKINIT, GIF is + * clear to prevent external interrupts interfering with Secure + * Startup. Re-enable all interrupts now that we are suitably set up. + * + * Refer to AMD APM Vol2 15.27 "Secure Startup with SKINIT". + */ + skinit_enable_intr(); + /* Enable NMIs. Our loader (e.g. Tboot) may have left them disabled. */ enable_nmis(); } diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 195e3681b4..0f11fea7be 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -49,6 +49,7 @@ #include =20 unsigned long __read_mostly trampoline_phys; +enum ap_boot_method __read_mostly ap_boot_method =3D AP_BOOT_NORMAL; =20 /* representing HT siblings of each logical CPU */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); @@ -424,7 +425,16 @@ static int wakeup_secondary_cpu(int phys_apicid, unsig= ned long start_eip) { unsigned long send_status =3D 0, accept_status =3D 0; int maxlvt, timeout, i; - bool send_INIT =3D true; + + /* + * Normal AP startup uses an INIT-SIPI-SIPI sequence. + * + * When using SKINIT for Secure Startup, the INIT IPI must be skipped,= so + * that SIPI is the first interrupt the AP sees. + * + * Refer to AMD APM Vol2 15.27 "Secure Startup with SKINIT". + */ + bool send_INIT =3D ap_boot_method !=3D AP_BOOT_SKINIT; =20 /* * Some versions of tboot might be able to handle the entire wake sequ= ence diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index ad3d84bdde..f62e526a96 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -76,6 +76,7 @@ #define cpu_has_svm boot_cpu_has(X86_FEATURE_SVM) #define cpu_has_sse4a boot_cpu_has(X86_FEATURE_SSE4A) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) +#define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) =20 diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-inde= x.h index ff583cf0ed..1f5a5d0e38 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -117,6 +117,7 @@ #define PASID_VALID (_AC(1, ULL) << 31) =20 #define MSR_K8_VM_CR 0xc0010114 +#define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) =20 /* diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index 9acb80fdcd..d5f467d245 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -631,6 +631,12 @@ static inline uint8_t get_cpu_family(uint32_t raw, uin= t8_t *model, extern int8_t opt_tsx, cpu_has_tsx_ctrl; void tsx_init(void); =20 +enum ap_boot_method { + AP_BOOT_NORMAL, + AP_BOOT_SKINIT, +}; +extern enum ap_boot_method ap_boot_method; + #endif /* !__ASSEMBLY__ */ =20 #endif /* __ASM_X86_PROCESSOR_H */ --=20 2.11.0 From nobody Sun May 5 19:19:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1611920749; cv=none; d=zohomail.com; s=zohoarc; b=QfezjDl/qJapJbFP4BdQLpx+TRUcjEn0WhpP8gRlGDDkGOCNHDxbhY6K2hCiG2HUX65ftG7Do3QuvX+tiSVHkLyRqDnSstXo9kh6qqqES4rFz+v/K0OV//kxbM7TJvGl9sYq18cnTw1v8O19gFz/5y+87B0TuBLVuIsU8b3PuIo= ARC-Message-Signature: i=1; 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Smith" , Rich Persaud , Christopher Clark Subject: [PATCH v2 3/3] x86: Support booting under Secure Startup via SKINIT Date: Fri, 29 Jan 2021 11:45:10 +0000 Message-ID: <20210129114510.30966-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210115231046.31785-1-andrew.cooper3@citrix.com> References: <20210115231046.31785-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) From: Norbert Kami=C5=84ski For now, this is simply enough logic to let Xen come up after the bootloader has executed an SKINIT instruction to begin a Secure Startup. During a Secure Startup, the BSP operates with the GIF clear (blocks all external interrupts, even SMI/NMI), and INIT_REDIRECTION active (converts I= NIT IPIs to #SX exceptions, if e.g. the platform needs to scrub secrets before resetting). To afford APs the same Secure Startup protections as the BSP, = the INIT IPI must be skipped, and SIPI must be the first interrupt seen. Full details are available in AMD APM Vol2 15.27 "Secure Startup with SKINI= T" Introduce skinit_enable_intr() and call it from cpu_init(), next to the enable_nmis() which performs a related function for tboot startups. Also introduce ap_boot_method to control the sequence of actions for AP boo= t. Signed-off-by: Marek Kasiewicz Signed-off-by: Norbert Kami=C5=84ski Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu CC: Marek Kasiewicz CC: Norbert Kami=C5=84ski CC: Michal Zygowski CC: Piotr Krol CC: Krystian Hebel CC: Daniel P. Smith CC: Rich Persaud CC: Christopher Clark v2: * Rebase over 'stgi' cleanup * Don't use wrmsr_safe(). --- xen/arch/x86/cpu/common.c | 32 ++++++++++++++++++++++++++++++++ xen/arch/x86/smpboot.c | 12 +++++++++++- xen/include/asm-x86/cpufeature.h | 1 + xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/processor.h | 6 ++++++ 5 files changed, 51 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index a684519a20..cca97e4e03 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -834,6 +834,29 @@ void load_system_tables(void) BUG_ON(system_state !=3D SYS_STATE_early_boot && (stack_bottom & 0xf)); } =20 +static void skinit_enable_intr(void) +{ + uint64_t val; + + /* + * If the platform is performing a Secure Launch via SKINIT + * INIT_REDIRECTION flag will be active. + */ + if ( !cpu_has_skinit || rdmsr_safe(MSR_K8_VM_CR, val) || + !(val & VM_CR_INIT_REDIRECTION) ) + return; + + ap_boot_method =3D AP_BOOT_SKINIT; + + /* + * We don't yet handle #SX. Disable INIT_REDIRECTION first, before + * enabling GIF, so a pending INIT resets us, rather than causing a + * panic due to an unknown exception. + */ + wrmsr(MSR_K8_VM_CR, val & ~VM_CR_INIT_REDIRECTION); + asm volatile ( "stgi" ::: "memory" ); +} + /* * cpu_init() initializes state that is per-CPU. Some data is already * initialized (naturally) in the bootstrap process, such as the GDT @@ -865,6 +888,15 @@ void cpu_init(void) write_debugreg(6, X86_DR6_DEFAULT); write_debugreg(7, X86_DR7_DEFAULT); =20 + /* + * If the platform is performing a Secure Launch via SKINIT, GIF is + * clear to prevent external interrupts interfering with Secure + * Startup. Re-enable all interrupts now that we are suitably set up. + * + * Refer to AMD APM Vol2 15.27 "Secure Startup with SKINIT". + */ + skinit_enable_intr(); + /* Enable NMIs. Our loader (e.g. Tboot) may have left them disabled. */ enable_nmis(); } diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 61ce923189..82c1012e89 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -49,6 +49,7 @@ #include =20 unsigned long __read_mostly trampoline_phys; +enum ap_boot_method __read_mostly ap_boot_method =3D AP_BOOT_NORMAL; =20 /* representing HT siblings of each logical CPU */ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); @@ -424,7 +425,16 @@ static int wakeup_secondary_cpu(int phys_apicid, unsig= ned long start_eip) { unsigned long send_status =3D 0, accept_status =3D 0; int maxlvt, timeout, i; - bool send_INIT =3D true; + + /* + * Normal AP startup uses an INIT-SIPI-SIPI sequence. + * + * When using SKINIT for Secure Startup, the INIT IPI must be skipped,= so + * that SIPI is the first interrupt the AP sees. + * + * Refer to AMD APM Vol2 15.27 "Secure Startup with SKINIT". + */ + bool send_INIT =3D ap_boot_method !=3D AP_BOOT_SKINIT; =20 /* * Some versions of tboot might be able to handle the entire wake sequ= ence diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeat= ure.h index ad3d84bdde..f62e526a96 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -76,6 +76,7 @@ #define cpu_has_svm boot_cpu_has(X86_FEATURE_SVM) #define cpu_has_sse4a boot_cpu_has(X86_FEATURE_SSE4A) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) +#define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) =20 diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-inde= x.h index ff583cf0ed..1f5a5d0e38 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -117,6 +117,7 @@ #define PASID_VALID (_AC(1, ULL) << 31) =20 #define MSR_K8_VM_CR 0xc0010114 +#define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) =20 /* diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processo= r.h index 9acb80fdcd..d5f467d245 100644 --- a/xen/include/asm-x86/processor.h +++ b/xen/include/asm-x86/processor.h @@ -631,6 +631,12 @@ static inline uint8_t get_cpu_family(uint32_t raw, uin= t8_t *model, extern int8_t opt_tsx, cpu_has_tsx_ctrl; void tsx_init(void); =20 +enum ap_boot_method { + AP_BOOT_NORMAL, + AP_BOOT_SKINIT, +}; +extern enum ap_boot_method ap_boot_method; + #endif /* !__ASSEMBLY__ */ =20 #endif /* __ASM_X86_PROCESSOR_H */ --=20 2.11.0 From nobody Sun May 5 19:19:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1611917178; cv=none; d=zohomail.com; s=zohoarc; b=Tpusx78m75VdwuIEsB8A7/3mX0oPNT7hX0Kw3vSLT8vqeN1HoVIA6jocH4Q0gYpIA3TMwr6Ihk2TXC813MEuUM+wo7jSuovwI/fn4PsrwL0gxuW4a4xmLPSjAYRS1CyqDSHGv1muynWYP8zMUe4pbAWNdcs2oUUcUgnTTCsKcxc= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) ... in order to reuse stgi elsewhere. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Wei Liu --- xen/arch/x86/hvm/svm/entry.S | 10 +++------- xen/include/asm-x86/asm-defns.h | 12 ++++++++++++ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/hvm/svm/entry.S b/xen/arch/x86/hvm/svm/entry.S index 1d2df08e89..e208a4b32a 100644 --- a/xen/arch/x86/hvm/svm/entry.S +++ b/xen/arch/x86/hvm/svm/entry.S @@ -22,10 +22,6 @@ #include #include =20 -#define VMRUN .byte 0x0F,0x01,0xD8 -#define STGI .byte 0x0F,0x01,0xDC -#define CLGI .byte 0x0F,0x01,0xDD - ENTRY(svm_asm_do_resume) GET_CURRENT(bx) .Lsvm_do_resume: @@ -82,9 +78,9 @@ __UNLIKELY_END(nsvm_hap) pop %rsi pop %rdi =20 - CLGI + clgi sti - VMRUN + vmrun =20 SAVE_ALL =20 @@ -93,7 +89,7 @@ __UNLIKELY_END(nsvm_hap) SPEC_CTRL_ENTRY_FROM_HVM /* Req: b=3Dcurr %rsp=3Dregs/cpuinfo, = Clob: acd */ /* WARNING! `ret`, `call *`, `jmp *` not safe before this point. */ =20 - STGI + stgi GLOBAL(svm_stgi_label) mov %rsp,%rdi call svm_vmexit_handler diff --git a/xen/include/asm-x86/asm-defns.h b/xen/include/asm-x86/asm-defn= s.h index 43f4868d40..2e3ec0ac01 100644 --- a/xen/include/asm-x86/asm-defns.h +++ b/xen/include/asm-x86/asm-defns.h @@ -8,6 +8,18 @@ .endm #endif =20 +.macro vmrun + .byte 0x0f, 0x01, 0xd8 +.endm + +.macro stgi + .byte 0x0f, 0x01, 0xdc +.endm + +.macro clgi + .byte 0x0f, 0x01, 0xdd +.endm + .macro INDIRECT_BRANCH insn:req arg:req /* * Create an indirect branch. insn is one of call/jmp, arg is a single --=20 2.11.0