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client-ip=40.67.248.234; helo=nebula.arm.com; From: Wei Chen To: , , , CC: , , , Subject: [PATCH] xen/arm: Using unsigned long for arm64 MPIDR mask Date: Tue, 5 Jan 2021 18:17:51 +0800 Message-ID: <20210105101751.1972883-1-wei.chen@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 702f284d-ea62-4947-5e23-08d8b1633c15 X-MS-TrafficTypeDiagnostic: DB6PR0802MB2343:|AM0PR08MB5172: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:538;OLM:538; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 9CRTnAxVbCjWVVN7xZMWcG29QApoBGv2uL36KZ2CUW8Qb3K3/9qmmR4JkiHqNnkKydhLCnBZtfLjuDMlrqVQEC2HGuWKUQFqMc8MZ6uMqoiYyKHTgvjukdl/T0+C4oxtDsg0TEMRfKPCoa7kKT9A9NX9ZwLY36o460ptEHJekF1V/0UM2hr3jnfWHLp4v9QJoNl8p3UyHtVSGmZdLRen7jsWz3snCgIjF0L2QvUkT+EInythGdxzBlPPl3q/J4wBmxrL+tn/D8JcKiuxdBUqf5un5TIKzY7NotYQUNaRgpZ3jyJJWv8YH4YDJP9grcQC5A+G24RyiTansfLsazpun0BMmHlY+/K/QB5U7VzvHMNf2SUKQWZBj+u2ZBmihuYpAcjAt0GuXPpPg6S0NV47jSxPJ9UyEA868zv5Kr18umZuWJfzdU8Z847/aMqVZfDjcc7XoY6CVd8QCVLj+UxU3Q== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(136003)(346002)(376002)(396003)(39860400002)(46966006)(36756003)(86362001)(44832011)(110136005)(54906003)(7696005)(2616005)(426003)(5660300002)(336012)(478600001)(1076003)(8676002)(2906002)(8936002)(4326008)(26005)(316002)(186003)(70206006)(70586007)(47076005)(83380400001)(356005)(81166007)(82740400003)(82310400003)(6666004);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2021 10:18:24.0227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 702f284d-ea62-4947-5e23-08d8b1633c15 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5172 X-ZohoMail-DKIM: pass (identity @armh.onmicrosoft.com) Content-Type: text/plain; charset="utf-8" Curretly, Xen is using UINT32 for MPIDR mask to retrieve affinity[0,1,2,3] values for MPIDR_EL1 register. The value of MPIDR_EL1 is 64-bit unsigned long. The operation of 64-bit and 32-bit integers are compiler related. This means the value is unpredictable. For example, when we are using MPIDR_AFF0_MASK to get cluster_id from a 64-bit integer in gic-v3 driver: uint64_t cluster_id =3D cpu_logical_map(cpu) & ~MPIDR_AFF0_MASK; When MPIDR_AFF0_MASK is UINT32, compiler output: f7c: 92785c16 and x22, x0, #0xffffff00 When MPIDR_AFF0_MASK is unsigned long, compiler output: f88: 9278dc75 and x21, x3, #0xffffffffffffff00 If we have a cpu_logical_map(cpu)=3D 0x1,00000000. We except to get a cluster_id 1, but with UINT32 MPIDR_AFF0_MASK, we will get 0. So, in this patch, we force aarch64 to use unsigned long as MPIDR mask to avoid such unpredictable operations. Signed-off-by: Wei Chen --- xen/include/asm-arm/processor.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processo= r.h index 87c8136022..5c1768cdec 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -75,11 +75,11 @@ =20 /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30) -#define MPIDR_UP (_AC(1,U) << _MPIDR_UP) +#define MPIDR_UP (_AC(1,UL) << _MPIDR_UP) #define _MPIDR_SMP (31) -#define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP) +#define MPIDR_SMP (_AC(1,UL) << _MPIDR_SMP) #define MPIDR_AFF0_SHIFT (0) -#define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT) +#define MPIDR_AFF0_MASK (_AC(0xff,UL) << MPIDR_AFF0_SHIFT) #ifdef CONFIG_ARM_64 #define MPIDR_HWID_MASK _AC(0xff00ffffff,UL) #else --=20 2.25.1