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[5.71.162.151]) by smtp.gmail.com with ESMTPSA id u23sm4096078wmc.32.2020.11.11.13.52.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Nov 2020 13:52:46 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 61dd892c-4a6a-4f81-9b53-1d30211448c1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lKBI14xArPA18L2e3mixfdhgDGBWzfLh6HwsMuwD7s4=; b=CBI9vPn64FgxZuhJIGgbZ3efbwKrz8NpUktTKCWRjraau29LdgEClES3irHVLpGUm1 PH9SNGgWKskLHy7zAA2Kjx+f91g2KNDKIDtuiqP8qYLuKzShz0dT4Q7vUS6NTcODUEd7 y874QrlFnnZ977xY7QVX3xrXv2FmvnYODQDijgqFBj4uX6Y+NmZDL5u6L3ZAD/U6IsY9 +H0KpYzeFk7jMdwO45yQ32wFe+Zf+kflZxzBEAgMhgQLaUuCe4HiNiCr45HiOVJGR4IC ECH4u/Huk+/B1zRTwJk6af7hrBZIkXcam1P2jnhORqvMqz+WsdK4uiow7aPmlQ/hJ/6t VymA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lKBI14xArPA18L2e3mixfdhgDGBWzfLh6HwsMuwD7s4=; b=sewc1Z+wtYJqdyUkZL5kMdzjyeDKYvVKxXvx5wEjcMDG2R/RSz+6RJsnabvwTHup5m YkvPaVkg84LEU6viguu4IIa/wHNWBAteetAQtDVyggvRu+93GPQ9OAyGzyjQv5MTECxb Es9YZxyfWl42XDVJbQKoJv2QcHnkFOU3Wog2mcOeGD5qSSSdM7fnPUBRnvf+crJCip0C OdVhnrwwpai7iNej2ARykg3KzJt3L2dzhwnGpjbEdkGDPGDlJtwDCGmC/JsJaWh/3QlS WPqth4cKVd8S1WqnFA+7OORnMfO7C2SRPnVwr4Yocls3cXYP3kyPyp3KcaGWYTcBX49P StlA== X-Gm-Message-State: AOAM531HR7nC/Lc1eWMWVpiO13FmQkwIoPcFag3wAa07K+W7W1XwYuwO txTW4f9Qrur1Yn9e2gEyPcdAuogRjug= X-Google-Smtp-Source: ABdhPJy/UaGSodvWycXJfP8lDDsD6AfWRUcQrVgiracEK6FwIOITn2EXSSWznnSwQQjRw7T4lAgMzA== X-Received: by 2002:adf:e44f:: with SMTP id t15mr29024528wrm.380.1605131567174; Wed, 11 Nov 2020 13:52:47 -0800 (PST) From: Ash Wilding X-Google-Original-From: Ash Wilding To: xen-devel@lists.xenproject.org Cc: Ash Wilding , julien@xen.org, bertrand.marquis@arm.com, rahul.singh@arm.com Subject: [RFC PATCH v2 07/15] xen/arm: prepare existing Xen headers for Linux atomics Date: Wed, 11 Nov 2020 21:51:55 +0000 Message-Id: <20201111215203.80336-8-ash.j.wilding@gmail.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20201111215203.80336-1-ash.j.wilding@gmail.com> References: <20201111215203.80336-1-ash.j.wilding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" From: Ash Wilding This small patch helps prepare and the arm32/arm64 specific system.h headers to play nicely with the Linux atomics helpers: - We don't need the indirection around atomic_add_unless() anymore so let's just pull up the old Xen arm64 definition into here and use it for both arm32 and arm64. - We don't need an atomic_xchg() in as the arm32/arm64 specific cmpxchg.h from Linux defines it for us. - We drop the includes of and from as they're not needed. - We swap out the include of the arm32/arm64 specific cmpxchg.h in the arm32/arm64 specific system.h and instead make them include atomic.h; this works around build issues from cmpxchg.h trying to use the __ll_sc_lse_body() macro before it's ready. Signed-off-by: Ash Wilding --- xen/include/asm-arm/arm32/system.h | 2 +- xen/include/asm-arm/arm64/system.h | 2 +- xen/include/asm-arm/atomic.h | 15 +++++++++++---- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/xen/include/asm-arm/arm32/system.h b/xen/include/asm-arm/arm32= /system.h index ab57abfbc5..88798d11db 100644 --- a/xen/include/asm-arm/arm32/system.h +++ b/xen/include/asm-arm/arm32/system.h @@ -2,7 +2,7 @@ #ifndef __ASM_ARM32_SYSTEM_H #define __ASM_ARM32_SYSTEM_H =20 -#include +#include =20 #define local_irq_disable() asm volatile ( "cpsid i @ local_irq_disable\n"= : : : "cc" ) #define local_irq_enable() asm volatile ( "cpsie i @ local_irq_enable\n" = : : : "cc" ) diff --git a/xen/include/asm-arm/arm64/system.h b/xen/include/asm-arm/arm64= /system.h index 2e36573ac6..dfbbe4b87d 100644 --- a/xen/include/asm-arm/arm64/system.h +++ b/xen/include/asm-arm/arm64/system.h @@ -2,7 +2,7 @@ #ifndef __ASM_ARM64_SYSTEM_H #define __ASM_ARM64_SYSTEM_H =20 -#include +#include =20 /* Uses uimm4 as a bitmask to select the clearing of one or more of * the DAIF exception mask bits: diff --git a/xen/include/asm-arm/atomic.h b/xen/include/asm-arm/atomic.h index ac2798d095..866f54d03c 100644 --- a/xen/include/asm-arm/atomic.h +++ b/xen/include/asm-arm/atomic.h @@ -2,8 +2,6 @@ #define __ARCH_ARM_ATOMIC__ =20 #include -#include -#include =20 #define build_atomic_read(name, size, width, type) \ static inline type name(const volatile type *addr) \ @@ -220,10 +218,19 @@ static inline int atomic_add_negative(int i, atomic_t= *v) =20 static inline int atomic_add_unless(atomic_t *v, int a, int u) { - return __atomic_add_unless(v, a, u); + int c, old; + + c =3D atomic_read(v); + while (c !=3D u && (old =3D atomic_cmpxchg((v), c, c + a)) !=3D c) + c =3D old; + + return c; } =20 -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) +static inline int atomic_cmpxchg(atomic_t *v, int old, int new) +{ + return cmpxchg(&((v)->counter), (old), (new)); +} =20 #endif /* __ARCH_ARM_ATOMIC__ */ /* --=20 2.24.3 (Apple Git-128)