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charset="utf-8" Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports FP/SIMD or not. But currently, this two MACROs only consider value 0 of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs that support FP/SIMD and half-precision floating-point features, the ID_AA64PFR0_EL1.FP/SIMD are 1. For these CPUs, xen will treat them as no FP/SIMD support. In this case, the vfp_save/restore_state will not take effect. Unfortunately, Cortex-N1/A76/A75 are the CPUs support FP/SIMD and half-precision floatiing-point. Their ID_AA64PFR0_EL1.FP/SMID are 1 (see Arm ARM DDI0487F.b, D13.2.64). In this case, on N1/A76/A75 platforms, Xen will always miss the float pointer registers save/restore. If different vCPUs are running on the same pCPU, the float pointer registers will be corrupted randomly. This patch fixes Xen on these new cores. Signed-off-by: Wei Chen Reviewed-by: Bertrand Marquis --- xen/include/asm-arm/cpufeature.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeat= ure.h index 674beb0353..588089e5ae 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -13,8 +13,8 @@ #define cpu_has_el2_64 (boot_cpu_feature64(el2) >=3D 1) #define cpu_has_el3_32 (boot_cpu_feature64(el3) =3D=3D 2) #define cpu_has_el3_64 (boot_cpu_feature64(el3) >=3D 1) -#define cpu_has_fp (boot_cpu_feature64(fp) =3D=3D 0) -#define cpu_has_simd (boot_cpu_feature64(simd) =3D=3D 0) +#define cpu_has_fp (boot_cpu_feature64(fp) <=3D 1) +#define cpu_has_simd (boot_cpu_feature64(simd) <=3D 1) #define cpu_has_gicv3 (boot_cpu_feature64(gic) =3D=3D 1) #endif -- 2.17.1 IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. 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