From nobody Tue Apr 23 07:14:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1595352201; cv=none; d=zohomail.com; s=zohoarc; b=c34ZYtnS+LfVhfGTlA8J9cMR6XOtHfzKoXGyJGpJ3JJkuKEB7EUwHk5Xvu5PeaxiGFWc9uJYZsOAIO4KNuTlqyWuzUrbzGYMnuGqde/la5w2Q618b/pRrGDYdVpBR3fuLDOVPXUHihcuQjrwoOcDMAyuf8ADxA6DwVrWErKD0FA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1595352201; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=9SDjt/VXoVQm95ieQu0psEEZfgPvoM4RLM8qMYa7NpI=; b=oBU0VHnJKVsERuCqvH72FoFHLGuhiuvBESPr4jOn+IP3urgIlQmBzr3PUVGkJRA5/3EJrjqTLGyYXSj+B9lFHCwpbSedjPowiFvRXwMfjlrljJvkB1MOX2pwDiYx/MqxtCk/AOoMIPgmZplI1wyQdxwH4rDOi6rJFhigR8n9vNQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1595352201032866.7793284009068; Tue, 21 Jul 2020 10:23:21 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jxvyQ-0003MU-Kb; Tue, 21 Jul 2020 17:22:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jxvyP-0003MP-HE for xen-devel@lists.xenproject.org; Tue, 21 Jul 2020 17:22:37 +0000 Received: from esa5.hc3370-68.iphmx.com (unknown [216.71.155.168]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id c48d8004-cb76-11ea-a110-12813bfff9fa; Tue, 21 Jul 2020 17:22:35 +0000 (UTC) X-Inumbo-ID: c48d8004-cb76-11ea-a110-12813bfff9fa DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=citrix.com; s=securemail; t=1595352155; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=U9TFSiMPyXpVYVZMejGmia8JMd9i23k5xSQc2PVJ5+Q=; b=QeLcFQZen2EDU7lLxnAUVZa7d4JkphtLpPoA+prKL0Ng6V1nAEOk0ecm FaAhNA34xl0HIuGBAXxSswHqnYySXojnXH5mc1htWx789zHown9TVKJrp LHY8lOFN/Dx+xHkrtCvVsrjtJ/spIFbUhssBo1Pp14F/m0et/eP/nMHGh Y=; Authentication-Results: esa5.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: 4JDADQ/sytG4ozsWr7yIeK7GkrOMB6CevNqwqE5rav/DcjQYI9gvEU6aoeAvqmntPFkur9u+bH ma409rlwRPmVD7noc2pT5LTeslcZOWqOhBjrg55k0/YYu1m+3VvWlIE2waX1PFrJ9I8pclf+zq z9nRcXDFZP6Yq9zxciOo26Tupvv8+AlgaEZg9xMYVQTdo5YfDD0ds60rI1B+8U6V7AxIg5otQk Wb4FkN8VeWkx+bE6mlPRF9UD0+SDVafoRZu1tSsRjPZSgHu1GbhDEEqxe4pFkNPp6/OY7aGlQM 5WQ= X-SBRS: 2.7 X-MesageID: 23065430 X-Ironport-Server: esa5.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.75,379,1589256000"; d="scan'208";a="23065430" From: Andrew Cooper To: Xen-devel Subject: [PATCH] x86/svm: Fold nsvm_{wr, rd}msr() into svm_msr_{read, write}_intercept() Date: Tue, 21 Jul 2020 18:22:08 +0100 Message-ID: <20200721172208.12176-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) ... to simplify the default cases. There are multiple errors with the handling of these three MSRs, but they a= re deliberately not addressed this point. This removes the dance converting -1/0/1 into X86EMUL_*, allowing for the removal of the 'ret' variable. While cleaning this up, drop the gdprintk()'s for #GP conditions, and the 'result' variable from svm_msr_write_intercept() is it is never modified. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- CC: Jan Beulich CC: Wei Liu CC: Roger Pau Monn=C3=A9 --- xen/arch/x86/hvm/svm/nestedsvm.c | 77 -----------------------------= ---- xen/arch/x86/hvm/svm/svm.c | 46 +++++++++++++------- xen/include/asm-x86/hvm/svm/nestedsvm.h | 4 -- 3 files changed, 31 insertions(+), 96 deletions(-) diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nested= svm.c index 11dc9c089c..a193d9de45 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -47,22 +47,6 @@ nestedsvm_vcpu_stgi(struct vcpu *v) local_event_delivery_enable(); /* unmask events for PV drivers */ } =20 -static int -nestedsvm_vmcb_isvalid(struct vcpu *v, uint64_t vmcxaddr) -{ - /* Address must be 4k aligned */ - if ( (vmcxaddr & ~PAGE_MASK) !=3D 0 ) - return 0; - - /* Maximum valid physical address. - * See AMD BKDG for HSAVE_PA MSR. - */ - if ( vmcxaddr > 0xfd00000000ULL ) - return 0; - - return 1; -} - int nestedsvm_vmcb_map(struct vcpu *v, uint64_t vmcbaddr) { struct nestedvcpu *nv =3D &vcpu_nestedhvm(v); @@ -1263,67 +1247,6 @@ enum hvm_intblk nsvm_intr_blocked(struct vcpu *v) return hvm_intblk_none; } =20 -/* MSR handling */ -int nsvm_rdmsr(struct vcpu *v, unsigned int msr, uint64_t *msr_content) -{ - struct nestedsvm *svm =3D &vcpu_nestedsvm(v); - int ret =3D 1; - - *msr_content =3D 0; - - switch (msr) { - case MSR_K8_VM_CR: - break; - case MSR_K8_VM_HSAVE_PA: - *msr_content =3D svm->ns_msr_hsavepa; - break; - case MSR_AMD64_TSC_RATIO: - *msr_content =3D svm->ns_tscratio; - break; - default: - ret =3D 0; - break; - } - - return ret; -} - -int nsvm_wrmsr(struct vcpu *v, unsigned int msr, uint64_t msr_content) -{ - int ret =3D 1; - struct nestedsvm *svm =3D &vcpu_nestedsvm(v); - - switch (msr) { - case MSR_K8_VM_CR: - /* ignore write. handle all bits as read-only. */ - break; - case MSR_K8_VM_HSAVE_PA: - if (!nestedsvm_vmcb_isvalid(v, msr_content)) { - gdprintk(XENLOG_ERR, - "MSR_K8_VM_HSAVE_PA value invalid %#"PRIx64"\n", msr_conte= nt); - ret =3D -1; /* inject #GP */ - break; - } - svm->ns_msr_hsavepa =3D msr_content; - break; - case MSR_AMD64_TSC_RATIO: - if ((msr_content & ~TSC_RATIO_RSVD_BITS) !=3D msr_content) { - gdprintk(XENLOG_ERR, - "reserved bits set in MSR_AMD64_TSC_RATIO %#"PRIx64"\n", - msr_content); - ret =3D -1; /* inject #GP */ - break; - } - svm->ns_tscratio =3D msr_content; - break; - default: - ret =3D 0; - break; - } - - return ret; -} - /* VMEXIT emulation */ void nestedsvm_vmexit_defer(struct vcpu *v, diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 4eb41792e2..bbe73744b8 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1788,10 +1788,10 @@ static void svm_dr_access(struct vcpu *v, struct cp= u_user_regs *regs) =20 static int svm_msr_read_intercept(unsigned int msr, uint64_t *msr_content) { - int ret; struct vcpu *v =3D current; const struct domain *d =3D v->domain; struct vmcb_struct *vmcb =3D v->arch.hvm.svm.vmcb; + const struct nestedsvm *nsvm =3D &vcpu_nestedsvm(v); =20 switch ( msr ) { @@ -1914,6 +1914,18 @@ static int svm_msr_read_intercept(unsigned int msr, = uint64_t *msr_content) goto gpf; break; =20 + case MSR_K8_VM_CR: + *msr_content =3D 0; + break; + + case MSR_K8_VM_HSAVE_PA: + *msr_content =3D nsvm->ns_msr_hsavepa; + break; + + case MSR_AMD64_TSC_RATIO: + *msr_content =3D nsvm->ns_tscratio; + break; + case MSR_AMD_OSVW_ID_LENGTH: case MSR_AMD_OSVW_STATUS: if ( !d->arch.cpuid->extd.osvw ) @@ -1922,12 +1934,6 @@ static int svm_msr_read_intercept(unsigned int msr, = uint64_t *msr_content) break; =20 default: - ret =3D nsvm_rdmsr(v, msr, msr_content); - if ( ret < 0 ) - goto gpf; - else if ( ret ) - break; - if ( rdmsr_safe(msr, *msr_content) =3D=3D 0 ) break; =20 @@ -1956,10 +1962,10 @@ static int svm_msr_read_intercept(unsigned int msr,= uint64_t *msr_content) =20 static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content) { - int ret, result =3D X86EMUL_OKAY; struct vcpu *v =3D current; struct domain *d =3D v->domain; struct vmcb_struct *vmcb =3D v->arch.hvm.svm.vmcb; + struct nestedsvm *nsvm =3D &vcpu_nestedsvm(v); =20 switch ( msr ) { @@ -2085,6 +2091,22 @@ static int svm_msr_write_intercept(unsigned int msr,= uint64_t msr_content) goto gpf; break; =20 + case MSR_K8_VM_CR: + /* ignore write. handle all bits as read-only. */ + break; + + case MSR_K8_VM_HSAVE_PA: + if ( (msr_content & ~PAGE_MASK) || msr_content > 0xfd00000000ULL ) + goto gpf; + nsvm->ns_msr_hsavepa =3D msr_content; + break; + + case MSR_AMD64_TSC_RATIO: + if ( msr_content & TSC_RATIO_RSVD_BITS ) + goto gpf; + nsvm->ns_tscratio =3D msr_content; + break; + case MSR_IA32_MCx_MISC(4): /* Threshold register */ case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3: /* @@ -2102,12 +2124,6 @@ static int svm_msr_write_intercept(unsigned int msr,= uint64_t msr_content) break; =20 default: - ret =3D nsvm_wrmsr(v, msr, msr_content); - if ( ret < 0 ) - goto gpf; - else if ( ret ) - break; - /* Match up with the RDMSR side; ultimately this should go away. */ if ( rdmsr_safe(msr, msr_content) =3D=3D 0 ) break; @@ -2115,7 +2131,7 @@ static int svm_msr_write_intercept(unsigned int msr, = uint64_t msr_content) goto gpf; } =20 - return result; + return X86EMUL_OKAY; =20 gpf: return X86EMUL_EXCEPTION; diff --git a/xen/include/asm-x86/hvm/svm/nestedsvm.h b/xen/include/asm-x86/= hvm/svm/nestedsvm.h index 31fb4bfeb4..0873698457 100644 --- a/xen/include/asm-x86/hvm/svm/nestedsvm.h +++ b/xen/include/asm-x86/hvm/svm/nestedsvm.h @@ -118,10 +118,6 @@ bool_t nsvm_vmcb_guest_intercepts_event( bool_t nsvm_vmcb_hap_enabled(struct vcpu *v); enum hvm_intblk nsvm_intr_blocked(struct vcpu *v); =20 -/* MSRs */ -int nsvm_rdmsr(struct vcpu *v, unsigned int msr, uint64_t *msr_content); -int nsvm_wrmsr(struct vcpu *v, unsigned int msr, uint64_t msr_content); - /* Interrupts, vGIF */ void svm_vmexit_do_clgi(struct cpu_user_regs *regs, struct vcpu *v); void svm_vmexit_do_stgi(struct cpu_user_regs *regs, struct vcpu *v); --=20 2.11.0