From nobody Mon Feb 9 16:34:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1591977466; cv=none; d=zohomail.com; s=zohoarc; b=CJOyOeWVaQ6a+deFBNZ5QZrkN41wBLTnQuuyHMoCMvCPOGgsg6ODNRgDr1XKfIN55CQxZxuUPKefsCSx4ljiwL2L1Of9khm9jJYedGX62IQLZsdV8zevFrMvEqOTVzrC9qMdhHIdSuAVPDLfIeYYOIIl3h0r806HpGXZvvHiKxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591977466; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zdwNVvv/uZSDiw3r+aXCsaRtm7Kn5rzl0pi2LfPZ06U=; b=Dv3t5bTBZZQ22YEm+pHNa8V2zYm198i2qC3vPe7zkDl9YoEsZ07zHmvOHtiZU2IP3wPiL8b2Qf9GfS7pbGnm2bg8yieM3LZUL5fnvZ11mgCmII9tOXezEusvUCG1m2qB8sAuYEYm1eLv0ENhdqu2EGW+JEPVNnbNwGQSUNYRax4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1591977466446848.7189277339486; Fri, 12 Jun 2020 08:57:46 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jjm3h-0006Tn-Fb; Fri, 12 Jun 2020 15:57:33 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1jjm3g-0006Lr-3G for xen-devel@lists.xenproject.org; Fri, 12 Jun 2020 15:57:32 +0000 Received: from esa4.hc3370-68.iphmx.com (unknown [216.71.155.144]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 6a382f84-acc5-11ea-bb8b-bc764e2007e4; Fri, 12 Jun 2020 15:57:28 +0000 (UTC) X-Inumbo-ID: 6a382f84-acc5-11ea-bb8b-bc764e2007e4 Authentication-Results: esa4.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none IronPort-SDR: nk10nRa/UyvEBV7y95MSrL+xvq0BM4oOMyFXxhDkS9COEmbBEEVgBpmDzpoDGprQ6qVnQJMxYY cdUWfwWeyEOknClS0zJXDeJAzX56V9SNb1bAzIY5rfyY9cQPkTd2aCcG5iXeR3h4MGJKkDX/RZ 0oaEMHruPAp2CU86Sx0lGU+UmTq18Z7ngvJzl6ZVwphRqHagPxu6Y0tjkAK+t0ErfuBFmZvxX8 fPjqdMhEY53CPyxatGglmG0Owi38yqd5+pIyGEiCb78J5koTs2qVW8lL1K3u3uexy8P/X3YCkK lpA= X-SBRS: 2.7 X-MesageID: 20688223 X-Ironport-Server: esa4.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.73,503,1583211600"; d="scan'208";a="20688223" From: Roger Pau Monne To: Subject: [PATCH for-4.14 8/8] x86/hvm: enable emulated PIT for PVH dom0 Date: Fri, 12 Jun 2020 17:56:40 +0200 Message-ID: <20200612155640.4101-9-roger.pau@citrix.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200612155640.4101-1-roger.pau@citrix.com> References: <20200612155640.4101-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Roger Pau Monne , Wei Liu , Jan Beulich , paul@xen.org Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Some video BIOS require a PIT in order to work properly, hence classic PV dom0 gets partial access to the physical PIT as long as it's not in use by Xen. Since PVH dom0 is built on top of HVM support, there's already an emulated PIT implementation available for use. Tweak the emulated PIT code so it injects interrupts directly into the vIO-APIC if the legacy PIC (i8259) is disabled. Make sure the GSI used matches the ISA IRQ 0 in the likely case there's an interrupt overwrite in the MADT ACPI table. Finally prevent the passthrough of the GSI that belongs to the PIT, since interrupts will be generated by the emulated PIT instead of the physical one. Signed-off-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/domain.c | 5 +++-- xen/arch/x86/emul-i8254.c | 12 +++++++++--- xen/arch/x86/hvm/vioapic.c | 9 ++++++++- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index fee6c3931a..dc0b4c2284 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -512,7 +512,8 @@ static bool emulation_flags_ok(const struct domain *d, = uint32_t emflags) if ( is_hvm_domain(d) ) { if ( is_hardware_domain(d) && - emflags !=3D (X86_EMU_VPCI | X86_EMU_LAPIC | X86_EMU_IOAPIC) ) + emflags !=3D (X86_EMU_VPCI | X86_EMU_LAPIC | X86_EMU_IOAPIC | + X86_EMU_PIT) ) return false; if ( !is_hardware_domain(d) && emflags !=3D (X86_EMU_ALL & ~X86_EMU_VPCI) && @@ -578,7 +579,7 @@ int arch_domain_create(struct domain *d, =20 emflags =3D config->arch.emulation_flags; =20 - if ( is_hardware_domain(d) && is_pv_domain(d) ) + if ( is_hardware_domain(d) ) emflags |=3D XEN_X86_EMU_PIT; =20 if ( emflags & ~XEN_X86_EMU_ALL ) diff --git a/xen/arch/x86/emul-i8254.c b/xen/arch/x86/emul-i8254.c index 73be4188ad..5aef0fe852 100644 --- a/xen/arch/x86/emul-i8254.c +++ b/xen/arch/x86/emul-i8254.c @@ -168,6 +168,7 @@ static void pit_load_count(PITState *pit, int channel, = int val) u32 period; struct hvm_hw_pit_channel *s =3D &pit->hw.channels[channel]; struct vcpu *v =3D vpit_vcpu(pit); + const struct domain *d =3D v ? v->domain : NULL; =20 ASSERT(spin_is_locked(&pit->lock)); =20 @@ -190,14 +191,18 @@ static void pit_load_count(PITState *pit, int channel= , int val) case 3: /* Periodic timer. */ TRACE_2D(TRC_HVM_EMUL_PIT_START_TIMER, period, period); - create_periodic_time(v, &pit->pt0, period, period, 0, pit_time_fir= ed,=20 + create_periodic_time(v, &pit->pt0, period, period, + has_vpic(d) ? 0 : hvm_isa_irq_to_gsi(d, 0), + pit_time_fired, &pit->count_load_time[channel], false); break; case 1: case 4: /* One-shot timer. */ TRACE_2D(TRC_HVM_EMUL_PIT_START_TIMER, period, 0); - create_periodic_time(v, &pit->pt0, period, 0, 0, pit_time_fired, + create_periodic_time(v, &pit->pt0, period, 0, + has_vpic(d) ? 0 : hvm_isa_irq_to_gsi(d, 0), + pit_time_fired, &pit->count_load_time[channel], false); break; default: @@ -455,7 +460,8 @@ void pit_reset(struct domain *d) { TRACE_0D(TRC_HVM_EMUL_PIT_STOP_TIMER); destroy_periodic_time(&pit->pt0); - pit->pt0.source =3D PTSRC_isa; + ASSERT(has_vpic(d) || has_vioapic(d)); + pit->pt0.source =3D has_vpic(d) ? PTSRC_isa : PTSRC_ioapic; } =20 spin_lock(&pit->lock); diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c index 34bec715b7..8b95e4412f 100644 --- a/xen/arch/x86/hvm/vioapic.c +++ b/xen/arch/x86/hvm/vioapic.c @@ -268,7 +268,14 @@ static void vioapic_write_redirent( =20 spin_unlock(&d->arch.hvm.irq_lock); =20 - if ( is_hardware_domain(d) && unmasked ) + if ( is_hardware_domain(d) && unmasked && + /* + * A PVH dom0 can have an emulated PIT that should respect any + * interrupt overwrites found in the ACPI MADT table, so we need = to + * check to which GSI the ISA IRQ 0 is mapped in order to prevent + * identity mapping it. + */ + (!has_vpit(d) || gsi !=3D hvm_isa_irq_to_gsi(d, 0)) ) { /* * NB: don't call vioapic_hwdom_map_gsi while holding hvm.irq_lock --=20 2.26.2